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st: Lower uniforms in st in the !PIPE_CAP_PACKED_UNIFORMS case as well.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/crc32.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "compiler/nir_types.h"
37 #include "nir/tgsi_to_nir.h"
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #include "mesa/state_tracker/st_glsl_types.h"
42
43 static struct qreg
44 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
45 static void
46 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
47
48 static int
49 type_size(const struct glsl_type *type)
50 {
51 return glsl_count_attribute_slots(type, false);
52 }
53
54 static int
55 uniforms_type_size(const struct glsl_type *type)
56 {
57 return st_glsl_storage_type_size(type, false);
58 }
59
60 static void
61 resize_qreg_array(struct vc4_compile *c,
62 struct qreg **regs,
63 uint32_t *size,
64 uint32_t decl_size)
65 {
66 if (*size >= decl_size)
67 return;
68
69 uint32_t old_size = *size;
70 *size = MAX2(*size * 2, decl_size);
71 *regs = reralloc(c, *regs, struct qreg, *size);
72 if (!*regs) {
73 fprintf(stderr, "Malloc failure\n");
74 abort();
75 }
76
77 for (uint32_t i = old_size; i < *size; i++)
78 (*regs)[i] = c->undef;
79 }
80
81 static void
82 ntq_emit_thrsw(struct vc4_compile *c)
83 {
84 if (!c->fs_threaded)
85 return;
86
87 /* Always thread switch after each texture operation for now.
88 *
89 * We could do better by batching a bunch of texture fetches up and
90 * then doing one thread switch and collecting all their results
91 * afterward.
92 */
93 qir_emit_nondef(c, qir_inst(QOP_THRSW, c->undef,
94 c->undef, c->undef));
95 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
96 }
97
98 static struct qreg
99 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
100 {
101 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
102 uint32_t offset = nir_intrinsic_base(intr);
103 struct vc4_compiler_ubo_range *range = NULL;
104 unsigned i;
105 for (i = 0; i < c->num_uniform_ranges; i++) {
106 range = &c->ubo_ranges[i];
107 if (offset >= range->src_offset &&
108 offset < range->src_offset + range->size) {
109 break;
110 }
111 }
112 /* The driver-location-based offset always has to be within a declared
113 * uniform range.
114 */
115 assert(range);
116 if (!range->used) {
117 range->used = true;
118 range->dst_offset = c->next_ubo_dst_offset;
119 c->next_ubo_dst_offset += range->size;
120 c->num_ubo_ranges++;
121 }
122
123 offset -= range->src_offset;
124
125 /* Adjust for where we stored the TGSI register base. */
126 indirect_offset = qir_ADD(c, indirect_offset,
127 qir_uniform_ui(c, (range->dst_offset +
128 offset)));
129
130 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
131 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
132 indirect_offset = qir_MIN_NOIMM(c, indirect_offset,
133 qir_uniform_ui(c, (range->dst_offset +
134 range->size - 4)));
135
136 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
137 indirect_offset,
138 qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
139
140 c->num_texture_samples++;
141
142 ntq_emit_thrsw(c);
143
144 return qir_TEX_RESULT(c);
145 }
146
147 static struct qreg
148 vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
149 {
150 unsigned buffer_index = nir_src_as_uint(intr->src[0]);
151 assert(buffer_index == 1);
152 assert(c->stage == QSTAGE_FRAG);
153
154 struct qreg offset = ntq_get_src(c, intr->src[1], 0);
155
156 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
157 offset = qir_MAX(c, offset, qir_uniform_ui(c, 0));
158 offset = qir_MIN_NOIMM(c, offset,
159 qir_uniform_ui(c, c->fs_key->ubo_1_size - 4));
160
161 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
162 offset,
163 qir_uniform(c, QUNIFORM_UBO_ADDR, buffer_index));
164
165 c->num_texture_samples++;
166
167 ntq_emit_thrsw(c);
168
169 return qir_TEX_RESULT(c);
170 }
171
172 nir_ssa_def *
173 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
174 {
175 switch (swiz) {
176 default:
177 case PIPE_SWIZZLE_NONE:
178 fprintf(stderr, "warning: unknown swizzle\n");
179 /* FALLTHROUGH */
180 case PIPE_SWIZZLE_0:
181 return nir_imm_float(b, 0.0);
182 case PIPE_SWIZZLE_1:
183 return nir_imm_float(b, 1.0);
184 case PIPE_SWIZZLE_X:
185 case PIPE_SWIZZLE_Y:
186 case PIPE_SWIZZLE_Z:
187 case PIPE_SWIZZLE_W:
188 return srcs[swiz];
189 }
190 }
191
192 static struct qreg *
193 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
194 {
195 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
196 def->num_components);
197 _mesa_hash_table_insert(c->def_ht, def, qregs);
198 return qregs;
199 }
200
201 /**
202 * This function is responsible for getting QIR results into the associated
203 * storage for a NIR instruction.
204 *
205 * If it's a NIR SSA def, then we just set the associated hash table entry to
206 * the new result.
207 *
208 * If it's a NIR reg, then we need to update the existing qreg assigned to the
209 * NIR destination with the incoming value. To do that without introducing
210 * new MOVs, we require that the incoming qreg either be a uniform, or be
211 * SSA-defined by the previous QIR instruction in the block and rewritable by
212 * this function. That lets us sneak ahead and insert the SF flag beforehand
213 * (knowing that the previous instruction doesn't depend on flags) and rewrite
214 * its destination to be the NIR reg's destination
215 */
216 static void
217 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
218 struct qreg result)
219 {
220 struct qinst *last_inst = NULL;
221 if (!list_empty(&c->cur_block->instructions))
222 last_inst = (struct qinst *)c->cur_block->instructions.prev;
223
224 assert(result.file == QFILE_UNIF ||
225 (result.file == QFILE_TEMP &&
226 last_inst && last_inst == c->defs[result.index]));
227
228 if (dest->is_ssa) {
229 assert(chan < dest->ssa.num_components);
230
231 struct qreg *qregs;
232 struct hash_entry *entry =
233 _mesa_hash_table_search(c->def_ht, &dest->ssa);
234
235 if (entry)
236 qregs = entry->data;
237 else
238 qregs = ntq_init_ssa_def(c, &dest->ssa);
239
240 qregs[chan] = result;
241 } else {
242 nir_register *reg = dest->reg.reg;
243 assert(dest->reg.base_offset == 0);
244 assert(reg->num_array_elems == 0);
245 struct hash_entry *entry =
246 _mesa_hash_table_search(c->def_ht, reg);
247 struct qreg *qregs = entry->data;
248
249 /* Insert a MOV if the source wasn't an SSA def in the
250 * previous instruction.
251 */
252 if (result.file == QFILE_UNIF) {
253 result = qir_MOV(c, result);
254 last_inst = c->defs[result.index];
255 }
256
257 /* We know they're both temps, so just rewrite index. */
258 c->defs[last_inst->dst.index] = NULL;
259 last_inst->dst.index = qregs[chan].index;
260
261 /* If we're in control flow, then make this update of the reg
262 * conditional on the execution mask.
263 */
264 if (c->execute.file != QFILE_NULL) {
265 last_inst->dst.index = qregs[chan].index;
266
267 /* Set the flags to the current exec mask. To insert
268 * the SF, we temporarily remove our SSA instruction.
269 */
270 list_del(&last_inst->link);
271 qir_SF(c, c->execute);
272 list_addtail(&last_inst->link,
273 &c->cur_block->instructions);
274
275 last_inst->cond = QPU_COND_ZS;
276 last_inst->cond_is_exec_mask = true;
277 }
278 }
279 }
280
281 static struct qreg *
282 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
283 {
284 if (dest->is_ssa) {
285 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
286 for (int i = 0; i < dest->ssa.num_components; i++)
287 qregs[i] = c->undef;
288 return qregs;
289 } else {
290 nir_register *reg = dest->reg.reg;
291 assert(dest->reg.base_offset == 0);
292 assert(reg->num_array_elems == 0);
293 struct hash_entry *entry =
294 _mesa_hash_table_search(c->def_ht, reg);
295 return entry->data;
296 }
297 }
298
299 static struct qreg
300 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
301 {
302 struct hash_entry *entry;
303 if (src.is_ssa) {
304 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
305 assert(i < src.ssa->num_components);
306 } else {
307 nir_register *reg = src.reg.reg;
308 entry = _mesa_hash_table_search(c->def_ht, reg);
309 assert(reg->num_array_elems == 0);
310 assert(src.reg.base_offset == 0);
311 assert(i < reg->num_components);
312 }
313
314 struct qreg *qregs = entry->data;
315 return qregs[i];
316 }
317
318 static struct qreg
319 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
320 unsigned src)
321 {
322 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
323 unsigned chan = ffs(instr->dest.write_mask) - 1;
324 struct qreg r = ntq_get_src(c, instr->src[src].src,
325 instr->src[src].swizzle[chan]);
326
327 assert(!instr->src[src].abs);
328 assert(!instr->src[src].negate);
329
330 return r;
331 };
332
333 static inline struct qreg
334 qir_SAT(struct vc4_compile *c, struct qreg val)
335 {
336 return qir_FMAX(c,
337 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
338 qir_uniform_f(c, 0.0));
339 }
340
341 static struct qreg
342 ntq_rcp(struct vc4_compile *c, struct qreg x)
343 {
344 struct qreg r = qir_RCP(c, x);
345
346 /* Apply a Newton-Raphson step to improve the accuracy. */
347 r = qir_FMUL(c, r, qir_FSUB(c,
348 qir_uniform_f(c, 2.0),
349 qir_FMUL(c, x, r)));
350
351 return r;
352 }
353
354 static struct qreg
355 ntq_rsq(struct vc4_compile *c, struct qreg x)
356 {
357 struct qreg r = qir_RSQ(c, x);
358
359 /* Apply a Newton-Raphson step to improve the accuracy. */
360 r = qir_FMUL(c, r, qir_FSUB(c,
361 qir_uniform_f(c, 1.5),
362 qir_FMUL(c,
363 qir_uniform_f(c, 0.5),
364 qir_FMUL(c, x,
365 qir_FMUL(c, r, r)))));
366
367 return r;
368 }
369
370 static struct qreg
371 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
372 {
373 struct qreg src0_hi = qir_SHR(c, src0,
374 qir_uniform_ui(c, 24));
375 struct qreg src1_hi = qir_SHR(c, src1,
376 qir_uniform_ui(c, 24));
377
378 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
379 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
380 struct qreg lolo = qir_MUL24(c, src0, src1);
381
382 return qir_ADD(c, lolo, qir_SHL(c,
383 qir_ADD(c, hilo, lohi),
384 qir_uniform_ui(c, 24)));
385 }
386
387 static struct qreg
388 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
389 {
390 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
391 qir_uniform_ui(c, 8)));
392 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
393 }
394
395 /**
396 * Emits a lowered TXF_MS from an MSAA texture.
397 *
398 * The addressing math has been lowered in NIR, and now we just need to read
399 * it like a UBO.
400 */
401 static void
402 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
403 {
404 uint32_t tile_width = 32;
405 uint32_t tile_height = 32;
406 uint32_t tile_size = (tile_height * tile_width *
407 VC4_MAX_SAMPLES * sizeof(uint32_t));
408
409 unsigned unit = instr->texture_index;
410 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
411 uint32_t w_tiles = w / tile_width;
412 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
413 uint32_t h_tiles = h / tile_height;
414 uint32_t size = w_tiles * h_tiles * tile_size;
415
416 struct qreg addr;
417 assert(instr->num_srcs == 1);
418 assert(instr->src[0].src_type == nir_tex_src_coord);
419 addr = ntq_get_src(c, instr->src[0].src, 0);
420
421 /* Perform the clamping required by kernel validation. */
422 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
423 addr = qir_MIN_NOIMM(c, addr, qir_uniform_ui(c, size - 4));
424
425 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
426 addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
427
428 ntq_emit_thrsw(c);
429
430 struct qreg tex = qir_TEX_RESULT(c);
431 c->num_texture_samples++;
432
433 enum pipe_format format = c->key->tex[unit].format;
434 if (util_format_is_depth_or_stencil(format)) {
435 struct qreg scaled = ntq_scale_depth_texture(c, tex);
436 for (int i = 0; i < 4; i++)
437 ntq_store_dest(c, &instr->dest, i, qir_MOV(c, scaled));
438 } else {
439 for (int i = 0; i < 4; i++)
440 ntq_store_dest(c, &instr->dest, i,
441 qir_UNPACK_8_F(c, tex, i));
442 }
443 }
444
445 static void
446 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
447 {
448 struct qreg s, t, r, lod, compare;
449 bool is_txb = false, is_txl = false;
450 unsigned unit = instr->texture_index;
451
452 if (instr->op == nir_texop_txf) {
453 ntq_emit_txf(c, instr);
454 return;
455 }
456
457 for (unsigned i = 0; i < instr->num_srcs; i++) {
458 switch (instr->src[i].src_type) {
459 case nir_tex_src_coord:
460 s = ntq_get_src(c, instr->src[i].src, 0);
461 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
462 t = qir_uniform_f(c, 0.5);
463 else
464 t = ntq_get_src(c, instr->src[i].src, 1);
465 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
466 r = ntq_get_src(c, instr->src[i].src, 2);
467 break;
468 case nir_tex_src_bias:
469 lod = ntq_get_src(c, instr->src[i].src, 0);
470 is_txb = true;
471 break;
472 case nir_tex_src_lod:
473 lod = ntq_get_src(c, instr->src[i].src, 0);
474 is_txl = true;
475 break;
476 case nir_tex_src_comparator:
477 compare = ntq_get_src(c, instr->src[i].src, 0);
478 break;
479 default:
480 unreachable("unknown texture source");
481 }
482 }
483
484 if (c->stage != QSTAGE_FRAG && !is_txl) {
485 /* From the GLSL 1.20 spec:
486 *
487 * "If it is mip-mapped and running on the vertex shader,
488 * then the base texture is used."
489 */
490 is_txl = true;
491 lod = qir_uniform_ui(c, 0);
492 }
493
494 if (c->key->tex[unit].force_first_level) {
495 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
496 is_txl = true;
497 is_txb = false;
498 }
499
500 struct qreg texture_u[] = {
501 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
502 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
503 qir_uniform(c, QUNIFORM_CONSTANT, 0),
504 qir_uniform(c, QUNIFORM_CONSTANT, 0),
505 };
506 uint32_t next_texture_u = 0;
507
508 /* There is no native support for GL texture rectangle coordinates, so
509 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
510 * 1]).
511 */
512 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
513 s = qir_FMUL(c, s,
514 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
515 t = qir_FMUL(c, t,
516 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
517 }
518
519 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
520 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
521 unit | (is_txl << 16));
522 }
523
524 struct qinst *tmu;
525 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
526 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), r);
527 tmu->src[qir_get_tex_uniform_src(tmu)] =
528 texture_u[next_texture_u++];
529 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
530 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
531 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
532 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
533 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0),
534 qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR,
535 unit));
536 tmu->src[qir_get_tex_uniform_src(tmu)] =
537 texture_u[next_texture_u++];
538 }
539
540 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
541 s = qir_SAT(c, s);
542 }
543
544 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
545 t = qir_SAT(c, t);
546 }
547
548 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_T, 0), t);
549 tmu->src[qir_get_tex_uniform_src(tmu)] =
550 texture_u[next_texture_u++];
551
552 if (is_txl || is_txb) {
553 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_B, 0), lod);
554 tmu->src[qir_get_tex_uniform_src(tmu)] =
555 texture_u[next_texture_u++];
556 }
557
558 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_S, 0), s);
559 tmu->src[qir_get_tex_uniform_src(tmu)] = texture_u[next_texture_u++];
560
561 c->num_texture_samples++;
562
563 ntq_emit_thrsw(c);
564
565 struct qreg tex = qir_TEX_RESULT(c);
566
567 enum pipe_format format = c->key->tex[unit].format;
568
569 struct qreg *dest = ntq_get_dest(c, &instr->dest);
570 if (util_format_is_depth_or_stencil(format)) {
571 struct qreg normalized = ntq_scale_depth_texture(c, tex);
572 struct qreg depth_output;
573
574 struct qreg u0 = qir_uniform_f(c, 0.0f);
575 struct qreg u1 = qir_uniform_f(c, 1.0f);
576 if (c->key->tex[unit].compare_mode) {
577 /* From the GL_ARB_shadow spec:
578 *
579 * "Let Dt (D subscript t) be the depth texture
580 * value, in the range [0, 1]. Let R be the
581 * interpolated texture coordinate clamped to the
582 * range [0, 1]."
583 */
584 compare = qir_SAT(c, compare);
585
586 switch (c->key->tex[unit].compare_func) {
587 case PIPE_FUNC_NEVER:
588 depth_output = qir_uniform_f(c, 0.0f);
589 break;
590 case PIPE_FUNC_ALWAYS:
591 depth_output = u1;
592 break;
593 case PIPE_FUNC_EQUAL:
594 qir_SF(c, qir_FSUB(c, compare, normalized));
595 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
596 break;
597 case PIPE_FUNC_NOTEQUAL:
598 qir_SF(c, qir_FSUB(c, compare, normalized));
599 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
600 break;
601 case PIPE_FUNC_GREATER:
602 qir_SF(c, qir_FSUB(c, compare, normalized));
603 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
604 break;
605 case PIPE_FUNC_GEQUAL:
606 qir_SF(c, qir_FSUB(c, normalized, compare));
607 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
608 break;
609 case PIPE_FUNC_LESS:
610 qir_SF(c, qir_FSUB(c, compare, normalized));
611 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
612 break;
613 case PIPE_FUNC_LEQUAL:
614 qir_SF(c, qir_FSUB(c, normalized, compare));
615 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
616 break;
617 }
618 } else {
619 depth_output = normalized;
620 }
621
622 for (int i = 0; i < 4; i++)
623 dest[i] = depth_output;
624 } else {
625 for (int i = 0; i < 4; i++)
626 dest[i] = qir_UNPACK_8_F(c, tex, i);
627 }
628 }
629
630 /**
631 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
632 * to zero).
633 */
634 static struct qreg
635 ntq_ffract(struct vc4_compile *c, struct qreg src)
636 {
637 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
638 struct qreg diff = qir_FSUB(c, src, trunc);
639 qir_SF(c, diff);
640
641 qir_FADD_dest(c, diff,
642 diff, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
643
644 return qir_MOV(c, diff);
645 }
646
647 /**
648 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
649 * zero).
650 */
651 static struct qreg
652 ntq_ffloor(struct vc4_compile *c, struct qreg src)
653 {
654 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
655
656 /* This will be < 0 if we truncated and the truncation was of a value
657 * that was < 0 in the first place.
658 */
659 qir_SF(c, qir_FSUB(c, src, result));
660
661 struct qinst *sub = qir_FSUB_dest(c, result,
662 result, qir_uniform_f(c, 1.0));
663 sub->cond = QPU_COND_NS;
664
665 return qir_MOV(c, result);
666 }
667
668 /**
669 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
670 * zero).
671 */
672 static struct qreg
673 ntq_fceil(struct vc4_compile *c, struct qreg src)
674 {
675 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
676
677 /* This will be < 0 if we truncated and the truncation was of a value
678 * that was > 0 in the first place.
679 */
680 qir_SF(c, qir_FSUB(c, result, src));
681
682 qir_FADD_dest(c, result,
683 result, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
684
685 return qir_MOV(c, result);
686 }
687
688 static struct qreg
689 ntq_shrink_sincos_input_range(struct vc4_compile *c, struct qreg x)
690 {
691 /* Since we're using a Taylor approximation, we want to have a small
692 * number of coefficients and take advantage of sin/cos repeating
693 * every 2pi. We keep our x as close to 0 as we can, since the series
694 * will be less accurate as |x| increases. (Also, be careful of
695 * shifting the input x value to be tricky with sin/cos relations,
696 * because getting accurate values for x==0 is very important for SDL
697 * rendering)
698 */
699 struct qreg scaled_x =
700 qir_FMUL(c, x,
701 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
702 /* Note: FTOI truncates toward 0. */
703 struct qreg x_frac = qir_FSUB(c, scaled_x,
704 qir_ITOF(c, qir_FTOI(c, scaled_x)));
705 /* Map [0.5, 1] to [-0.5, 0] */
706 qir_SF(c, qir_FSUB(c, x_frac, qir_uniform_f(c, 0.5)));
707 qir_FSUB_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NC;
708 /* Map [-1, -0.5] to [0, 0.5] */
709 qir_SF(c, qir_FADD(c, x_frac, qir_uniform_f(c, 0.5)));
710 qir_FADD_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
711
712 return x_frac;
713 }
714
715 static struct qreg
716 ntq_fsin(struct vc4_compile *c, struct qreg src)
717 {
718 float coeff[] = {
719 2.0 * M_PI,
720 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
721 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
722 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
723 pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
724 };
725
726 struct qreg x = ntq_shrink_sincos_input_range(c, src);
727 struct qreg x2 = qir_FMUL(c, x, x);
728 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
729 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
730 x = qir_FMUL(c, x, x2);
731 sum = qir_FADD(c,
732 sum,
733 qir_FMUL(c,
734 x,
735 qir_uniform_f(c, coeff[i])));
736 }
737 return sum;
738 }
739
740 static struct qreg
741 ntq_fcos(struct vc4_compile *c, struct qreg src)
742 {
743 float coeff[] = {
744 1.0f,
745 -pow(2.0 * M_PI, 2) / (2 * 1),
746 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
747 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
748 pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
749 -pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
750 };
751
752 struct qreg x_frac = ntq_shrink_sincos_input_range(c, src);
753 struct qreg sum = qir_uniform_f(c, coeff[0]);
754 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
755 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
756 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
757 if (i != 1)
758 x = qir_FMUL(c, x, x2);
759
760 sum = qir_FADD(c, qir_FMUL(c,
761 x,
762 qir_uniform_f(c, coeff[i])),
763 sum);
764 }
765 return sum;
766 }
767
768 static struct qreg
769 ntq_fsign(struct vc4_compile *c, struct qreg src)
770 {
771 struct qreg t = qir_get_temp(c);
772
773 qir_SF(c, src);
774 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
775 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
776 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
777 return qir_MOV(c, t);
778 }
779
780 static void
781 emit_vertex_input(struct vc4_compile *c, int attr)
782 {
783 enum pipe_format format = c->vs_key->attr_formats[attr];
784 uint32_t attr_size = util_format_get_blocksize(format);
785
786 c->vattr_sizes[attr] = align(attr_size, 4);
787 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
788 c->inputs[attr * 4 + i] =
789 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
790 c->num_inputs++;
791 }
792 }
793
794 static void
795 emit_fragcoord_input(struct vc4_compile *c, int attr)
796 {
797 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
798 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
799 c->inputs[attr * 4 + 2] =
800 qir_FMUL(c,
801 qir_ITOF(c, qir_FRAG_Z(c)),
802 qir_uniform_f(c, 1.0 / 0xffffff));
803 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
804 }
805
806 static struct qreg
807 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
808 uint8_t swizzle)
809 {
810 uint32_t i = c->num_input_slots++;
811 struct qreg vary = {
812 QFILE_VARY,
813 i
814 };
815
816 if (c->num_input_slots >= c->input_slots_array_size) {
817 c->input_slots_array_size =
818 MAX2(4, c->input_slots_array_size * 2);
819
820 c->input_slots = reralloc(c, c->input_slots,
821 struct vc4_varying_slot,
822 c->input_slots_array_size);
823 }
824
825 c->input_slots[i].slot = slot;
826 c->input_slots[i].swizzle = swizzle;
827
828 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
829 }
830
831 static void
832 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
833 {
834 for (int i = 0; i < 4; i++) {
835 c->inputs[attr * 4 + i] =
836 emit_fragment_varying(c, slot, i);
837 c->num_inputs++;
838 }
839 }
840
841 static void
842 add_output(struct vc4_compile *c,
843 uint32_t decl_offset,
844 uint8_t slot,
845 uint8_t swizzle)
846 {
847 uint32_t old_array_size = c->outputs_array_size;
848 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
849 decl_offset + 1);
850
851 if (old_array_size != c->outputs_array_size) {
852 c->output_slots = reralloc(c,
853 c->output_slots,
854 struct vc4_varying_slot,
855 c->outputs_array_size);
856 }
857
858 c->output_slots[decl_offset].slot = slot;
859 c->output_slots[decl_offset].swizzle = swizzle;
860 }
861
862 static void
863 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
864 {
865 unsigned array_id = c->num_uniform_ranges++;
866 if (array_id >= c->ubo_ranges_array_size) {
867 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
868 array_id + 1);
869 c->ubo_ranges = reralloc(c, c->ubo_ranges,
870 struct vc4_compiler_ubo_range,
871 c->ubo_ranges_array_size);
872 }
873
874 c->ubo_ranges[array_id].dst_offset = 0;
875 c->ubo_ranges[array_id].src_offset = start;
876 c->ubo_ranges[array_id].size = size;
877 c->ubo_ranges[array_id].used = false;
878 }
879
880 static bool
881 ntq_src_is_only_ssa_def_user(nir_src *src)
882 {
883 if (!src->is_ssa)
884 return false;
885
886 if (!list_empty(&src->ssa->if_uses))
887 return false;
888
889 return (src->ssa->uses.next == &src->use_link &&
890 src->ssa->uses.next->next == &src->ssa->uses);
891 }
892
893 /**
894 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
895 * bit set.
896 *
897 * However, as an optimization, it tries to find the instructions generating
898 * the sources to be packed and just emit the pack flag there, if possible.
899 */
900 static void
901 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
902 {
903 struct qreg result = qir_get_temp(c);
904 struct nir_alu_instr *vec4 = NULL;
905
906 /* If packing from a vec4 op (as expected), identify it so that we can
907 * peek back at what generated its sources.
908 */
909 if (instr->src[0].src.is_ssa &&
910 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
911 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
912 nir_op_vec4) {
913 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
914 }
915
916 /* If the pack is replicating the same channel 4 times, use the 8888
917 * pack flag. This is common for blending using the alpha
918 * channel.
919 */
920 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
921 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
922 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
923 struct qreg rep = ntq_get_src(c,
924 instr->src[0].src,
925 instr->src[0].swizzle[0]);
926 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
927 return;
928 }
929
930 for (int i = 0; i < 4; i++) {
931 int swiz = instr->src[0].swizzle[i];
932 struct qreg src;
933 if (vec4) {
934 src = ntq_get_src(c, vec4->src[swiz].src,
935 vec4->src[swiz].swizzle[0]);
936 } else {
937 src = ntq_get_src(c, instr->src[0].src, swiz);
938 }
939
940 if (vec4 &&
941 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
942 src.file == QFILE_TEMP &&
943 c->defs[src.index] &&
944 qir_is_mul(c->defs[src.index]) &&
945 !c->defs[src.index]->dst.pack) {
946 struct qinst *rewrite = c->defs[src.index];
947 c->defs[src.index] = NULL;
948 rewrite->dst = result;
949 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
950 continue;
951 }
952
953 qir_PACK_8_F(c, result, src, i);
954 }
955
956 ntq_store_dest(c, &instr->dest.dest, 0, qir_MOV(c, result));
957 }
958
959 /** Handles sign-extended bitfield extracts for 16 bits. */
960 static struct qreg
961 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
962 struct qreg bits)
963 {
964 assert(bits.file == QFILE_UNIF &&
965 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
966 c->uniform_data[bits.index] == 16);
967
968 assert(offset.file == QFILE_UNIF &&
969 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
970 int offset_bit = c->uniform_data[offset.index];
971 assert(offset_bit % 16 == 0);
972
973 return qir_UNPACK_16_I(c, base, offset_bit / 16);
974 }
975
976 /** Handles unsigned bitfield extracts for 8 bits. */
977 static struct qreg
978 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
979 struct qreg bits)
980 {
981 assert(bits.file == QFILE_UNIF &&
982 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
983 c->uniform_data[bits.index] == 8);
984
985 assert(offset.file == QFILE_UNIF &&
986 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
987 int offset_bit = c->uniform_data[offset.index];
988 assert(offset_bit % 8 == 0);
989
990 return qir_UNPACK_8_I(c, base, offset_bit / 8);
991 }
992
993 /**
994 * If compare_instr is a valid comparison instruction, emits the
995 * compare_instr's comparison and returns the sel_instr's return value based
996 * on the compare_instr's result.
997 */
998 static bool
999 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
1000 nir_alu_instr *compare_instr,
1001 nir_alu_instr *sel_instr)
1002 {
1003 enum qpu_cond cond;
1004
1005 switch (compare_instr->op) {
1006 case nir_op_feq32:
1007 case nir_op_ieq32:
1008 case nir_op_seq:
1009 cond = QPU_COND_ZS;
1010 break;
1011 case nir_op_fne32:
1012 case nir_op_ine32:
1013 case nir_op_sne:
1014 cond = QPU_COND_ZC;
1015 break;
1016 case nir_op_fge32:
1017 case nir_op_ige32:
1018 case nir_op_uge32:
1019 case nir_op_sge:
1020 cond = QPU_COND_NC;
1021 break;
1022 case nir_op_flt32:
1023 case nir_op_ilt32:
1024 case nir_op_slt:
1025 cond = QPU_COND_NS;
1026 break;
1027 default:
1028 return false;
1029 }
1030
1031 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
1032 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
1033
1034 unsigned unsized_type =
1035 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
1036 if (unsized_type == nir_type_float)
1037 qir_SF(c, qir_FSUB(c, src0, src1));
1038 else
1039 qir_SF(c, qir_SUB(c, src0, src1));
1040
1041 switch (sel_instr->op) {
1042 case nir_op_seq:
1043 case nir_op_sne:
1044 case nir_op_sge:
1045 case nir_op_slt:
1046 *dest = qir_SEL(c, cond,
1047 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
1048 break;
1049
1050 case nir_op_b32csel:
1051 *dest = qir_SEL(c, cond,
1052 ntq_get_alu_src(c, sel_instr, 1),
1053 ntq_get_alu_src(c, sel_instr, 2));
1054 break;
1055
1056 default:
1057 *dest = qir_SEL(c, cond,
1058 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
1059 break;
1060 }
1061
1062 /* Make the temporary for nir_store_dest(). */
1063 *dest = qir_MOV(c, *dest);
1064
1065 return true;
1066 }
1067
1068 /**
1069 * Attempts to fold a comparison generating a boolean result into the
1070 * condition code for selecting between two values, instead of comparing the
1071 * boolean result against 0 to generate the condition code.
1072 */
1073 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
1074 struct qreg *src)
1075 {
1076 if (!instr->src[0].src.is_ssa)
1077 goto out;
1078 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
1079 goto out;
1080 nir_alu_instr *compare =
1081 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
1082 if (!compare)
1083 goto out;
1084
1085 struct qreg dest;
1086 if (ntq_emit_comparison(c, &dest, compare, instr))
1087 return dest;
1088
1089 out:
1090 qir_SF(c, src[0]);
1091 return qir_MOV(c, qir_SEL(c, QPU_COND_NS, src[1], src[2]));
1092 }
1093
1094 static struct qreg
1095 ntq_fddx(struct vc4_compile *c, struct qreg src)
1096 {
1097 /* Make sure that we have a bare temp to use for MUL rotation, so it
1098 * can be allocated to an accumulator.
1099 */
1100 if (src.pack || src.file != QFILE_TEMP)
1101 src = qir_MOV(c, src);
1102
1103 struct qreg from_left = qir_ROT_MUL(c, src, 1);
1104 struct qreg from_right = qir_ROT_MUL(c, src, 15);
1105
1106 /* Distinguish left/right pixels of the quad. */
1107 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
1108 qir_uniform_ui(c, 1)));
1109
1110 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1111 qir_FSUB(c, from_right, src),
1112 qir_FSUB(c, src, from_left)));
1113 }
1114
1115 static struct qreg
1116 ntq_fddy(struct vc4_compile *c, struct qreg src)
1117 {
1118 if (src.pack || src.file != QFILE_TEMP)
1119 src = qir_MOV(c, src);
1120
1121 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
1122 struct qreg from_top = qir_ROT_MUL(c, src, 14);
1123
1124 /* Distinguish top/bottom pixels of the quad. */
1125 qir_SF(c, qir_AND(c,
1126 qir_reg(QFILE_QPU_ELEMENT, 0),
1127 qir_uniform_ui(c, 2)));
1128
1129 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1130 qir_FSUB(c, from_top, src),
1131 qir_FSUB(c, src, from_bottom)));
1132 }
1133
1134 static void
1135 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
1136 {
1137 /* This should always be lowered to ALU operations for VC4. */
1138 assert(!instr->dest.saturate);
1139
1140 /* Vectors are special in that they have non-scalarized writemasks,
1141 * and just take the first swizzle channel for each argument in order
1142 * into each writemask channel.
1143 */
1144 if (instr->op == nir_op_vec2 ||
1145 instr->op == nir_op_vec3 ||
1146 instr->op == nir_op_vec4) {
1147 struct qreg srcs[4];
1148 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1149 srcs[i] = ntq_get_src(c, instr->src[i].src,
1150 instr->src[i].swizzle[0]);
1151 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1152 ntq_store_dest(c, &instr->dest.dest, i,
1153 qir_MOV(c, srcs[i]));
1154 return;
1155 }
1156
1157 if (instr->op == nir_op_pack_unorm_4x8) {
1158 ntq_emit_pack_unorm_4x8(c, instr);
1159 return;
1160 }
1161
1162 if (instr->op == nir_op_unpack_unorm_4x8) {
1163 struct qreg src = ntq_get_src(c, instr->src[0].src,
1164 instr->src[0].swizzle[0]);
1165 for (int i = 0; i < 4; i++) {
1166 if (instr->dest.write_mask & (1 << i))
1167 ntq_store_dest(c, &instr->dest.dest, i,
1168 qir_UNPACK_8_F(c, src, i));
1169 }
1170 return;
1171 }
1172
1173 /* General case: We can just grab the one used channel per src. */
1174 struct qreg src[nir_op_infos[instr->op].num_inputs];
1175 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1176 src[i] = ntq_get_alu_src(c, instr, i);
1177 }
1178
1179 struct qreg result;
1180
1181 switch (instr->op) {
1182 case nir_op_fmov:
1183 case nir_op_imov:
1184 result = qir_MOV(c, src[0]);
1185 break;
1186 case nir_op_fmul:
1187 result = qir_FMUL(c, src[0], src[1]);
1188 break;
1189 case nir_op_fadd:
1190 result = qir_FADD(c, src[0], src[1]);
1191 break;
1192 case nir_op_fsub:
1193 result = qir_FSUB(c, src[0], src[1]);
1194 break;
1195 case nir_op_fmin:
1196 result = qir_FMIN(c, src[0], src[1]);
1197 break;
1198 case nir_op_fmax:
1199 result = qir_FMAX(c, src[0], src[1]);
1200 break;
1201
1202 case nir_op_f2i32:
1203 case nir_op_f2u32:
1204 result = qir_FTOI(c, src[0]);
1205 break;
1206 case nir_op_i2f32:
1207 case nir_op_u2f32:
1208 result = qir_ITOF(c, src[0]);
1209 break;
1210 case nir_op_b2f32:
1211 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1212 break;
1213 case nir_op_b2i32:
1214 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1215 break;
1216 case nir_op_i2b32:
1217 case nir_op_f2b32:
1218 qir_SF(c, src[0]);
1219 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC,
1220 qir_uniform_ui(c, ~0),
1221 qir_uniform_ui(c, 0)));
1222 break;
1223
1224 case nir_op_iadd:
1225 result = qir_ADD(c, src[0], src[1]);
1226 break;
1227 case nir_op_ushr:
1228 result = qir_SHR(c, src[0], src[1]);
1229 break;
1230 case nir_op_isub:
1231 result = qir_SUB(c, src[0], src[1]);
1232 break;
1233 case nir_op_ishr:
1234 result = qir_ASR(c, src[0], src[1]);
1235 break;
1236 case nir_op_ishl:
1237 result = qir_SHL(c, src[0], src[1]);
1238 break;
1239 case nir_op_imin:
1240 result = qir_MIN(c, src[0], src[1]);
1241 break;
1242 case nir_op_imax:
1243 result = qir_MAX(c, src[0], src[1]);
1244 break;
1245 case nir_op_iand:
1246 result = qir_AND(c, src[0], src[1]);
1247 break;
1248 case nir_op_ior:
1249 result = qir_OR(c, src[0], src[1]);
1250 break;
1251 case nir_op_ixor:
1252 result = qir_XOR(c, src[0], src[1]);
1253 break;
1254 case nir_op_inot:
1255 result = qir_NOT(c, src[0]);
1256 break;
1257
1258 case nir_op_imul:
1259 result = ntq_umul(c, src[0], src[1]);
1260 break;
1261
1262 case nir_op_seq:
1263 case nir_op_sne:
1264 case nir_op_sge:
1265 case nir_op_slt:
1266 case nir_op_feq32:
1267 case nir_op_fne32:
1268 case nir_op_fge32:
1269 case nir_op_flt32:
1270 case nir_op_ieq32:
1271 case nir_op_ine32:
1272 case nir_op_ige32:
1273 case nir_op_uge32:
1274 case nir_op_ilt32:
1275 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1276 fprintf(stderr, "Bad comparison instruction\n");
1277 }
1278 break;
1279
1280 case nir_op_b32csel:
1281 result = ntq_emit_bcsel(c, instr, src);
1282 break;
1283 case nir_op_fcsel:
1284 qir_SF(c, src[0]);
1285 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC, src[1], src[2]));
1286 break;
1287
1288 case nir_op_frcp:
1289 result = ntq_rcp(c, src[0]);
1290 break;
1291 case nir_op_frsq:
1292 result = ntq_rsq(c, src[0]);
1293 break;
1294 case nir_op_fexp2:
1295 result = qir_EXP2(c, src[0]);
1296 break;
1297 case nir_op_flog2:
1298 result = qir_LOG2(c, src[0]);
1299 break;
1300
1301 case nir_op_ftrunc:
1302 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1303 break;
1304 case nir_op_fceil:
1305 result = ntq_fceil(c, src[0]);
1306 break;
1307 case nir_op_ffract:
1308 result = ntq_ffract(c, src[0]);
1309 break;
1310 case nir_op_ffloor:
1311 result = ntq_ffloor(c, src[0]);
1312 break;
1313
1314 case nir_op_fsin:
1315 result = ntq_fsin(c, src[0]);
1316 break;
1317 case nir_op_fcos:
1318 result = ntq_fcos(c, src[0]);
1319 break;
1320
1321 case nir_op_fsign:
1322 result = ntq_fsign(c, src[0]);
1323 break;
1324
1325 case nir_op_fabs:
1326 result = qir_FMAXABS(c, src[0], src[0]);
1327 break;
1328 case nir_op_iabs:
1329 result = qir_MAX(c, src[0],
1330 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1331 break;
1332
1333 case nir_op_ibitfield_extract:
1334 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1335 break;
1336
1337 case nir_op_ubitfield_extract:
1338 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1339 break;
1340
1341 case nir_op_usadd_4x8:
1342 result = qir_V8ADDS(c, src[0], src[1]);
1343 break;
1344
1345 case nir_op_ussub_4x8:
1346 result = qir_V8SUBS(c, src[0], src[1]);
1347 break;
1348
1349 case nir_op_umin_4x8:
1350 result = qir_V8MIN(c, src[0], src[1]);
1351 break;
1352
1353 case nir_op_umax_4x8:
1354 result = qir_V8MAX(c, src[0], src[1]);
1355 break;
1356
1357 case nir_op_umul_unorm_4x8:
1358 result = qir_V8MULD(c, src[0], src[1]);
1359 break;
1360
1361 case nir_op_fddx:
1362 case nir_op_fddx_coarse:
1363 case nir_op_fddx_fine:
1364 result = ntq_fddx(c, src[0]);
1365 break;
1366
1367 case nir_op_fddy:
1368 case nir_op_fddy_coarse:
1369 case nir_op_fddy_fine:
1370 result = ntq_fddy(c, src[0]);
1371 break;
1372
1373 default:
1374 fprintf(stderr, "unknown NIR ALU inst: ");
1375 nir_print_instr(&instr->instr, stderr);
1376 fprintf(stderr, "\n");
1377 abort();
1378 }
1379
1380 /* We have a scalar result, so the instruction should only have a
1381 * single channel written to.
1382 */
1383 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1384 ntq_store_dest(c, &instr->dest.dest,
1385 ffs(instr->dest.write_mask) - 1, result);
1386 }
1387
1388 static void
1389 emit_frag_end(struct vc4_compile *c)
1390 {
1391 struct qreg color;
1392 if (c->output_color_index != -1) {
1393 color = c->outputs[c->output_color_index];
1394 } else {
1395 color = qir_uniform_ui(c, 0);
1396 }
1397
1398 uint32_t discard_cond = QPU_COND_ALWAYS;
1399 if (c->s->info.fs.uses_discard) {
1400 qir_SF(c, c->discard);
1401 discard_cond = QPU_COND_ZS;
1402 }
1403
1404 if (c->fs_key->stencil_enabled) {
1405 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1406 qir_uniform(c, QUNIFORM_STENCIL, 0));
1407 if (c->fs_key->stencil_twoside) {
1408 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1409 qir_uniform(c, QUNIFORM_STENCIL, 1));
1410 }
1411 if (c->fs_key->stencil_full_writemasks) {
1412 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1413 qir_uniform(c, QUNIFORM_STENCIL, 2));
1414 }
1415 }
1416
1417 if (c->output_sample_mask_index != -1) {
1418 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1419 }
1420
1421 if (c->fs_key->depth_enabled) {
1422 if (c->output_position_index != -1) {
1423 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1424 qir_FMUL(c,
1425 c->outputs[c->output_position_index],
1426 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1427 } else {
1428 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1429 qir_FRAG_Z(c))->cond = discard_cond;
1430 }
1431 }
1432
1433 if (!c->msaa_per_sample_output) {
1434 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1435 color)->cond = discard_cond;
1436 } else {
1437 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1438 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1439 c->sample_colors[i])->cond = discard_cond;
1440 }
1441 }
1442 }
1443
1444 static void
1445 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1446 {
1447 struct qreg packed = qir_get_temp(c);
1448
1449 for (int i = 0; i < 2; i++) {
1450 struct qreg scale =
1451 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1452
1453 struct qreg packed_chan = packed;
1454 packed_chan.pack = QPU_PACK_A_16A + i;
1455
1456 qir_FTOI_dest(c, packed_chan,
1457 qir_FMUL(c,
1458 qir_FMUL(c,
1459 c->outputs[c->output_position_index + i],
1460 scale),
1461 rcp_w));
1462 }
1463
1464 qir_VPM_WRITE(c, packed);
1465 }
1466
1467 static void
1468 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1469 {
1470 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1471 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1472
1473 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1474 c->outputs[c->output_position_index + 2],
1475 zscale),
1476 rcp_w),
1477 zoffset));
1478 }
1479
1480 static void
1481 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1482 {
1483 qir_VPM_WRITE(c, rcp_w);
1484 }
1485
1486 static void
1487 emit_point_size_write(struct vc4_compile *c)
1488 {
1489 struct qreg point_size;
1490
1491 if (c->output_point_size_index != -1)
1492 point_size = c->outputs[c->output_point_size_index];
1493 else
1494 point_size = qir_uniform_f(c, 1.0);
1495
1496 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1497 * BCM21553).
1498 */
1499 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1500
1501 qir_VPM_WRITE(c, point_size);
1502 }
1503
1504 /**
1505 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1506 *
1507 * The simulator insists that there be at least one vertex attribute, so
1508 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1509 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1510 * to consume it here.
1511 */
1512 static void
1513 emit_stub_vpm_read(struct vc4_compile *c)
1514 {
1515 if (c->num_inputs)
1516 return;
1517
1518 c->vattr_sizes[0] = 4;
1519 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1520 c->num_inputs++;
1521 }
1522
1523 static void
1524 emit_vert_end(struct vc4_compile *c,
1525 struct vc4_varying_slot *fs_inputs,
1526 uint32_t num_fs_inputs)
1527 {
1528 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1529
1530 emit_stub_vpm_read(c);
1531
1532 emit_scaled_viewport_write(c, rcp_w);
1533 emit_zs_write(c, rcp_w);
1534 emit_rcp_wc_write(c, rcp_w);
1535 if (c->vs_key->per_vertex_point_size)
1536 emit_point_size_write(c);
1537
1538 for (int i = 0; i < num_fs_inputs; i++) {
1539 struct vc4_varying_slot *input = &fs_inputs[i];
1540 int j;
1541
1542 for (j = 0; j < c->num_outputs; j++) {
1543 struct vc4_varying_slot *output =
1544 &c->output_slots[j];
1545
1546 if (input->slot == output->slot &&
1547 input->swizzle == output->swizzle) {
1548 qir_VPM_WRITE(c, c->outputs[j]);
1549 break;
1550 }
1551 }
1552 /* Emit padding if we didn't find a declared VS output for
1553 * this FS input.
1554 */
1555 if (j == c->num_outputs)
1556 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1557 }
1558 }
1559
1560 static void
1561 emit_coord_end(struct vc4_compile *c)
1562 {
1563 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1564
1565 emit_stub_vpm_read(c);
1566
1567 for (int i = 0; i < 4; i++)
1568 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1569
1570 emit_scaled_viewport_write(c, rcp_w);
1571 emit_zs_write(c, rcp_w);
1572 emit_rcp_wc_write(c, rcp_w);
1573 if (c->vs_key->per_vertex_point_size)
1574 emit_point_size_write(c);
1575 }
1576
1577 static void
1578 vc4_optimize_nir(struct nir_shader *s)
1579 {
1580 bool progress;
1581
1582 do {
1583 progress = false;
1584
1585 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1586 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1587 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1588 NIR_PASS(progress, s, nir_copy_prop);
1589 NIR_PASS(progress, s, nir_opt_remove_phis);
1590 NIR_PASS(progress, s, nir_opt_dce);
1591 NIR_PASS(progress, s, nir_opt_dead_cf);
1592 NIR_PASS(progress, s, nir_opt_cse);
1593 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1594 NIR_PASS(progress, s, nir_opt_algebraic);
1595 NIR_PASS(progress, s, nir_opt_constant_folding);
1596 NIR_PASS(progress, s, nir_opt_undef);
1597 NIR_PASS(progress, s, nir_opt_loop_unroll,
1598 nir_var_shader_in |
1599 nir_var_shader_out |
1600 nir_var_function_temp);
1601 } while (progress);
1602 }
1603
1604 static int
1605 driver_location_compare(const void *in_a, const void *in_b)
1606 {
1607 const nir_variable *const *a = in_a;
1608 const nir_variable *const *b = in_b;
1609
1610 return (*a)->data.driver_location - (*b)->data.driver_location;
1611 }
1612
1613 static void
1614 ntq_setup_inputs(struct vc4_compile *c)
1615 {
1616 unsigned num_entries = 0;
1617 nir_foreach_variable(var, &c->s->inputs)
1618 num_entries++;
1619
1620 nir_variable *vars[num_entries];
1621
1622 unsigned i = 0;
1623 nir_foreach_variable(var, &c->s->inputs)
1624 vars[i++] = var;
1625
1626 /* Sort the variables so that we emit the input setup in
1627 * driver_location order. This is required for VPM reads, whose data
1628 * is fetched into the VPM in driver_location (TGSI register index)
1629 * order.
1630 */
1631 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1632
1633 for (unsigned i = 0; i < num_entries; i++) {
1634 nir_variable *var = vars[i];
1635 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1636 unsigned loc = var->data.driver_location;
1637
1638 assert(array_len == 1);
1639 (void)array_len;
1640 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1641 (loc + 1) * 4);
1642
1643 if (c->stage == QSTAGE_FRAG) {
1644 if (var->data.location == VARYING_SLOT_POS) {
1645 emit_fragcoord_input(c, loc);
1646 } else if (var->data.location == VARYING_SLOT_PNTC ||
1647 (var->data.location >= VARYING_SLOT_VAR0 &&
1648 (c->fs_key->point_sprite_mask &
1649 (1 << (var->data.location -
1650 VARYING_SLOT_VAR0))))) {
1651 c->inputs[loc * 4 + 0] = c->point_x;
1652 c->inputs[loc * 4 + 1] = c->point_y;
1653 } else {
1654 emit_fragment_input(c, loc, var->data.location);
1655 }
1656 } else {
1657 emit_vertex_input(c, loc);
1658 }
1659 }
1660 }
1661
1662 static void
1663 ntq_setup_outputs(struct vc4_compile *c)
1664 {
1665 nir_foreach_variable(var, &c->s->outputs) {
1666 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1667 unsigned loc = var->data.driver_location * 4;
1668
1669 assert(array_len == 1);
1670 (void)array_len;
1671
1672 for (int i = 0; i < 4; i++)
1673 add_output(c, loc + i, var->data.location, i);
1674
1675 if (c->stage == QSTAGE_FRAG) {
1676 switch (var->data.location) {
1677 case FRAG_RESULT_COLOR:
1678 case FRAG_RESULT_DATA0:
1679 c->output_color_index = loc;
1680 break;
1681 case FRAG_RESULT_DEPTH:
1682 c->output_position_index = loc;
1683 break;
1684 case FRAG_RESULT_SAMPLE_MASK:
1685 c->output_sample_mask_index = loc;
1686 break;
1687 }
1688 } else {
1689 switch (var->data.location) {
1690 case VARYING_SLOT_POS:
1691 c->output_position_index = loc;
1692 break;
1693 case VARYING_SLOT_PSIZ:
1694 c->output_point_size_index = loc;
1695 break;
1696 }
1697 }
1698 }
1699 }
1700
1701 static void
1702 ntq_setup_uniforms(struct vc4_compile *c)
1703 {
1704 nir_foreach_variable(var, &c->s->uniforms) {
1705 uint32_t vec4_count = uniforms_type_size(var->type);
1706 unsigned vec4_size = 4 * sizeof(float);
1707
1708 declare_uniform_range(c, var->data.driver_location * vec4_size,
1709 vec4_count * vec4_size);
1710
1711 }
1712 }
1713
1714 /**
1715 * Sets up the mapping from nir_register to struct qreg *.
1716 *
1717 * Each nir_register gets a struct qreg per 32-bit component being stored.
1718 */
1719 static void
1720 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1721 {
1722 foreach_list_typed(nir_register, nir_reg, node, list) {
1723 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1724 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1725 array_len *
1726 nir_reg->num_components);
1727
1728 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1729
1730 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1731 qregs[i] = qir_get_temp(c);
1732 }
1733 }
1734
1735 static void
1736 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1737 {
1738 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1739 for (int i = 0; i < instr->def.num_components; i++)
1740 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1741
1742 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1743 }
1744
1745 static void
1746 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1747 {
1748 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1749
1750 /* QIR needs there to be *some* value, so pick 0 (same as for
1751 * ntq_setup_registers().
1752 */
1753 for (int i = 0; i < instr->def.num_components; i++)
1754 qregs[i] = qir_uniform_ui(c, 0);
1755 }
1756
1757 static void
1758 ntq_emit_color_read(struct vc4_compile *c, nir_intrinsic_instr *instr)
1759 {
1760 assert(nir_src_as_uint(instr->src[0]) == 0);
1761
1762 /* Reads of the per-sample color need to be done in
1763 * order.
1764 */
1765 int sample_index = (nir_intrinsic_base(instr) -
1766 VC4_NIR_TLB_COLOR_READ_INPUT);
1767 for (int i = 0; i <= sample_index; i++) {
1768 if (c->color_reads[i].file == QFILE_NULL) {
1769 c->color_reads[i] =
1770 qir_TLB_COLOR_READ(c);
1771 }
1772 }
1773 ntq_store_dest(c, &instr->dest, 0,
1774 qir_MOV(c, c->color_reads[sample_index]));
1775 }
1776
1777 static void
1778 ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
1779 {
1780 assert(instr->num_components == 1);
1781 assert(nir_src_is_const(instr->src[0]) &&
1782 "vc4 doesn't support indirect inputs");
1783
1784 if (c->stage == QSTAGE_FRAG &&
1785 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1786 ntq_emit_color_read(c, instr);
1787 return;
1788 }
1789
1790 uint32_t offset = nir_intrinsic_base(instr) +
1791 nir_src_as_uint(instr->src[0]);
1792 int comp = nir_intrinsic_component(instr);
1793 ntq_store_dest(c, &instr->dest, 0,
1794 qir_MOV(c, c->inputs[offset * 4 + comp]));
1795 }
1796
1797 static void
1798 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1799 {
1800 unsigned offset;
1801
1802 switch (instr->intrinsic) {
1803 case nir_intrinsic_load_uniform:
1804 assert(instr->num_components == 1);
1805 if (nir_src_is_const(instr->src[0])) {
1806 offset = nir_intrinsic_base(instr) +
1807 nir_src_as_uint(instr->src[0]);
1808 assert(offset % 4 == 0);
1809 /* We need dwords */
1810 offset = offset / 4;
1811 ntq_store_dest(c, &instr->dest, 0,
1812 qir_uniform(c, QUNIFORM_UNIFORM,
1813 offset));
1814 } else {
1815 ntq_store_dest(c, &instr->dest, 0,
1816 indirect_uniform_load(c, instr));
1817 }
1818 break;
1819
1820 case nir_intrinsic_load_ubo:
1821 assert(instr->num_components == 1);
1822 ntq_store_dest(c, &instr->dest, 0, vc4_ubo_load(c, instr));
1823 break;
1824
1825 case nir_intrinsic_load_user_clip_plane:
1826 for (int i = 0; i < instr->num_components; i++) {
1827 ntq_store_dest(c, &instr->dest, i,
1828 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1829 nir_intrinsic_ucp_id(instr) *
1830 4 + i));
1831 }
1832 break;
1833
1834 case nir_intrinsic_load_blend_const_color_r_float:
1835 case nir_intrinsic_load_blend_const_color_g_float:
1836 case nir_intrinsic_load_blend_const_color_b_float:
1837 case nir_intrinsic_load_blend_const_color_a_float:
1838 ntq_store_dest(c, &instr->dest, 0,
1839 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1840 (instr->intrinsic -
1841 nir_intrinsic_load_blend_const_color_r_float),
1842 0));
1843 break;
1844
1845 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1846 ntq_store_dest(c, &instr->dest, 0,
1847 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1848 0));
1849 break;
1850
1851 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1852 ntq_store_dest(c, &instr->dest, 0,
1853 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1854 0));
1855 break;
1856
1857 case nir_intrinsic_load_alpha_ref_float:
1858 ntq_store_dest(c, &instr->dest, 0,
1859 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1860 break;
1861
1862 case nir_intrinsic_load_sample_mask_in:
1863 ntq_store_dest(c, &instr->dest, 0,
1864 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1865 break;
1866
1867 case nir_intrinsic_load_front_face:
1868 /* The register contains 0 (front) or 1 (back), and we need to
1869 * turn it into a NIR bool where true means front.
1870 */
1871 ntq_store_dest(c, &instr->dest, 0,
1872 qir_ADD(c,
1873 qir_uniform_ui(c, -1),
1874 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1875 break;
1876
1877 case nir_intrinsic_load_input:
1878 ntq_emit_load_input(c, instr);
1879 break;
1880
1881 case nir_intrinsic_store_output:
1882 assert(nir_src_is_const(instr->src[1]) &&
1883 "vc4 doesn't support indirect outputs");
1884 offset = nir_intrinsic_base(instr) +
1885 nir_src_as_uint(instr->src[1]);
1886
1887 /* MSAA color outputs are the only case where we have an
1888 * output that's not lowered to being a store of a single 32
1889 * bit value.
1890 */
1891 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1892 assert(offset == c->output_color_index);
1893 for (int i = 0; i < 4; i++) {
1894 c->sample_colors[i] =
1895 qir_MOV(c, ntq_get_src(c, instr->src[0],
1896 i));
1897 }
1898 } else {
1899 offset = offset * 4 + nir_intrinsic_component(instr);
1900 assert(instr->num_components == 1);
1901 c->outputs[offset] =
1902 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1903 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1904 }
1905 break;
1906
1907 case nir_intrinsic_discard:
1908 if (c->execute.file != QFILE_NULL) {
1909 qir_SF(c, c->execute);
1910 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1911 qir_uniform_ui(c, ~0));
1912 } else {
1913 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1914 }
1915 break;
1916
1917 case nir_intrinsic_discard_if: {
1918 /* true (~0) if we're discarding */
1919 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1920
1921 if (c->execute.file != QFILE_NULL) {
1922 /* execute == 0 means the channel is active. Invert
1923 * the condition so that we can use zero as "executing
1924 * and discarding."
1925 */
1926 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1927 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1928 } else {
1929 qir_OR_dest(c, c->discard, c->discard,
1930 ntq_get_src(c, instr->src[0], 0));
1931 }
1932
1933 break;
1934 }
1935
1936 default:
1937 fprintf(stderr, "Unknown intrinsic: ");
1938 nir_print_instr(&instr->instr, stderr);
1939 fprintf(stderr, "\n");
1940 break;
1941 }
1942 }
1943
1944 /* Clears (activates) the execute flags for any channels whose jump target
1945 * matches this block.
1946 */
1947 static void
1948 ntq_activate_execute_for_block(struct vc4_compile *c)
1949 {
1950 qir_SF(c, qir_SUB(c,
1951 c->execute,
1952 qir_uniform_ui(c, c->cur_block->index)));
1953 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1954 }
1955
1956 static void
1957 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1958 {
1959 if (!c->vc4->screen->has_control_flow) {
1960 fprintf(stderr,
1961 "IF statement support requires updated kernel.\n");
1962 return;
1963 }
1964
1965 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1966 bool empty_else_block =
1967 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1968 exec_list_is_empty(&nir_else_block->instr_list));
1969
1970 struct qblock *then_block = qir_new_block(c);
1971 struct qblock *after_block = qir_new_block(c);
1972 struct qblock *else_block;
1973 if (empty_else_block)
1974 else_block = after_block;
1975 else
1976 else_block = qir_new_block(c);
1977
1978 bool was_top_level = false;
1979 if (c->execute.file == QFILE_NULL) {
1980 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1981 was_top_level = true;
1982 }
1983
1984 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1985 * 0) channels, and then update execute flags for those to point to
1986 * the ELSE block.
1987 */
1988 qir_SF(c, qir_OR(c,
1989 c->execute,
1990 ntq_get_src(c, if_stmt->condition, 0)));
1991 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1992 qir_uniform_ui(c, else_block->index));
1993
1994 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1995 * through.
1996 */
1997 qir_SF(c, c->execute);
1998 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1999 qir_link_blocks(c->cur_block, else_block);
2000 qir_link_blocks(c->cur_block, then_block);
2001
2002 /* Process the THEN block. */
2003 qir_set_emit_block(c, then_block);
2004 ntq_emit_cf_list(c, &if_stmt->then_list);
2005
2006 if (!empty_else_block) {
2007 /* Handle the end of the THEN block. First, all currently
2008 * active channels update their execute flags to point to
2009 * ENDIF
2010 */
2011 qir_SF(c, c->execute);
2012 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
2013 qir_uniform_ui(c, after_block->index));
2014
2015 /* If everything points at ENDIF, then jump there immediately. */
2016 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
2017 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
2018 qir_link_blocks(c->cur_block, after_block);
2019 qir_link_blocks(c->cur_block, else_block);
2020
2021 qir_set_emit_block(c, else_block);
2022 ntq_activate_execute_for_block(c);
2023 ntq_emit_cf_list(c, &if_stmt->else_list);
2024 }
2025
2026 qir_link_blocks(c->cur_block, after_block);
2027
2028 qir_set_emit_block(c, after_block);
2029 if (was_top_level) {
2030 c->execute = c->undef;
2031 c->last_top_block = c->cur_block;
2032 } else {
2033 ntq_activate_execute_for_block(c);
2034 }
2035 }
2036
2037 static void
2038 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
2039 {
2040 struct qblock *jump_block;
2041 switch (jump->type) {
2042 case nir_jump_break:
2043 jump_block = c->loop_break_block;
2044 break;
2045 case nir_jump_continue:
2046 jump_block = c->loop_cont_block;
2047 break;
2048 default:
2049 unreachable("Unsupported jump type\n");
2050 }
2051
2052 qir_SF(c, c->execute);
2053 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
2054 qir_uniform_ui(c, jump_block->index));
2055
2056 /* Jump to the destination block if everyone has taken the jump. */
2057 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, jump_block->index)));
2058 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
2059 struct qblock *new_block = qir_new_block(c);
2060 qir_link_blocks(c->cur_block, jump_block);
2061 qir_link_blocks(c->cur_block, new_block);
2062 qir_set_emit_block(c, new_block);
2063 }
2064
2065 static void
2066 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
2067 {
2068 switch (instr->type) {
2069 case nir_instr_type_alu:
2070 ntq_emit_alu(c, nir_instr_as_alu(instr));
2071 break;
2072
2073 case nir_instr_type_intrinsic:
2074 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2075 break;
2076
2077 case nir_instr_type_load_const:
2078 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2079 break;
2080
2081 case nir_instr_type_ssa_undef:
2082 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2083 break;
2084
2085 case nir_instr_type_tex:
2086 ntq_emit_tex(c, nir_instr_as_tex(instr));
2087 break;
2088
2089 case nir_instr_type_jump:
2090 ntq_emit_jump(c, nir_instr_as_jump(instr));
2091 break;
2092
2093 default:
2094 fprintf(stderr, "Unknown NIR instr type: ");
2095 nir_print_instr(instr, stderr);
2096 fprintf(stderr, "\n");
2097 abort();
2098 }
2099 }
2100
2101 static void
2102 ntq_emit_block(struct vc4_compile *c, nir_block *block)
2103 {
2104 nir_foreach_instr(instr, block) {
2105 ntq_emit_instr(c, instr);
2106 }
2107 }
2108
2109 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
2110
2111 static void
2112 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
2113 {
2114 if (!c->vc4->screen->has_control_flow) {
2115 fprintf(stderr,
2116 "loop support requires updated kernel.\n");
2117 ntq_emit_cf_list(c, &loop->body);
2118 return;
2119 }
2120
2121 bool was_top_level = false;
2122 if (c->execute.file == QFILE_NULL) {
2123 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
2124 was_top_level = true;
2125 }
2126
2127 struct qblock *save_loop_cont_block = c->loop_cont_block;
2128 struct qblock *save_loop_break_block = c->loop_break_block;
2129
2130 c->loop_cont_block = qir_new_block(c);
2131 c->loop_break_block = qir_new_block(c);
2132
2133 qir_link_blocks(c->cur_block, c->loop_cont_block);
2134 qir_set_emit_block(c, c->loop_cont_block);
2135 ntq_activate_execute_for_block(c);
2136
2137 ntq_emit_cf_list(c, &loop->body);
2138
2139 /* If anything had explicitly continued, or is here at the end of the
2140 * loop, then we need to loop again. SF updates are masked by the
2141 * instruction's condition, so we can do the OR of the two conditions
2142 * within SF.
2143 */
2144 qir_SF(c, c->execute);
2145 struct qinst *cont_check =
2146 qir_SUB_dest(c,
2147 c->undef,
2148 c->execute,
2149 qir_uniform_ui(c, c->loop_cont_block->index));
2150 cont_check->cond = QPU_COND_ZC;
2151 cont_check->sf = true;
2152
2153 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
2154 qir_link_blocks(c->cur_block, c->loop_cont_block);
2155 qir_link_blocks(c->cur_block, c->loop_break_block);
2156
2157 qir_set_emit_block(c, c->loop_break_block);
2158 if (was_top_level) {
2159 c->execute = c->undef;
2160 c->last_top_block = c->cur_block;
2161 } else {
2162 ntq_activate_execute_for_block(c);
2163 }
2164
2165 c->loop_break_block = save_loop_break_block;
2166 c->loop_cont_block = save_loop_cont_block;
2167 }
2168
2169 static void
2170 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
2171 {
2172 fprintf(stderr, "FUNCTIONS not handled.\n");
2173 abort();
2174 }
2175
2176 static void
2177 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
2178 {
2179 foreach_list_typed(nir_cf_node, node, node, list) {
2180 switch (node->type) {
2181 case nir_cf_node_block:
2182 ntq_emit_block(c, nir_cf_node_as_block(node));
2183 break;
2184
2185 case nir_cf_node_if:
2186 ntq_emit_if(c, nir_cf_node_as_if(node));
2187 break;
2188
2189 case nir_cf_node_loop:
2190 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2191 break;
2192
2193 case nir_cf_node_function:
2194 ntq_emit_function(c, nir_cf_node_as_function(node));
2195 break;
2196
2197 default:
2198 fprintf(stderr, "Unknown NIR node type\n");
2199 abort();
2200 }
2201 }
2202 }
2203
2204 static void
2205 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2206 {
2207 ntq_setup_registers(c, &impl->registers);
2208 ntq_emit_cf_list(c, &impl->body);
2209 }
2210
2211 static void
2212 nir_to_qir(struct vc4_compile *c)
2213 {
2214 if (c->stage == QSTAGE_FRAG && c->s->info.fs.uses_discard)
2215 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2216
2217 ntq_setup_inputs(c);
2218 ntq_setup_outputs(c);
2219 ntq_setup_uniforms(c);
2220
2221 /* Find the main function and emit the body. */
2222 nir_foreach_function(function, c->s) {
2223 assert(strcmp(function->name, "main") == 0);
2224 assert(function->impl);
2225 ntq_emit_impl(c, function->impl);
2226 }
2227 }
2228
2229 static const nir_shader_compiler_options nir_options = {
2230 .lower_all_io_to_temps = true,
2231 .lower_extract_byte = true,
2232 .lower_extract_word = true,
2233 .lower_fdiv = true,
2234 .lower_ffma = true,
2235 .lower_flrp32 = true,
2236 .lower_fpow = true,
2237 .lower_fsat = true,
2238 .lower_fsqrt = true,
2239 .lower_ldexp = true,
2240 .lower_negate = true,
2241 .native_integers = true,
2242 .max_unroll_iterations = 32,
2243 };
2244
2245 const void *
2246 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2247 enum pipe_shader_ir ir,
2248 enum pipe_shader_type shader)
2249 {
2250 return &nir_options;
2251 }
2252
2253 static int
2254 count_nir_instrs(nir_shader *nir)
2255 {
2256 int count = 0;
2257 nir_foreach_function(function, nir) {
2258 if (!function->impl)
2259 continue;
2260 nir_foreach_block(block, function->impl) {
2261 nir_foreach_instr(instr, block)
2262 count++;
2263 }
2264 }
2265 return count;
2266 }
2267
2268 static struct vc4_compile *
2269 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2270 struct vc4_key *key, bool fs_threaded)
2271 {
2272 struct vc4_compile *c = qir_compile_init();
2273
2274 c->vc4 = vc4;
2275 c->stage = stage;
2276 c->shader_state = &key->shader_state->base;
2277 c->program_id = key->shader_state->program_id;
2278 c->variant_id =
2279 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2280 c->fs_threaded = fs_threaded;
2281
2282 c->key = key;
2283 switch (stage) {
2284 case QSTAGE_FRAG:
2285 c->fs_key = (struct vc4_fs_key *)key;
2286 if (c->fs_key->is_points) {
2287 c->point_x = emit_fragment_varying(c, ~0, 0);
2288 c->point_y = emit_fragment_varying(c, ~0, 0);
2289 } else if (c->fs_key->is_lines) {
2290 c->line_x = emit_fragment_varying(c, ~0, 0);
2291 }
2292 break;
2293 case QSTAGE_VERT:
2294 c->vs_key = (struct vc4_vs_key *)key;
2295 break;
2296 case QSTAGE_COORD:
2297 c->vs_key = (struct vc4_vs_key *)key;
2298 break;
2299 }
2300
2301 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2302
2303 if (stage == QSTAGE_FRAG) {
2304 if (c->fs_key->alpha_test_func != COMPARE_FUNC_ALWAYS) {
2305 NIR_PASS_V(c->s, nir_lower_alpha_test,
2306 c->fs_key->alpha_test_func,
2307 c->fs_key->sample_alpha_to_one &&
2308 c->fs_key->msaa);
2309 }
2310 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2311 }
2312
2313 struct nir_lower_tex_options tex_options = {
2314 /* We would need to implement txs, but we don't want the
2315 * int/float conversions
2316 */
2317 .lower_rect = false,
2318
2319 .lower_txp = ~0,
2320
2321 /* Apply swizzles to all samplers. */
2322 .swizzle_result = ~0,
2323 };
2324
2325 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2326 * The format swizzling applies before sRGB decode, and
2327 * ARB_texture_swizzle is the last thing before returning the sample.
2328 */
2329 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2330 enum pipe_format format = c->key->tex[i].format;
2331
2332 if (!format)
2333 continue;
2334
2335 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2336
2337 for (int j = 0; j < 4; j++) {
2338 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2339
2340 if (arb_swiz <= 3) {
2341 tex_options.swizzles[i][j] =
2342 format_swizzle[arb_swiz];
2343 } else {
2344 tex_options.swizzles[i][j] = arb_swiz;
2345 }
2346 }
2347
2348 if (util_format_is_srgb(format))
2349 tex_options.lower_srgb |= (1 << i);
2350 }
2351
2352 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2353
2354 if (c->fs_key && c->fs_key->light_twoside)
2355 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2356
2357 if (c->vs_key && c->vs_key->clamp_color)
2358 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2359
2360 if (c->key->ucp_enables) {
2361 if (stage == QSTAGE_FRAG) {
2362 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2363 } else {
2364 NIR_PASS_V(c->s, nir_lower_clip_vs,
2365 c->key->ucp_enables, false);
2366 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2367 nir_var_shader_out);
2368 }
2369 }
2370
2371 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2372 * which only handles a vec4 at a time. Similarly, VS output
2373 * scalarizing must happen after nir_lower_clip_vs.
2374 */
2375 if (c->stage == QSTAGE_FRAG)
2376 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2377 else
2378 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2379
2380 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2381 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2382 NIR_PASS_V(c->s, nir_lower_idiv);
2383
2384 vc4_optimize_nir(c->s);
2385
2386 NIR_PASS_V(c->s, nir_lower_bool_to_int32);
2387
2388 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2389
2390 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2391 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2392 qir_get_stage_name(c->stage),
2393 c->program_id, c->variant_id,
2394 count_nir_instrs(c->s));
2395 }
2396
2397 if (vc4_debug & VC4_DEBUG_NIR) {
2398 fprintf(stderr, "%s prog %d/%d NIR:\n",
2399 qir_get_stage_name(c->stage),
2400 c->program_id, c->variant_id);
2401 nir_print_shader(c->s, stderr);
2402 }
2403
2404 nir_to_qir(c);
2405
2406 switch (stage) {
2407 case QSTAGE_FRAG:
2408 /* FS threading requires that the thread execute
2409 * QPU_SIG_LAST_THREAD_SWITCH exactly once before terminating
2410 * (with no other THRSW afterwards, obviously). If we didn't
2411 * fetch a texture at a top level block, this wouldn't be
2412 * true.
2413 */
2414 if (c->fs_threaded && !c->last_thrsw_at_top_level) {
2415 c->failed = true;
2416 return c;
2417 }
2418
2419 emit_frag_end(c);
2420 break;
2421 case QSTAGE_VERT:
2422 emit_vert_end(c,
2423 c->vs_key->fs_inputs->input_slots,
2424 c->vs_key->fs_inputs->num_inputs);
2425 break;
2426 case QSTAGE_COORD:
2427 emit_coord_end(c);
2428 break;
2429 }
2430
2431 if (vc4_debug & VC4_DEBUG_QIR) {
2432 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2433 qir_get_stage_name(c->stage),
2434 c->program_id, c->variant_id);
2435 qir_dump(c);
2436 fprintf(stderr, "\n");
2437 }
2438
2439 qir_optimize(c);
2440 qir_lower_uniforms(c);
2441
2442 qir_schedule_instructions(c);
2443 qir_emit_uniform_stream_resets(c);
2444
2445 if (vc4_debug & VC4_DEBUG_QIR) {
2446 fprintf(stderr, "%s prog %d/%d QIR:\n",
2447 qir_get_stage_name(c->stage),
2448 c->program_id, c->variant_id);
2449 qir_dump(c);
2450 fprintf(stderr, "\n");
2451 }
2452
2453 qir_reorder_uniforms(c);
2454 vc4_generate_code(vc4, c);
2455
2456 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2457 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2458 qir_get_stage_name(c->stage),
2459 c->program_id, c->variant_id,
2460 c->qpu_inst_count);
2461 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2462 qir_get_stage_name(c->stage),
2463 c->program_id, c->variant_id,
2464 c->num_uniforms);
2465 }
2466
2467 ralloc_free(c->s);
2468
2469 return c;
2470 }
2471
2472 static void *
2473 vc4_shader_state_create(struct pipe_context *pctx,
2474 const struct pipe_shader_state *cso)
2475 {
2476 struct vc4_context *vc4 = vc4_context(pctx);
2477 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2478 if (!so)
2479 return NULL;
2480
2481 so->program_id = vc4->next_uncompiled_program_id++;
2482
2483 nir_shader *s;
2484
2485 if (cso->type == PIPE_SHADER_IR_NIR) {
2486 /* The backend takes ownership of the NIR shader on state
2487 * creation.
2488 */
2489 s = cso->ir.nir;
2490 } else {
2491 assert(cso->type == PIPE_SHADER_IR_TGSI);
2492
2493 if (vc4_debug & VC4_DEBUG_TGSI) {
2494 fprintf(stderr, "prog %d TGSI:\n",
2495 so->program_id);
2496 tgsi_dump(cso->tokens, 0);
2497 fprintf(stderr, "\n");
2498 }
2499 s = tgsi_to_nir(cso->tokens, pctx->screen);
2500 }
2501
2502 NIR_PASS_V(s, nir_lower_io, nir_var_all, type_size,
2503 (nir_lower_io_options)0);
2504
2505 NIR_PASS_V(s, nir_lower_regs_to_ssa);
2506 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2507
2508 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2509
2510 vc4_optimize_nir(s);
2511
2512 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp);
2513
2514 /* Garbage collect dead instructions */
2515 nir_sweep(s);
2516
2517 so->base.type = PIPE_SHADER_IR_NIR;
2518 so->base.ir.nir = s;
2519
2520 if (vc4_debug & VC4_DEBUG_NIR) {
2521 fprintf(stderr, "%s prog %d NIR:\n",
2522 gl_shader_stage_name(s->info.stage),
2523 so->program_id);
2524 nir_print_shader(s, stderr);
2525 fprintf(stderr, "\n");
2526 }
2527
2528 return so;
2529 }
2530
2531 static void
2532 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2533 struct vc4_compile *c)
2534 {
2535 int count = c->num_uniforms;
2536 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2537
2538 uinfo->count = count;
2539 uinfo->data = ralloc_array(shader, uint32_t, count);
2540 memcpy(uinfo->data, c->uniform_data,
2541 count * sizeof(*uinfo->data));
2542 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2543 memcpy(uinfo->contents, c->uniform_contents,
2544 count * sizeof(*uinfo->contents));
2545 uinfo->num_texture_samples = c->num_texture_samples;
2546
2547 vc4_set_shader_uniform_dirty_flags(shader);
2548 }
2549
2550 static void
2551 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2552 struct vc4_compiled_shader *shader)
2553 {
2554 struct vc4_fs_inputs inputs;
2555
2556 memset(&inputs, 0, sizeof(inputs));
2557 inputs.input_slots = ralloc_array(shader,
2558 struct vc4_varying_slot,
2559 c->num_input_slots);
2560
2561 bool input_live[c->num_input_slots];
2562
2563 memset(input_live, 0, sizeof(input_live));
2564 qir_for_each_inst_inorder(inst, c) {
2565 for (int i = 0; i < qir_get_nsrc(inst); i++) {
2566 if (inst->src[i].file == QFILE_VARY)
2567 input_live[inst->src[i].index] = true;
2568 }
2569 }
2570
2571 for (int i = 0; i < c->num_input_slots; i++) {
2572 struct vc4_varying_slot *slot = &c->input_slots[i];
2573
2574 if (!input_live[i])
2575 continue;
2576
2577 /* Skip non-VS-output inputs. */
2578 if (slot->slot == (uint8_t)~0)
2579 continue;
2580
2581 if (slot->slot == VARYING_SLOT_COL0 ||
2582 slot->slot == VARYING_SLOT_COL1 ||
2583 slot->slot == VARYING_SLOT_BFC0 ||
2584 slot->slot == VARYING_SLOT_BFC1) {
2585 shader->color_inputs |= (1 << inputs.num_inputs);
2586 }
2587
2588 inputs.input_slots[inputs.num_inputs] = *slot;
2589 inputs.num_inputs++;
2590 }
2591 shader->num_inputs = inputs.num_inputs;
2592
2593 /* Add our set of inputs to the set of all inputs seen. This way, we
2594 * can have a single pointer that identifies an FS inputs set,
2595 * allowing VS to avoid recompiling when the FS is recompiled (or a
2596 * new one is bound using separate shader objects) but the inputs
2597 * don't change.
2598 */
2599 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2600 if (entry) {
2601 shader->fs_inputs = entry->key;
2602 ralloc_free(inputs.input_slots);
2603 } else {
2604 struct vc4_fs_inputs *alloc_inputs;
2605
2606 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2607 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2608 ralloc_steal(alloc_inputs, inputs.input_slots);
2609 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2610
2611 shader->fs_inputs = alloc_inputs;
2612 }
2613 }
2614
2615 static struct vc4_compiled_shader *
2616 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2617 struct vc4_key *key)
2618 {
2619 struct hash_table *ht;
2620 uint32_t key_size;
2621 bool try_threading;
2622
2623 if (stage == QSTAGE_FRAG) {
2624 ht = vc4->fs_cache;
2625 key_size = sizeof(struct vc4_fs_key);
2626 try_threading = vc4->screen->has_threaded_fs;
2627 } else {
2628 ht = vc4->vs_cache;
2629 key_size = sizeof(struct vc4_vs_key);
2630 try_threading = false;
2631 }
2632
2633 struct vc4_compiled_shader *shader;
2634 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2635 if (entry)
2636 return entry->data;
2637
2638 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key, try_threading);
2639 /* If the FS failed to compile threaded, fall back to single threaded. */
2640 if (try_threading && c->failed) {
2641 qir_compile_destroy(c);
2642 c = vc4_shader_ntq(vc4, stage, key, false);
2643 }
2644
2645 shader = rzalloc(NULL, struct vc4_compiled_shader);
2646
2647 shader->program_id = vc4->next_compiled_program_id++;
2648 if (stage == QSTAGE_FRAG) {
2649 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2650
2651 /* Note: the temporary clone in c->s has been freed. */
2652 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2653 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2654 shader->disable_early_z = true;
2655 } else {
2656 shader->num_inputs = c->num_inputs;
2657
2658 shader->vattr_offsets[0] = 0;
2659 for (int i = 0; i < 8; i++) {
2660 shader->vattr_offsets[i + 1] =
2661 shader->vattr_offsets[i] + c->vattr_sizes[i];
2662
2663 if (c->vattr_sizes[i])
2664 shader->vattrs_live |= (1 << i);
2665 }
2666 }
2667
2668 shader->failed = c->failed;
2669 if (c->failed) {
2670 shader->failed = true;
2671 } else {
2672 copy_uniform_state_to_shader(shader, c);
2673 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2674 c->qpu_inst_count *
2675 sizeof(uint64_t));
2676 }
2677
2678 shader->fs_threaded = c->fs_threaded;
2679
2680 /* Copy the compiler UBO range state to the compiled shader, dropping
2681 * out arrays that were never referenced by an indirect load.
2682 *
2683 * (Note that QIR dead code elimination of an array access still
2684 * leaves that array alive, though)
2685 */
2686 if (c->num_ubo_ranges) {
2687 shader->num_ubo_ranges = c->num_ubo_ranges;
2688 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2689 c->num_ubo_ranges);
2690 uint32_t j = 0;
2691 for (int i = 0; i < c->num_uniform_ranges; i++) {
2692 struct vc4_compiler_ubo_range *range =
2693 &c->ubo_ranges[i];
2694 if (!range->used)
2695 continue;
2696
2697 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2698 shader->ubo_ranges[j].src_offset = range->src_offset;
2699 shader->ubo_ranges[j].size = range->size;
2700 shader->ubo_size += c->ubo_ranges[i].size;
2701 j++;
2702 }
2703 }
2704 if (shader->ubo_size) {
2705 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2706 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2707 qir_get_stage_name(c->stage),
2708 c->program_id, c->variant_id,
2709 shader->ubo_size / 4);
2710 }
2711 }
2712
2713 if ((vc4_debug & VC4_DEBUG_SHADERDB) && stage == QSTAGE_FRAG) {
2714 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d FS threads\n",
2715 qir_get_stage_name(c->stage),
2716 c->program_id, c->variant_id,
2717 1 + shader->fs_threaded);
2718 }
2719
2720 qir_compile_destroy(c);
2721
2722 struct vc4_key *dup_key;
2723 dup_key = rzalloc_size(shader, key_size); /* TODO: don't use rzalloc */
2724 memcpy(dup_key, key, key_size);
2725 _mesa_hash_table_insert(ht, dup_key, shader);
2726
2727 return shader;
2728 }
2729
2730 static void
2731 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2732 struct vc4_texture_stateobj *texstate)
2733 {
2734 for (int i = 0; i < texstate->num_textures; i++) {
2735 struct pipe_sampler_view *sampler = texstate->textures[i];
2736 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2737 struct pipe_sampler_state *sampler_state =
2738 texstate->samplers[i];
2739
2740 if (!sampler)
2741 continue;
2742
2743 key->tex[i].format = sampler->format;
2744 key->tex[i].swizzle[0] = sampler->swizzle_r;
2745 key->tex[i].swizzle[1] = sampler->swizzle_g;
2746 key->tex[i].swizzle[2] = sampler->swizzle_b;
2747 key->tex[i].swizzle[3] = sampler->swizzle_a;
2748
2749 if (sampler->texture->nr_samples > 1) {
2750 key->tex[i].msaa_width = sampler->texture->width0;
2751 key->tex[i].msaa_height = sampler->texture->height0;
2752 } else if (sampler){
2753 key->tex[i].compare_mode = sampler_state->compare_mode;
2754 key->tex[i].compare_func = sampler_state->compare_func;
2755 key->tex[i].wrap_s = sampler_state->wrap_s;
2756 key->tex[i].wrap_t = sampler_state->wrap_t;
2757 key->tex[i].force_first_level =
2758 vc4_sampler->force_first_level;
2759 }
2760 }
2761
2762 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2763 }
2764
2765 static void
2766 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2767 {
2768 struct vc4_job *job = vc4->job;
2769 struct vc4_fs_key local_key;
2770 struct vc4_fs_key *key = &local_key;
2771
2772 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2773 VC4_DIRTY_BLEND |
2774 VC4_DIRTY_FRAMEBUFFER |
2775 VC4_DIRTY_ZSA |
2776 VC4_DIRTY_RASTERIZER |
2777 VC4_DIRTY_SAMPLE_MASK |
2778 VC4_DIRTY_FRAGTEX |
2779 VC4_DIRTY_UNCOMPILED_FS |
2780 VC4_DIRTY_UBO_1_SIZE))) {
2781 return;
2782 }
2783
2784 memset(key, 0, sizeof(*key));
2785 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2786 key->base.shader_state = vc4->prog.bind_fs;
2787 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2788 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2789 prim_mode <= PIPE_PRIM_LINE_STRIP);
2790 key->blend = vc4->blend->rt[0];
2791 if (vc4->blend->logicop_enable) {
2792 key->logicop_func = vc4->blend->logicop_func;
2793 } else {
2794 key->logicop_func = PIPE_LOGICOP_COPY;
2795 }
2796 if (job->msaa) {
2797 key->msaa = vc4->rasterizer->base.multisample;
2798 key->sample_coverage = (vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2799 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2800 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2801 }
2802
2803 if (vc4->framebuffer.cbufs[0])
2804 key->color_format = vc4->framebuffer.cbufs[0]->format;
2805
2806 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2807 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2808 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2809 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2810 key->stencil_enabled);
2811 if (vc4->zsa->base.alpha.enabled)
2812 key->alpha_test_func = vc4->zsa->base.alpha.func;
2813 else
2814 key->alpha_test_func = COMPARE_FUNC_ALWAYS;
2815
2816 if (key->is_points) {
2817 key->point_sprite_mask =
2818 vc4->rasterizer->base.sprite_coord_enable;
2819 key->point_coord_upper_left =
2820 (vc4->rasterizer->base.sprite_coord_mode ==
2821 PIPE_SPRITE_COORD_UPPER_LEFT);
2822 }
2823
2824 key->ubo_1_size = vc4->constbuf[PIPE_SHADER_FRAGMENT].cb[1].buffer_size;
2825 key->light_twoside = vc4->rasterizer->base.light_twoside;
2826
2827 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2828 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2829 if (vc4->prog.fs == old_fs)
2830 return;
2831
2832 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2833
2834 if (vc4->rasterizer->base.flatshade &&
2835 (!old_fs || vc4->prog.fs->color_inputs != old_fs->color_inputs)) {
2836 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2837 }
2838
2839 if (!old_fs || vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2840 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2841 }
2842
2843 static void
2844 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2845 {
2846 struct vc4_vs_key local_key;
2847 struct vc4_vs_key *key = &local_key;
2848
2849 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2850 VC4_DIRTY_RASTERIZER |
2851 VC4_DIRTY_VERTTEX |
2852 VC4_DIRTY_VTXSTATE |
2853 VC4_DIRTY_UNCOMPILED_VS |
2854 VC4_DIRTY_FS_INPUTS))) {
2855 return;
2856 }
2857
2858 memset(key, 0, sizeof(*key));
2859 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2860 key->base.shader_state = vc4->prog.bind_vs;
2861 key->fs_inputs = vc4->prog.fs->fs_inputs;
2862 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2863
2864 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2865 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2866
2867 key->per_vertex_point_size =
2868 (prim_mode == PIPE_PRIM_POINTS &&
2869 vc4->rasterizer->base.point_size_per_vertex);
2870
2871 struct vc4_compiled_shader *vs =
2872 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2873 if (vs != vc4->prog.vs) {
2874 vc4->prog.vs = vs;
2875 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2876 }
2877
2878 key->is_coord = true;
2879 /* Coord shaders don't care what the FS inputs are. */
2880 key->fs_inputs = NULL;
2881 struct vc4_compiled_shader *cs =
2882 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2883 if (cs != vc4->prog.cs) {
2884 vc4->prog.cs = cs;
2885 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2886 }
2887 }
2888
2889 bool
2890 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2891 {
2892 vc4_update_compiled_fs(vc4, prim_mode);
2893 vc4_update_compiled_vs(vc4, prim_mode);
2894
2895 return !(vc4->prog.cs->failed ||
2896 vc4->prog.vs->failed ||
2897 vc4->prog.fs->failed);
2898 }
2899
2900 static uint32_t
2901 fs_cache_hash(const void *key)
2902 {
2903 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2904 }
2905
2906 static uint32_t
2907 vs_cache_hash(const void *key)
2908 {
2909 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2910 }
2911
2912 static bool
2913 fs_cache_compare(const void *key1, const void *key2)
2914 {
2915 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2916 }
2917
2918 static bool
2919 vs_cache_compare(const void *key1, const void *key2)
2920 {
2921 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2922 }
2923
2924 static uint32_t
2925 fs_inputs_hash(const void *key)
2926 {
2927 const struct vc4_fs_inputs *inputs = key;
2928
2929 return _mesa_hash_data(inputs->input_slots,
2930 sizeof(*inputs->input_slots) *
2931 inputs->num_inputs);
2932 }
2933
2934 static bool
2935 fs_inputs_compare(const void *key1, const void *key2)
2936 {
2937 const struct vc4_fs_inputs *inputs1 = key1;
2938 const struct vc4_fs_inputs *inputs2 = key2;
2939
2940 return (inputs1->num_inputs == inputs2->num_inputs &&
2941 memcmp(inputs1->input_slots,
2942 inputs2->input_slots,
2943 sizeof(*inputs1->input_slots) *
2944 inputs1->num_inputs) == 0);
2945 }
2946
2947 static void
2948 delete_from_cache_if_matches(struct hash_table *ht,
2949 struct vc4_compiled_shader **last_compile,
2950 struct hash_entry *entry,
2951 struct vc4_uncompiled_shader *so)
2952 {
2953 const struct vc4_key *key = entry->key;
2954
2955 if (key->shader_state == so) {
2956 struct vc4_compiled_shader *shader = entry->data;
2957 _mesa_hash_table_remove(ht, entry);
2958 vc4_bo_unreference(&shader->bo);
2959
2960 if (shader == *last_compile)
2961 *last_compile = NULL;
2962
2963 ralloc_free(shader);
2964 }
2965 }
2966
2967 static void
2968 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2969 {
2970 struct vc4_context *vc4 = vc4_context(pctx);
2971 struct vc4_uncompiled_shader *so = hwcso;
2972
2973 hash_table_foreach(vc4->fs_cache, entry) {
2974 delete_from_cache_if_matches(vc4->fs_cache, &vc4->prog.fs,
2975 entry, so);
2976 }
2977 hash_table_foreach(vc4->vs_cache, entry) {
2978 delete_from_cache_if_matches(vc4->vs_cache, &vc4->prog.vs,
2979 entry, so);
2980 }
2981
2982 ralloc_free(so->base.ir.nir);
2983 free(so);
2984 }
2985
2986 static void
2987 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2988 {
2989 struct vc4_context *vc4 = vc4_context(pctx);
2990 vc4->prog.bind_fs = hwcso;
2991 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2992 }
2993
2994 static void
2995 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2996 {
2997 struct vc4_context *vc4 = vc4_context(pctx);
2998 vc4->prog.bind_vs = hwcso;
2999 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
3000 }
3001
3002 void
3003 vc4_program_init(struct pipe_context *pctx)
3004 {
3005 struct vc4_context *vc4 = vc4_context(pctx);
3006
3007 pctx->create_vs_state = vc4_shader_state_create;
3008 pctx->delete_vs_state = vc4_shader_state_delete;
3009
3010 pctx->create_fs_state = vc4_shader_state_create;
3011 pctx->delete_fs_state = vc4_shader_state_delete;
3012
3013 pctx->bind_fs_state = vc4_fp_state_bind;
3014 pctx->bind_vs_state = vc4_vp_state_bind;
3015
3016 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
3017 fs_cache_compare);
3018 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
3019 vs_cache_compare);
3020 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
3021 fs_inputs_compare);
3022 }
3023
3024 void
3025 vc4_program_fini(struct pipe_context *pctx)
3026 {
3027 struct vc4_context *vc4 = vc4_context(pctx);
3028
3029 hash_table_foreach(vc4->fs_cache, entry) {
3030 struct vc4_compiled_shader *shader = entry->data;
3031 vc4_bo_unreference(&shader->bo);
3032 ralloc_free(shader);
3033 _mesa_hash_table_remove(vc4->fs_cache, entry);
3034 }
3035
3036 hash_table_foreach(vc4->vs_cache, entry) {
3037 struct vc4_compiled_shader *shader = entry->data;
3038 vc4_bo_unreference(&shader->bo);
3039 ralloc_free(shader);
3040 _mesa_hash_table_remove(vc4->vs_cache, entry);
3041 }
3042 }