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vc4: Avoid making temporaries for assignments to NIR registers.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
38 #include "vc4_qpu.h"
39 #include "vc4_qir.h"
40 #include "mesa/state_tracker/st_glsl_types.h"
41
42 static struct qreg
43 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
44 static void
45 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
46
47 static void
48 resize_qreg_array(struct vc4_compile *c,
49 struct qreg **regs,
50 uint32_t *size,
51 uint32_t decl_size)
52 {
53 if (*size >= decl_size)
54 return;
55
56 uint32_t old_size = *size;
57 *size = MAX2(*size * 2, decl_size);
58 *regs = reralloc(c, *regs, struct qreg, *size);
59 if (!*regs) {
60 fprintf(stderr, "Malloc failure\n");
61 abort();
62 }
63
64 for (uint32_t i = old_size; i < *size; i++)
65 (*regs)[i] = c->undef;
66 }
67
68 static struct qreg
69 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
70 {
71 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
72 uint32_t offset = nir_intrinsic_base(intr);
73 struct vc4_compiler_ubo_range *range = NULL;
74 unsigned i;
75 for (i = 0; i < c->num_uniform_ranges; i++) {
76 range = &c->ubo_ranges[i];
77 if (offset >= range->src_offset &&
78 offset < range->src_offset + range->size) {
79 break;
80 }
81 }
82 /* The driver-location-based offset always has to be within a declared
83 * uniform range.
84 */
85 assert(range);
86 if (!range->used) {
87 range->used = true;
88 range->dst_offset = c->next_ubo_dst_offset;
89 c->next_ubo_dst_offset += range->size;
90 c->num_ubo_ranges++;
91 }
92
93 offset -= range->src_offset;
94
95 /* Adjust for where we stored the TGSI register base. */
96 indirect_offset = qir_ADD(c, indirect_offset,
97 qir_uniform_ui(c, (range->dst_offset +
98 offset)));
99
100 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
101 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
102 indirect_offset = qir_MIN(c, indirect_offset,
103 qir_uniform_ui(c, (range->dst_offset +
104 range->size - 4)));
105
106 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
107 c->num_texture_samples++;
108 return qir_TEX_RESULT(c);
109 }
110
111 nir_ssa_def *
112 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
113 {
114 switch (swiz) {
115 default:
116 case PIPE_SWIZZLE_NONE:
117 fprintf(stderr, "warning: unknown swizzle\n");
118 /* FALLTHROUGH */
119 case PIPE_SWIZZLE_0:
120 return nir_imm_float(b, 0.0);
121 case PIPE_SWIZZLE_1:
122 return nir_imm_float(b, 1.0);
123 case PIPE_SWIZZLE_X:
124 case PIPE_SWIZZLE_Y:
125 case PIPE_SWIZZLE_Z:
126 case PIPE_SWIZZLE_W:
127 return srcs[swiz];
128 }
129 }
130
131 static struct qreg *
132 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
133 {
134 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
135 def->num_components);
136 _mesa_hash_table_insert(c->def_ht, def, qregs);
137 return qregs;
138 }
139
140 /**
141 * This function is responsible for getting QIR results into the associated
142 * storage for a NIR instruction.
143 *
144 * If it's a NIR SSA def, then we just set the associated hash table entry to
145 * the new result.
146 *
147 * If it's a NIR reg, then we need to update the existing qreg assigned to the
148 * NIR destination with the incoming value. To do that without introducing
149 * new MOVs, we require that the incoming qreg either be a uniform, or be
150 * SSA-defined by the previous QIR instruction in the block and rewritable by
151 * this function. That lets us sneak ahead and insert the SF flag beforehand
152 * (knowing that the previous instruction doesn't depend on flags) and rewrite
153 * its destination to be the NIR reg's destination
154 */
155 static void
156 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
157 struct qreg result)
158 {
159 struct qinst *last_inst = NULL;
160 if (!list_empty(&c->cur_block->instructions))
161 last_inst = (struct qinst *)c->cur_block->instructions.prev;
162
163 assert(result.file == QFILE_UNIF ||
164 (result.file == QFILE_TEMP &&
165 last_inst && last_inst == c->defs[result.index]));
166
167 if (dest->is_ssa) {
168 assert(chan < dest->ssa.num_components);
169
170 struct qreg *qregs;
171 struct hash_entry *entry =
172 _mesa_hash_table_search(c->def_ht, &dest->ssa);
173
174 if (entry)
175 qregs = entry->data;
176 else
177 qregs = ntq_init_ssa_def(c, &dest->ssa);
178
179 qregs[chan] = result;
180 } else {
181 nir_register *reg = dest->reg.reg;
182 assert(dest->reg.base_offset == 0);
183 assert(reg->num_array_elems == 0);
184 struct hash_entry *entry =
185 _mesa_hash_table_search(c->def_ht, reg);
186 struct qreg *qregs = entry->data;
187
188 /* Insert a MOV if the source wasn't an SSA def in the
189 * previous instruction.
190 */
191 if (result.file == QFILE_UNIF) {
192 result = qir_MOV(c, result);
193 last_inst = c->defs[result.index];
194 }
195
196 /* We know they're both temps, so just rewrite index. */
197 c->defs[last_inst->dst.index] = NULL;
198 last_inst->dst.index = qregs[chan].index;
199
200 /* If we're in control flow, then make this update of the reg
201 * conditional on the execution mask.
202 */
203 if (c->execute.file != QFILE_NULL) {
204 last_inst->dst.index = qregs[chan].index;
205
206 /* Set the flags to the current exec mask. To insert
207 * the SF, we temporarily remove our SSA instruction.
208 */
209 list_del(&last_inst->link);
210 qir_SF(c, c->execute);
211 list_addtail(&last_inst->link,
212 &c->cur_block->instructions);
213
214 last_inst->cond = QPU_COND_ZS;
215 last_inst->cond_is_exec_mask = true;
216 }
217 }
218 }
219
220 static struct qreg *
221 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
222 {
223 if (dest->is_ssa) {
224 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
225 for (int i = 0; i < dest->ssa.num_components; i++)
226 qregs[i] = c->undef;
227 return qregs;
228 } else {
229 nir_register *reg = dest->reg.reg;
230 assert(dest->reg.base_offset == 0);
231 assert(reg->num_array_elems == 0);
232 struct hash_entry *entry =
233 _mesa_hash_table_search(c->def_ht, reg);
234 return entry->data;
235 }
236 }
237
238 static struct qreg
239 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
240 {
241 struct hash_entry *entry;
242 if (src.is_ssa) {
243 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
244 assert(i < src.ssa->num_components);
245 } else {
246 nir_register *reg = src.reg.reg;
247 entry = _mesa_hash_table_search(c->def_ht, reg);
248 assert(reg->num_array_elems == 0);
249 assert(src.reg.base_offset == 0);
250 assert(i < reg->num_components);
251 }
252
253 struct qreg *qregs = entry->data;
254 return qregs[i];
255 }
256
257 static struct qreg
258 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
259 unsigned src)
260 {
261 assert(util_is_power_of_two(instr->dest.write_mask));
262 unsigned chan = ffs(instr->dest.write_mask) - 1;
263 struct qreg r = ntq_get_src(c, instr->src[src].src,
264 instr->src[src].swizzle[chan]);
265
266 assert(!instr->src[src].abs);
267 assert(!instr->src[src].negate);
268
269 return r;
270 };
271
272 static inline struct qreg
273 qir_SAT(struct vc4_compile *c, struct qreg val)
274 {
275 return qir_FMAX(c,
276 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
277 qir_uniform_f(c, 0.0));
278 }
279
280 static struct qreg
281 ntq_rcp(struct vc4_compile *c, struct qreg x)
282 {
283 struct qreg r = qir_RCP(c, x);
284
285 /* Apply a Newton-Raphson step to improve the accuracy. */
286 r = qir_FMUL(c, r, qir_FSUB(c,
287 qir_uniform_f(c, 2.0),
288 qir_FMUL(c, x, r)));
289
290 return r;
291 }
292
293 static struct qreg
294 ntq_rsq(struct vc4_compile *c, struct qreg x)
295 {
296 struct qreg r = qir_RSQ(c, x);
297
298 /* Apply a Newton-Raphson step to improve the accuracy. */
299 r = qir_FMUL(c, r, qir_FSUB(c,
300 qir_uniform_f(c, 1.5),
301 qir_FMUL(c,
302 qir_uniform_f(c, 0.5),
303 qir_FMUL(c, x,
304 qir_FMUL(c, r, r)))));
305
306 return r;
307 }
308
309 static struct qreg
310 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
311 {
312 struct qreg src0_hi = qir_SHR(c, src0,
313 qir_uniform_ui(c, 24));
314 struct qreg src1_hi = qir_SHR(c, src1,
315 qir_uniform_ui(c, 24));
316
317 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
318 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
319 struct qreg lolo = qir_MUL24(c, src0, src1);
320
321 return qir_ADD(c, lolo, qir_SHL(c,
322 qir_ADD(c, hilo, lohi),
323 qir_uniform_ui(c, 24)));
324 }
325
326 static struct qreg
327 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
328 {
329 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
330 qir_uniform_ui(c, 8)));
331 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
332 }
333
334 /**
335 * Emits a lowered TXF_MS from an MSAA texture.
336 *
337 * The addressing math has been lowered in NIR, and now we just need to read
338 * it like a UBO.
339 */
340 static void
341 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
342 {
343 uint32_t tile_width = 32;
344 uint32_t tile_height = 32;
345 uint32_t tile_size = (tile_height * tile_width *
346 VC4_MAX_SAMPLES * sizeof(uint32_t));
347
348 unsigned unit = instr->texture_index;
349 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
350 uint32_t w_tiles = w / tile_width;
351 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
352 uint32_t h_tiles = h / tile_height;
353 uint32_t size = w_tiles * h_tiles * tile_size;
354
355 struct qreg addr;
356 assert(instr->num_srcs == 1);
357 assert(instr->src[0].src_type == nir_tex_src_coord);
358 addr = ntq_get_src(c, instr->src[0].src, 0);
359
360 /* Perform the clamping required by kernel validation. */
361 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
362 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
363
364 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
365
366 struct qreg tex = qir_TEX_RESULT(c);
367 c->num_texture_samples++;
368
369 enum pipe_format format = c->key->tex[unit].format;
370 if (util_format_is_depth_or_stencil(format)) {
371 struct qreg scaled = ntq_scale_depth_texture(c, tex);
372 for (int i = 0; i < 4; i++)
373 ntq_store_dest(c, &instr->dest, i, qir_MOV(c, scaled));
374 } else {
375 for (int i = 0; i < 4; i++)
376 ntq_store_dest(c, &instr->dest, i,
377 qir_UNPACK_8_F(c, tex, i));
378 }
379 }
380
381 static void
382 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
383 {
384 struct qreg s, t, r, lod, compare;
385 bool is_txb = false, is_txl = false;
386 unsigned unit = instr->texture_index;
387
388 if (instr->op == nir_texop_txf) {
389 ntq_emit_txf(c, instr);
390 return;
391 }
392
393 for (unsigned i = 0; i < instr->num_srcs; i++) {
394 switch (instr->src[i].src_type) {
395 case nir_tex_src_coord:
396 s = ntq_get_src(c, instr->src[i].src, 0);
397 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
398 t = qir_uniform_f(c, 0.5);
399 else
400 t = ntq_get_src(c, instr->src[i].src, 1);
401 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
402 r = ntq_get_src(c, instr->src[i].src, 2);
403 break;
404 case nir_tex_src_bias:
405 lod = ntq_get_src(c, instr->src[i].src, 0);
406 is_txb = true;
407 break;
408 case nir_tex_src_lod:
409 lod = ntq_get_src(c, instr->src[i].src, 0);
410 is_txl = true;
411 break;
412 case nir_tex_src_comparitor:
413 compare = ntq_get_src(c, instr->src[i].src, 0);
414 break;
415 default:
416 unreachable("unknown texture source");
417 }
418 }
419
420 if (c->key->tex[unit].force_first_level) {
421 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
422 is_txl = true;
423 is_txb = false;
424 }
425
426 struct qreg texture_u[] = {
427 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
428 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
429 qir_uniform(c, QUNIFORM_CONSTANT, 0),
430 qir_uniform(c, QUNIFORM_CONSTANT, 0),
431 };
432 uint32_t next_texture_u = 0;
433
434 /* There is no native support for GL texture rectangle coordinates, so
435 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
436 * 1]).
437 */
438 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
439 s = qir_FMUL(c, s,
440 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
441 t = qir_FMUL(c, t,
442 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
443 }
444
445 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
446 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
447 unit | (is_txl << 16));
448 }
449
450 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
451 qir_TEX_R(c, r, texture_u[next_texture_u++]);
452 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
453 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
454 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
455 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
456 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
457 texture_u[next_texture_u++]);
458 }
459
460 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
461 s = qir_SAT(c, s);
462 }
463
464 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
465 t = qir_SAT(c, t);
466 }
467
468 qir_TEX_T(c, t, texture_u[next_texture_u++]);
469
470 if (is_txl || is_txb)
471 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
472
473 qir_TEX_S(c, s, texture_u[next_texture_u++]);
474
475 c->num_texture_samples++;
476 struct qreg tex = qir_TEX_RESULT(c);
477
478 enum pipe_format format = c->key->tex[unit].format;
479
480 struct qreg *dest = ntq_get_dest(c, &instr->dest);
481 if (util_format_is_depth_or_stencil(format)) {
482 struct qreg normalized = ntq_scale_depth_texture(c, tex);
483 struct qreg depth_output;
484
485 struct qreg u0 = qir_uniform_f(c, 0.0f);
486 struct qreg u1 = qir_uniform_f(c, 1.0f);
487 if (c->key->tex[unit].compare_mode) {
488 switch (c->key->tex[unit].compare_func) {
489 case PIPE_FUNC_NEVER:
490 depth_output = qir_uniform_f(c, 0.0f);
491 break;
492 case PIPE_FUNC_ALWAYS:
493 depth_output = u1;
494 break;
495 case PIPE_FUNC_EQUAL:
496 qir_SF(c, qir_FSUB(c, compare, normalized));
497 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
498 break;
499 case PIPE_FUNC_NOTEQUAL:
500 qir_SF(c, qir_FSUB(c, compare, normalized));
501 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
502 break;
503 case PIPE_FUNC_GREATER:
504 qir_SF(c, qir_FSUB(c, compare, normalized));
505 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
506 break;
507 case PIPE_FUNC_GEQUAL:
508 qir_SF(c, qir_FSUB(c, normalized, compare));
509 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
510 break;
511 case PIPE_FUNC_LESS:
512 qir_SF(c, qir_FSUB(c, compare, normalized));
513 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
514 break;
515 case PIPE_FUNC_LEQUAL:
516 qir_SF(c, qir_FSUB(c, normalized, compare));
517 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
518 break;
519 }
520 } else {
521 depth_output = normalized;
522 }
523
524 for (int i = 0; i < 4; i++)
525 dest[i] = depth_output;
526 } else {
527 for (int i = 0; i < 4; i++)
528 dest[i] = qir_UNPACK_8_F(c, tex, i);
529 }
530 }
531
532 /**
533 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
534 * to zero).
535 */
536 static struct qreg
537 ntq_ffract(struct vc4_compile *c, struct qreg src)
538 {
539 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
540 struct qreg diff = qir_FSUB(c, src, trunc);
541 qir_SF(c, diff);
542 return qir_MOV(c, qir_SEL(c, QPU_COND_NS,
543 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
544 diff));
545 }
546
547 /**
548 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
549 * zero).
550 */
551 static struct qreg
552 ntq_ffloor(struct vc4_compile *c, struct qreg src)
553 {
554 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
555
556 /* This will be < 0 if we truncated and the truncation was of a value
557 * that was < 0 in the first place.
558 */
559 qir_SF(c, qir_FSUB(c, src, trunc));
560
561 return qir_MOV(c, qir_SEL(c, QPU_COND_NS,
562 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
563 trunc));
564 }
565
566 /**
567 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
568 * zero).
569 */
570 static struct qreg
571 ntq_fceil(struct vc4_compile *c, struct qreg src)
572 {
573 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
574
575 /* This will be < 0 if we truncated and the truncation was of a value
576 * that was > 0 in the first place.
577 */
578 qir_SF(c, qir_FSUB(c, trunc, src));
579
580 return qir_MOV(c, qir_SEL(c, QPU_COND_NS,
581 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
582 trunc));
583 }
584
585 static struct qreg
586 ntq_fsin(struct vc4_compile *c, struct qreg src)
587 {
588 float coeff[] = {
589 -2.0 * M_PI,
590 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
591 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
592 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
593 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
594 };
595
596 struct qreg scaled_x =
597 qir_FMUL(c,
598 src,
599 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
600
601 struct qreg x = qir_FADD(c,
602 ntq_ffract(c, scaled_x),
603 qir_uniform_f(c, -0.5));
604 struct qreg x2 = qir_FMUL(c, x, x);
605 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
606 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
607 x = qir_FMUL(c, x, x2);
608 sum = qir_FADD(c,
609 sum,
610 qir_FMUL(c,
611 x,
612 qir_uniform_f(c, coeff[i])));
613 }
614 return sum;
615 }
616
617 static struct qreg
618 ntq_fcos(struct vc4_compile *c, struct qreg src)
619 {
620 float coeff[] = {
621 -1.0f,
622 pow(2.0 * M_PI, 2) / (2 * 1),
623 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
624 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
625 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
626 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
627 };
628
629 struct qreg scaled_x =
630 qir_FMUL(c, src,
631 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
632 struct qreg x_frac = qir_FADD(c,
633 ntq_ffract(c, scaled_x),
634 qir_uniform_f(c, -0.5));
635
636 struct qreg sum = qir_uniform_f(c, coeff[0]);
637 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
638 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
639 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
640 if (i != 1)
641 x = qir_FMUL(c, x, x2);
642
643 struct qreg mul = qir_FMUL(c,
644 x,
645 qir_uniform_f(c, coeff[i]));
646 if (i == 0)
647 sum = mul;
648 else
649 sum = qir_FADD(c, sum, mul);
650 }
651 return sum;
652 }
653
654 static struct qreg
655 ntq_fsign(struct vc4_compile *c, struct qreg src)
656 {
657 struct qreg t = qir_get_temp(c);
658
659 qir_SF(c, src);
660 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
661 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
662 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
663 return qir_MOV(c, t);
664 }
665
666 static void
667 emit_vertex_input(struct vc4_compile *c, int attr)
668 {
669 enum pipe_format format = c->vs_key->attr_formats[attr];
670 uint32_t attr_size = util_format_get_blocksize(format);
671
672 c->vattr_sizes[attr] = align(attr_size, 4);
673 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
674 c->inputs[attr * 4 + i] =
675 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
676 c->num_inputs++;
677 }
678 }
679
680 static void
681 emit_fragcoord_input(struct vc4_compile *c, int attr)
682 {
683 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
684 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
685 c->inputs[attr * 4 + 2] =
686 qir_FMUL(c,
687 qir_ITOF(c, qir_FRAG_Z(c)),
688 qir_uniform_f(c, 1.0 / 0xffffff));
689 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
690 }
691
692 static struct qreg
693 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
694 uint8_t swizzle)
695 {
696 uint32_t i = c->num_input_slots++;
697 struct qreg vary = {
698 QFILE_VARY,
699 i
700 };
701
702 if (c->num_input_slots >= c->input_slots_array_size) {
703 c->input_slots_array_size =
704 MAX2(4, c->input_slots_array_size * 2);
705
706 c->input_slots = reralloc(c, c->input_slots,
707 struct vc4_varying_slot,
708 c->input_slots_array_size);
709 }
710
711 c->input_slots[i].slot = slot;
712 c->input_slots[i].swizzle = swizzle;
713
714 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
715 }
716
717 static void
718 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
719 {
720 for (int i = 0; i < 4; i++) {
721 c->inputs[attr * 4 + i] =
722 emit_fragment_varying(c, slot, i);
723 c->num_inputs++;
724 }
725 }
726
727 static void
728 add_output(struct vc4_compile *c,
729 uint32_t decl_offset,
730 uint8_t slot,
731 uint8_t swizzle)
732 {
733 uint32_t old_array_size = c->outputs_array_size;
734 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
735 decl_offset + 1);
736
737 if (old_array_size != c->outputs_array_size) {
738 c->output_slots = reralloc(c,
739 c->output_slots,
740 struct vc4_varying_slot,
741 c->outputs_array_size);
742 }
743
744 c->output_slots[decl_offset].slot = slot;
745 c->output_slots[decl_offset].swizzle = swizzle;
746 }
747
748 static void
749 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
750 {
751 unsigned array_id = c->num_uniform_ranges++;
752 if (array_id >= c->ubo_ranges_array_size) {
753 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
754 array_id + 1);
755 c->ubo_ranges = reralloc(c, c->ubo_ranges,
756 struct vc4_compiler_ubo_range,
757 c->ubo_ranges_array_size);
758 }
759
760 c->ubo_ranges[array_id].dst_offset = 0;
761 c->ubo_ranges[array_id].src_offset = start;
762 c->ubo_ranges[array_id].size = size;
763 c->ubo_ranges[array_id].used = false;
764 }
765
766 static bool
767 ntq_src_is_only_ssa_def_user(nir_src *src)
768 {
769 if (!src->is_ssa)
770 return false;
771
772 if (!list_empty(&src->ssa->if_uses))
773 return false;
774
775 return (src->ssa->uses.next == &src->use_link &&
776 src->ssa->uses.next->next == &src->ssa->uses);
777 }
778
779 /**
780 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
781 * bit set.
782 *
783 * However, as an optimization, it tries to find the instructions generating
784 * the sources to be packed and just emit the pack flag there, if possible.
785 */
786 static void
787 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
788 {
789 struct qreg result = qir_get_temp(c);
790 struct nir_alu_instr *vec4 = NULL;
791
792 /* If packing from a vec4 op (as expected), identify it so that we can
793 * peek back at what generated its sources.
794 */
795 if (instr->src[0].src.is_ssa &&
796 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
797 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
798 nir_op_vec4) {
799 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
800 }
801
802 /* If the pack is replicating the same channel 4 times, use the 8888
803 * pack flag. This is common for blending using the alpha
804 * channel.
805 */
806 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
807 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
808 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
809 struct qreg rep = ntq_get_src(c,
810 instr->src[0].src,
811 instr->src[0].swizzle[0]);
812 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
813 return;
814 }
815
816 for (int i = 0; i < 4; i++) {
817 int swiz = instr->src[0].swizzle[i];
818 struct qreg src;
819 if (vec4) {
820 src = ntq_get_src(c, vec4->src[swiz].src,
821 vec4->src[swiz].swizzle[0]);
822 } else {
823 src = ntq_get_src(c, instr->src[0].src, swiz);
824 }
825
826 if (vec4 &&
827 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
828 src.file == QFILE_TEMP &&
829 c->defs[src.index] &&
830 qir_is_mul(c->defs[src.index]) &&
831 !c->defs[src.index]->dst.pack) {
832 struct qinst *rewrite = c->defs[src.index];
833 c->defs[src.index] = NULL;
834 rewrite->dst = result;
835 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
836 continue;
837 }
838
839 qir_PACK_8_F(c, result, src, i);
840 }
841
842 ntq_store_dest(c, &instr->dest.dest, 0, qir_MOV(c, result));
843 }
844
845 /** Handles sign-extended bitfield extracts for 16 bits. */
846 static struct qreg
847 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
848 struct qreg bits)
849 {
850 assert(bits.file == QFILE_UNIF &&
851 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
852 c->uniform_data[bits.index] == 16);
853
854 assert(offset.file == QFILE_UNIF &&
855 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
856 int offset_bit = c->uniform_data[offset.index];
857 assert(offset_bit % 16 == 0);
858
859 return qir_UNPACK_16_I(c, base, offset_bit / 16);
860 }
861
862 /** Handles unsigned bitfield extracts for 8 bits. */
863 static struct qreg
864 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
865 struct qreg bits)
866 {
867 assert(bits.file == QFILE_UNIF &&
868 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
869 c->uniform_data[bits.index] == 8);
870
871 assert(offset.file == QFILE_UNIF &&
872 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
873 int offset_bit = c->uniform_data[offset.index];
874 assert(offset_bit % 8 == 0);
875
876 return qir_UNPACK_8_I(c, base, offset_bit / 8);
877 }
878
879 /**
880 * If compare_instr is a valid comparison instruction, emits the
881 * compare_instr's comparison and returns the sel_instr's return value based
882 * on the compare_instr's result.
883 */
884 static bool
885 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
886 nir_alu_instr *compare_instr,
887 nir_alu_instr *sel_instr)
888 {
889 enum qpu_cond cond;
890
891 switch (compare_instr->op) {
892 case nir_op_feq:
893 case nir_op_ieq:
894 case nir_op_seq:
895 cond = QPU_COND_ZS;
896 break;
897 case nir_op_fne:
898 case nir_op_ine:
899 case nir_op_sne:
900 cond = QPU_COND_ZC;
901 break;
902 case nir_op_fge:
903 case nir_op_ige:
904 case nir_op_uge:
905 case nir_op_sge:
906 cond = QPU_COND_NC;
907 break;
908 case nir_op_flt:
909 case nir_op_ilt:
910 case nir_op_slt:
911 cond = QPU_COND_NS;
912 break;
913 default:
914 return false;
915 }
916
917 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
918 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
919
920 unsigned unsized_type =
921 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
922 if (unsized_type == nir_type_float)
923 qir_SF(c, qir_FSUB(c, src0, src1));
924 else
925 qir_SF(c, qir_SUB(c, src0, src1));
926
927 switch (sel_instr->op) {
928 case nir_op_seq:
929 case nir_op_sne:
930 case nir_op_sge:
931 case nir_op_slt:
932 *dest = qir_SEL(c, cond,
933 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
934 break;
935
936 case nir_op_bcsel:
937 *dest = qir_SEL(c, cond,
938 ntq_get_alu_src(c, sel_instr, 1),
939 ntq_get_alu_src(c, sel_instr, 2));
940 break;
941
942 default:
943 *dest = qir_SEL(c, cond,
944 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
945 break;
946 }
947
948 /* Make the temporary for nir_store_dest(). */
949 *dest = qir_MOV(c, *dest);
950
951 return true;
952 }
953
954 /**
955 * Attempts to fold a comparison generating a boolean result into the
956 * condition code for selecting between two values, instead of comparing the
957 * boolean result against 0 to generate the condition code.
958 */
959 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
960 struct qreg *src)
961 {
962 if (!instr->src[0].src.is_ssa)
963 goto out;
964 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
965 goto out;
966 nir_alu_instr *compare =
967 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
968 if (!compare)
969 goto out;
970
971 struct qreg dest;
972 if (ntq_emit_comparison(c, &dest, compare, instr))
973 return dest;
974
975 out:
976 qir_SF(c, src[0]);
977 return qir_MOV(c, qir_SEL(c, QPU_COND_NS, src[1], src[2]));
978 }
979
980 static struct qreg
981 ntq_fddx(struct vc4_compile *c, struct qreg src)
982 {
983 /* Make sure that we have a bare temp to use for MUL rotation, so it
984 * can be allocated to an accumulator.
985 */
986 if (src.pack || src.file != QFILE_TEMP)
987 src = qir_MOV(c, src);
988
989 struct qreg from_left = qir_ROT_MUL(c, src, 1);
990 struct qreg from_right = qir_ROT_MUL(c, src, 15);
991
992 /* Distinguish left/right pixels of the quad. */
993 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
994 qir_uniform_ui(c, 1)));
995
996 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
997 qir_FSUB(c, from_right, src),
998 qir_FSUB(c, src, from_left)));
999 }
1000
1001 static struct qreg
1002 ntq_fddy(struct vc4_compile *c, struct qreg src)
1003 {
1004 if (src.pack || src.file != QFILE_TEMP)
1005 src = qir_MOV(c, src);
1006
1007 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
1008 struct qreg from_top = qir_ROT_MUL(c, src, 14);
1009
1010 /* Distinguish top/bottom pixels of the quad. */
1011 qir_SF(c, qir_AND(c,
1012 qir_reg(QFILE_QPU_ELEMENT, 0),
1013 qir_uniform_ui(c, 2)));
1014
1015 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1016 qir_FSUB(c, from_top, src),
1017 qir_FSUB(c, src, from_bottom)));
1018 }
1019
1020 static void
1021 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
1022 {
1023 /* This should always be lowered to ALU operations for VC4. */
1024 assert(!instr->dest.saturate);
1025
1026 /* Vectors are special in that they have non-scalarized writemasks,
1027 * and just take the first swizzle channel for each argument in order
1028 * into each writemask channel.
1029 */
1030 if (instr->op == nir_op_vec2 ||
1031 instr->op == nir_op_vec3 ||
1032 instr->op == nir_op_vec4) {
1033 struct qreg srcs[4];
1034 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1035 srcs[i] = ntq_get_src(c, instr->src[i].src,
1036 instr->src[i].swizzle[0]);
1037 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1038 ntq_store_dest(c, &instr->dest.dest, i,
1039 qir_MOV(c, srcs[i]));
1040 return;
1041 }
1042
1043 if (instr->op == nir_op_pack_unorm_4x8) {
1044 ntq_emit_pack_unorm_4x8(c, instr);
1045 return;
1046 }
1047
1048 if (instr->op == nir_op_unpack_unorm_4x8) {
1049 struct qreg src = ntq_get_src(c, instr->src[0].src,
1050 instr->src[0].swizzle[0]);
1051 for (int i = 0; i < 4; i++) {
1052 if (instr->dest.write_mask & (1 << i))
1053 ntq_store_dest(c, &instr->dest.dest, i,
1054 qir_UNPACK_8_F(c, src, i));
1055 }
1056 return;
1057 }
1058
1059 /* General case: We can just grab the one used channel per src. */
1060 struct qreg src[nir_op_infos[instr->op].num_inputs];
1061 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1062 src[i] = ntq_get_alu_src(c, instr, i);
1063 }
1064
1065 struct qreg result;
1066
1067 switch (instr->op) {
1068 case nir_op_fmov:
1069 case nir_op_imov:
1070 result = qir_MOV(c, src[0]);
1071 break;
1072 case nir_op_fmul:
1073 result = qir_FMUL(c, src[0], src[1]);
1074 break;
1075 case nir_op_fadd:
1076 result = qir_FADD(c, src[0], src[1]);
1077 break;
1078 case nir_op_fsub:
1079 result = qir_FSUB(c, src[0], src[1]);
1080 break;
1081 case nir_op_fmin:
1082 result = qir_FMIN(c, src[0], src[1]);
1083 break;
1084 case nir_op_fmax:
1085 result = qir_FMAX(c, src[0], src[1]);
1086 break;
1087
1088 case nir_op_f2i:
1089 case nir_op_f2u:
1090 result = qir_FTOI(c, src[0]);
1091 break;
1092 case nir_op_i2f:
1093 case nir_op_u2f:
1094 result = qir_ITOF(c, src[0]);
1095 break;
1096 case nir_op_b2f:
1097 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1098 break;
1099 case nir_op_b2i:
1100 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1101 break;
1102 case nir_op_i2b:
1103 case nir_op_f2b:
1104 qir_SF(c, src[0]);
1105 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC,
1106 qir_uniform_ui(c, ~0),
1107 qir_uniform_ui(c, 0)));
1108 break;
1109
1110 case nir_op_iadd:
1111 result = qir_ADD(c, src[0], src[1]);
1112 break;
1113 case nir_op_ushr:
1114 result = qir_SHR(c, src[0], src[1]);
1115 break;
1116 case nir_op_isub:
1117 result = qir_SUB(c, src[0], src[1]);
1118 break;
1119 case nir_op_ishr:
1120 result = qir_ASR(c, src[0], src[1]);
1121 break;
1122 case nir_op_ishl:
1123 result = qir_SHL(c, src[0], src[1]);
1124 break;
1125 case nir_op_imin:
1126 result = qir_MIN(c, src[0], src[1]);
1127 break;
1128 case nir_op_imax:
1129 result = qir_MAX(c, src[0], src[1]);
1130 break;
1131 case nir_op_iand:
1132 result = qir_AND(c, src[0], src[1]);
1133 break;
1134 case nir_op_ior:
1135 result = qir_OR(c, src[0], src[1]);
1136 break;
1137 case nir_op_ixor:
1138 result = qir_XOR(c, src[0], src[1]);
1139 break;
1140 case nir_op_inot:
1141 result = qir_NOT(c, src[0]);
1142 break;
1143
1144 case nir_op_imul:
1145 result = ntq_umul(c, src[0], src[1]);
1146 break;
1147
1148 case nir_op_seq:
1149 case nir_op_sne:
1150 case nir_op_sge:
1151 case nir_op_slt:
1152 case nir_op_feq:
1153 case nir_op_fne:
1154 case nir_op_fge:
1155 case nir_op_flt:
1156 case nir_op_ieq:
1157 case nir_op_ine:
1158 case nir_op_ige:
1159 case nir_op_uge:
1160 case nir_op_ilt:
1161 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1162 fprintf(stderr, "Bad comparison instruction\n");
1163 }
1164 break;
1165
1166 case nir_op_bcsel:
1167 result = ntq_emit_bcsel(c, instr, src);
1168 break;
1169 case nir_op_fcsel:
1170 qir_SF(c, src[0]);
1171 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC, src[1], src[2]));
1172 break;
1173
1174 case nir_op_frcp:
1175 result = ntq_rcp(c, src[0]);
1176 break;
1177 case nir_op_frsq:
1178 result = ntq_rsq(c, src[0]);
1179 break;
1180 case nir_op_fexp2:
1181 result = qir_EXP2(c, src[0]);
1182 break;
1183 case nir_op_flog2:
1184 result = qir_LOG2(c, src[0]);
1185 break;
1186
1187 case nir_op_ftrunc:
1188 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1189 break;
1190 case nir_op_fceil:
1191 result = ntq_fceil(c, src[0]);
1192 break;
1193 case nir_op_ffract:
1194 result = ntq_ffract(c, src[0]);
1195 break;
1196 case nir_op_ffloor:
1197 result = ntq_ffloor(c, src[0]);
1198 break;
1199
1200 case nir_op_fsin:
1201 result = ntq_fsin(c, src[0]);
1202 break;
1203 case nir_op_fcos:
1204 result = ntq_fcos(c, src[0]);
1205 break;
1206
1207 case nir_op_fsign:
1208 result = ntq_fsign(c, src[0]);
1209 break;
1210
1211 case nir_op_fabs:
1212 result = qir_FMAXABS(c, src[0], src[0]);
1213 break;
1214 case nir_op_iabs:
1215 result = qir_MAX(c, src[0],
1216 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1217 break;
1218
1219 case nir_op_ibitfield_extract:
1220 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1221 break;
1222
1223 case nir_op_ubitfield_extract:
1224 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1225 break;
1226
1227 case nir_op_usadd_4x8:
1228 result = qir_V8ADDS(c, src[0], src[1]);
1229 break;
1230
1231 case nir_op_ussub_4x8:
1232 result = qir_V8SUBS(c, src[0], src[1]);
1233 break;
1234
1235 case nir_op_umin_4x8:
1236 result = qir_V8MIN(c, src[0], src[1]);
1237 break;
1238
1239 case nir_op_umax_4x8:
1240 result = qir_V8MAX(c, src[0], src[1]);
1241 break;
1242
1243 case nir_op_umul_unorm_4x8:
1244 result = qir_V8MULD(c, src[0], src[1]);
1245 break;
1246
1247 case nir_op_fddx:
1248 case nir_op_fddx_coarse:
1249 case nir_op_fddx_fine:
1250 result = ntq_fddx(c, src[0]);
1251 break;
1252
1253 case nir_op_fddy:
1254 case nir_op_fddy_coarse:
1255 case nir_op_fddy_fine:
1256 result = ntq_fddy(c, src[0]);
1257 break;
1258
1259 default:
1260 fprintf(stderr, "unknown NIR ALU inst: ");
1261 nir_print_instr(&instr->instr, stderr);
1262 fprintf(stderr, "\n");
1263 abort();
1264 }
1265
1266 /* We have a scalar result, so the instruction should only have a
1267 * single channel written to.
1268 */
1269 assert(util_is_power_of_two(instr->dest.write_mask));
1270 ntq_store_dest(c, &instr->dest.dest,
1271 ffs(instr->dest.write_mask) - 1, result);
1272 }
1273
1274 static void
1275 emit_frag_end(struct vc4_compile *c)
1276 {
1277 struct qreg color;
1278 if (c->output_color_index != -1) {
1279 color = c->outputs[c->output_color_index];
1280 } else {
1281 color = qir_uniform_ui(c, 0);
1282 }
1283
1284 uint32_t discard_cond = QPU_COND_ALWAYS;
1285 if (c->s->info.fs.uses_discard) {
1286 qir_SF(c, c->discard);
1287 discard_cond = QPU_COND_ZS;
1288 }
1289
1290 if (c->fs_key->stencil_enabled) {
1291 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1292 qir_uniform(c, QUNIFORM_STENCIL, 0));
1293 if (c->fs_key->stencil_twoside) {
1294 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1295 qir_uniform(c, QUNIFORM_STENCIL, 1));
1296 }
1297 if (c->fs_key->stencil_full_writemasks) {
1298 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1299 qir_uniform(c, QUNIFORM_STENCIL, 2));
1300 }
1301 }
1302
1303 if (c->output_sample_mask_index != -1) {
1304 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1305 }
1306
1307 if (c->fs_key->depth_enabled) {
1308 if (c->output_position_index != -1) {
1309 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1310 qir_FMUL(c,
1311 c->outputs[c->output_position_index],
1312 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1313 } else {
1314 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1315 qir_FRAG_Z(c))->cond = discard_cond;
1316 }
1317 }
1318
1319 if (!c->msaa_per_sample_output) {
1320 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1321 color)->cond = discard_cond;
1322 } else {
1323 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1324 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1325 c->sample_colors[i])->cond = discard_cond;
1326 }
1327 }
1328 }
1329
1330 static void
1331 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1332 {
1333 struct qreg packed = qir_get_temp(c);
1334
1335 for (int i = 0; i < 2; i++) {
1336 struct qreg scale =
1337 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1338
1339 struct qreg packed_chan = packed;
1340 packed_chan.pack = QPU_PACK_A_16A + i;
1341
1342 qir_FTOI_dest(c, packed_chan,
1343 qir_FMUL(c,
1344 qir_FMUL(c,
1345 c->outputs[c->output_position_index + i],
1346 scale),
1347 rcp_w));
1348 }
1349
1350 qir_VPM_WRITE(c, packed);
1351 }
1352
1353 static void
1354 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1355 {
1356 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1357 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1358
1359 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1360 c->outputs[c->output_position_index + 2],
1361 zscale),
1362 rcp_w),
1363 zoffset));
1364 }
1365
1366 static void
1367 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1368 {
1369 qir_VPM_WRITE(c, rcp_w);
1370 }
1371
1372 static void
1373 emit_point_size_write(struct vc4_compile *c)
1374 {
1375 struct qreg point_size;
1376
1377 if (c->output_point_size_index != -1)
1378 point_size = c->outputs[c->output_point_size_index];
1379 else
1380 point_size = qir_uniform_f(c, 1.0);
1381
1382 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1383 * BCM21553).
1384 */
1385 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1386
1387 qir_VPM_WRITE(c, point_size);
1388 }
1389
1390 /**
1391 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1392 *
1393 * The simulator insists that there be at least one vertex attribute, so
1394 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1395 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1396 * to consume it here.
1397 */
1398 static void
1399 emit_stub_vpm_read(struct vc4_compile *c)
1400 {
1401 if (c->num_inputs)
1402 return;
1403
1404 c->vattr_sizes[0] = 4;
1405 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1406 c->num_inputs++;
1407 }
1408
1409 static void
1410 emit_vert_end(struct vc4_compile *c,
1411 struct vc4_varying_slot *fs_inputs,
1412 uint32_t num_fs_inputs)
1413 {
1414 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1415
1416 emit_stub_vpm_read(c);
1417
1418 emit_scaled_viewport_write(c, rcp_w);
1419 emit_zs_write(c, rcp_w);
1420 emit_rcp_wc_write(c, rcp_w);
1421 if (c->vs_key->per_vertex_point_size)
1422 emit_point_size_write(c);
1423
1424 for (int i = 0; i < num_fs_inputs; i++) {
1425 struct vc4_varying_slot *input = &fs_inputs[i];
1426 int j;
1427
1428 for (j = 0; j < c->num_outputs; j++) {
1429 struct vc4_varying_slot *output =
1430 &c->output_slots[j];
1431
1432 if (input->slot == output->slot &&
1433 input->swizzle == output->swizzle) {
1434 qir_VPM_WRITE(c, c->outputs[j]);
1435 break;
1436 }
1437 }
1438 /* Emit padding if we didn't find a declared VS output for
1439 * this FS input.
1440 */
1441 if (j == c->num_outputs)
1442 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1443 }
1444 }
1445
1446 static void
1447 emit_coord_end(struct vc4_compile *c)
1448 {
1449 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1450
1451 emit_stub_vpm_read(c);
1452
1453 for (int i = 0; i < 4; i++)
1454 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1455
1456 emit_scaled_viewport_write(c, rcp_w);
1457 emit_zs_write(c, rcp_w);
1458 emit_rcp_wc_write(c, rcp_w);
1459 if (c->vs_key->per_vertex_point_size)
1460 emit_point_size_write(c);
1461 }
1462
1463 static void
1464 vc4_optimize_nir(struct nir_shader *s)
1465 {
1466 bool progress;
1467
1468 do {
1469 progress = false;
1470
1471 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1472 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1473 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1474 NIR_PASS(progress, s, nir_copy_prop);
1475 NIR_PASS(progress, s, nir_opt_remove_phis);
1476 NIR_PASS(progress, s, nir_opt_dce);
1477 NIR_PASS(progress, s, nir_opt_dead_cf);
1478 NIR_PASS(progress, s, nir_opt_cse);
1479 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1480 NIR_PASS(progress, s, nir_opt_algebraic);
1481 NIR_PASS(progress, s, nir_opt_constant_folding);
1482 NIR_PASS(progress, s, nir_opt_undef);
1483 } while (progress);
1484 }
1485
1486 static int
1487 driver_location_compare(const void *in_a, const void *in_b)
1488 {
1489 const nir_variable *const *a = in_a;
1490 const nir_variable *const *b = in_b;
1491
1492 return (*a)->data.driver_location - (*b)->data.driver_location;
1493 }
1494
1495 static void
1496 ntq_setup_inputs(struct vc4_compile *c)
1497 {
1498 unsigned num_entries = 0;
1499 nir_foreach_variable(var, &c->s->inputs)
1500 num_entries++;
1501
1502 nir_variable *vars[num_entries];
1503
1504 unsigned i = 0;
1505 nir_foreach_variable(var, &c->s->inputs)
1506 vars[i++] = var;
1507
1508 /* Sort the variables so that we emit the input setup in
1509 * driver_location order. This is required for VPM reads, whose data
1510 * is fetched into the VPM in driver_location (TGSI register index)
1511 * order.
1512 */
1513 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1514
1515 for (unsigned i = 0; i < num_entries; i++) {
1516 nir_variable *var = vars[i];
1517 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1518 unsigned loc = var->data.driver_location;
1519
1520 assert(array_len == 1);
1521 (void)array_len;
1522 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1523 (loc + 1) * 4);
1524
1525 if (c->stage == QSTAGE_FRAG) {
1526 if (var->data.location == VARYING_SLOT_POS) {
1527 emit_fragcoord_input(c, loc);
1528 } else if (var->data.location == VARYING_SLOT_PNTC ||
1529 (var->data.location >= VARYING_SLOT_VAR0 &&
1530 (c->fs_key->point_sprite_mask &
1531 (1 << (var->data.location -
1532 VARYING_SLOT_VAR0))))) {
1533 c->inputs[loc * 4 + 0] = c->point_x;
1534 c->inputs[loc * 4 + 1] = c->point_y;
1535 } else {
1536 emit_fragment_input(c, loc, var->data.location);
1537 }
1538 } else {
1539 emit_vertex_input(c, loc);
1540 }
1541 }
1542 }
1543
1544 static void
1545 ntq_setup_outputs(struct vc4_compile *c)
1546 {
1547 nir_foreach_variable(var, &c->s->outputs) {
1548 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1549 unsigned loc = var->data.driver_location * 4;
1550
1551 assert(array_len == 1);
1552 (void)array_len;
1553
1554 for (int i = 0; i < 4; i++)
1555 add_output(c, loc + i, var->data.location, i);
1556
1557 if (c->stage == QSTAGE_FRAG) {
1558 switch (var->data.location) {
1559 case FRAG_RESULT_COLOR:
1560 case FRAG_RESULT_DATA0:
1561 c->output_color_index = loc;
1562 break;
1563 case FRAG_RESULT_DEPTH:
1564 c->output_position_index = loc;
1565 break;
1566 case FRAG_RESULT_SAMPLE_MASK:
1567 c->output_sample_mask_index = loc;
1568 break;
1569 }
1570 } else {
1571 switch (var->data.location) {
1572 case VARYING_SLOT_POS:
1573 c->output_position_index = loc;
1574 break;
1575 case VARYING_SLOT_PSIZ:
1576 c->output_point_size_index = loc;
1577 break;
1578 }
1579 }
1580 }
1581 }
1582
1583 static void
1584 ntq_setup_uniforms(struct vc4_compile *c)
1585 {
1586 nir_foreach_variable(var, &c->s->uniforms) {
1587 uint32_t vec4_count = st_glsl_type_size(var->type);
1588 unsigned vec4_size = 4 * sizeof(float);
1589
1590 declare_uniform_range(c, var->data.driver_location * vec4_size,
1591 vec4_count * vec4_size);
1592
1593 }
1594 }
1595
1596 /**
1597 * Sets up the mapping from nir_register to struct qreg *.
1598 *
1599 * Each nir_register gets a struct qreg per 32-bit component being stored.
1600 */
1601 static void
1602 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1603 {
1604 foreach_list_typed(nir_register, nir_reg, node, list) {
1605 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1606 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1607 array_len *
1608 nir_reg->num_components);
1609
1610 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1611
1612 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1613 qregs[i] = qir_get_temp(c);
1614 }
1615 }
1616
1617 static void
1618 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1619 {
1620 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1621 for (int i = 0; i < instr->def.num_components; i++)
1622 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1623
1624 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1625 }
1626
1627 static void
1628 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1629 {
1630 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1631
1632 /* QIR needs there to be *some* value, so pick 0 (same as for
1633 * ntq_setup_registers().
1634 */
1635 for (int i = 0; i < instr->def.num_components; i++)
1636 qregs[i] = qir_uniform_ui(c, 0);
1637 }
1638
1639 static void
1640 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1641 {
1642 nir_const_value *const_offset;
1643 unsigned offset;
1644
1645 switch (instr->intrinsic) {
1646 case nir_intrinsic_load_uniform:
1647 assert(instr->num_components == 1);
1648 const_offset = nir_src_as_const_value(instr->src[0]);
1649 if (const_offset) {
1650 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1651 assert(offset % 4 == 0);
1652 /* We need dwords */
1653 offset = offset / 4;
1654 ntq_store_dest(c, &instr->dest, 0,
1655 qir_uniform(c, QUNIFORM_UNIFORM,
1656 offset));
1657 } else {
1658 ntq_store_dest(c, &instr->dest, 0,
1659 indirect_uniform_load(c, instr));
1660 }
1661 break;
1662
1663 case nir_intrinsic_load_user_clip_plane:
1664 for (int i = 0; i < instr->num_components; i++) {
1665 ntq_store_dest(c, &instr->dest, i,
1666 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1667 nir_intrinsic_ucp_id(instr) *
1668 4 + i));
1669 }
1670 break;
1671
1672 case nir_intrinsic_load_blend_const_color_r_float:
1673 case nir_intrinsic_load_blend_const_color_g_float:
1674 case nir_intrinsic_load_blend_const_color_b_float:
1675 case nir_intrinsic_load_blend_const_color_a_float:
1676 ntq_store_dest(c, &instr->dest, 0,
1677 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1678 (instr->intrinsic -
1679 nir_intrinsic_load_blend_const_color_r_float),
1680 0));
1681 break;
1682
1683 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1684 ntq_store_dest(c, &instr->dest, 0,
1685 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1686 0));
1687 break;
1688
1689 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1690 ntq_store_dest(c, &instr->dest, 0,
1691 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1692 0));
1693 break;
1694
1695 case nir_intrinsic_load_alpha_ref_float:
1696 ntq_store_dest(c, &instr->dest, 0,
1697 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1698 break;
1699
1700 case nir_intrinsic_load_sample_mask_in:
1701 ntq_store_dest(c, &instr->dest, 0,
1702 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1703 break;
1704
1705 case nir_intrinsic_load_front_face:
1706 /* The register contains 0 (front) or 1 (back), and we need to
1707 * turn it into a NIR bool where true means front.
1708 */
1709 ntq_store_dest(c, &instr->dest, 0,
1710 qir_ADD(c,
1711 qir_uniform_ui(c, -1),
1712 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1713 break;
1714
1715 case nir_intrinsic_load_input:
1716 assert(instr->num_components == 1);
1717 const_offset = nir_src_as_const_value(instr->src[0]);
1718 assert(const_offset && "vc4 doesn't support indirect inputs");
1719 if (c->stage == QSTAGE_FRAG &&
1720 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1721 assert(const_offset->u32[0] == 0);
1722 /* Reads of the per-sample color need to be done in
1723 * order.
1724 */
1725 int sample_index = (nir_intrinsic_base(instr) -
1726 VC4_NIR_TLB_COLOR_READ_INPUT);
1727 for (int i = 0; i <= sample_index; i++) {
1728 if (c->color_reads[i].file == QFILE_NULL) {
1729 c->color_reads[i] =
1730 qir_TLB_COLOR_READ(c);
1731 }
1732 }
1733 ntq_store_dest(c, &instr->dest, 0,
1734 qir_MOV(c, c->color_reads[sample_index]));
1735 } else {
1736 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1737 int comp = nir_intrinsic_component(instr);
1738 ntq_store_dest(c, &instr->dest, 0,
1739 qir_MOV(c, c->inputs[offset * 4 + comp]));
1740 }
1741 break;
1742
1743 case nir_intrinsic_store_output:
1744 const_offset = nir_src_as_const_value(instr->src[1]);
1745 assert(const_offset && "vc4 doesn't support indirect outputs");
1746 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1747
1748 /* MSAA color outputs are the only case where we have an
1749 * output that's not lowered to being a store of a single 32
1750 * bit value.
1751 */
1752 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1753 assert(offset == c->output_color_index);
1754 for (int i = 0; i < 4; i++) {
1755 c->sample_colors[i] =
1756 qir_MOV(c, ntq_get_src(c, instr->src[0],
1757 i));
1758 }
1759 } else {
1760 offset = offset * 4 + nir_intrinsic_component(instr);
1761 assert(instr->num_components == 1);
1762 c->outputs[offset] =
1763 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1764 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1765 }
1766 break;
1767
1768 case nir_intrinsic_discard:
1769 if (c->execute.file != QFILE_NULL) {
1770 qir_SF(c, c->execute);
1771 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1772 qir_uniform_ui(c, ~0));
1773 } else {
1774 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1775 }
1776 break;
1777
1778 case nir_intrinsic_discard_if: {
1779 /* true (~0) if we're discarding */
1780 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1781
1782 if (c->execute.file != QFILE_NULL) {
1783 /* execute == 0 means the channel is active. Invert
1784 * the condition so that we can use zero as "executing
1785 * and discarding."
1786 */
1787 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1788 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1789 } else {
1790 qir_OR_dest(c, c->discard, c->discard,
1791 ntq_get_src(c, instr->src[0], 0));
1792 }
1793
1794 break;
1795 }
1796
1797 default:
1798 fprintf(stderr, "Unknown intrinsic: ");
1799 nir_print_instr(&instr->instr, stderr);
1800 fprintf(stderr, "\n");
1801 break;
1802 }
1803 }
1804
1805 /* Clears (activates) the execute flags for any channels whose jump target
1806 * matches this block.
1807 */
1808 static void
1809 ntq_activate_execute_for_block(struct vc4_compile *c)
1810 {
1811 qir_SF(c, qir_SUB(c,
1812 c->execute,
1813 qir_uniform_ui(c, c->cur_block->index)));
1814 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1815 }
1816
1817 static void
1818 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1819 {
1820 if (!c->vc4->screen->has_control_flow) {
1821 fprintf(stderr,
1822 "IF statement support requires updated kernel.\n");
1823 return;
1824 }
1825
1826 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1827 bool empty_else_block =
1828 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1829 exec_list_is_empty(&nir_else_block->instr_list));
1830
1831 struct qblock *then_block = qir_new_block(c);
1832 struct qblock *after_block = qir_new_block(c);
1833 struct qblock *else_block;
1834 if (empty_else_block)
1835 else_block = after_block;
1836 else
1837 else_block = qir_new_block(c);
1838
1839 bool was_top_level = false;
1840 if (c->execute.file == QFILE_NULL) {
1841 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1842 was_top_level = true;
1843 }
1844
1845 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1846 * 0) channels, and then update execute flags for those to point to
1847 * the ELSE block.
1848 */
1849 qir_SF(c, qir_OR(c,
1850 c->execute,
1851 ntq_get_src(c, if_stmt->condition, 0)));
1852 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1853 qir_uniform_ui(c, else_block->index));
1854
1855 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1856 * through.
1857 */
1858 qir_SF(c, c->execute);
1859 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1860 qir_link_blocks(c->cur_block, else_block);
1861 qir_link_blocks(c->cur_block, then_block);
1862
1863 /* Process the THEN block. */
1864 qir_set_emit_block(c, then_block);
1865 ntq_emit_cf_list(c, &if_stmt->then_list);
1866
1867 if (!empty_else_block) {
1868 /* Handle the end of the THEN block. First, all currently
1869 * active channels update their execute flags to point to
1870 * ENDIF
1871 */
1872 qir_SF(c, c->execute);
1873 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1874 qir_uniform_ui(c, after_block->index));
1875
1876 /* If everything points at ENDIF, then jump there immediately. */
1877 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1878 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1879 qir_link_blocks(c->cur_block, after_block);
1880 qir_link_blocks(c->cur_block, else_block);
1881
1882 qir_set_emit_block(c, else_block);
1883 ntq_activate_execute_for_block(c);
1884 ntq_emit_cf_list(c, &if_stmt->else_list);
1885 }
1886
1887 qir_link_blocks(c->cur_block, after_block);
1888
1889 qir_set_emit_block(c, after_block);
1890 if (was_top_level)
1891 c->execute = c->undef;
1892 else
1893 ntq_activate_execute_for_block(c);
1894
1895 }
1896
1897 static void
1898 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1899 {
1900 switch (jump->type) {
1901 case nir_jump_break:
1902 qir_SF(c, c->execute);
1903 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1904 qir_uniform_ui(c, c->loop_break_block->index));
1905 break;
1906
1907 case nir_jump_continue:
1908 qir_SF(c, c->execute);
1909 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1910 qir_uniform_ui(c, c->loop_cont_block->index));
1911 break;
1912
1913 case nir_jump_return:
1914 unreachable("All returns shouold be lowered\n");
1915 }
1916 }
1917
1918 static void
1919 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1920 {
1921 switch (instr->type) {
1922 case nir_instr_type_alu:
1923 ntq_emit_alu(c, nir_instr_as_alu(instr));
1924 break;
1925
1926 case nir_instr_type_intrinsic:
1927 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1928 break;
1929
1930 case nir_instr_type_load_const:
1931 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1932 break;
1933
1934 case nir_instr_type_ssa_undef:
1935 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1936 break;
1937
1938 case nir_instr_type_tex:
1939 ntq_emit_tex(c, nir_instr_as_tex(instr));
1940 break;
1941
1942 case nir_instr_type_jump:
1943 ntq_emit_jump(c, nir_instr_as_jump(instr));
1944 break;
1945
1946 default:
1947 fprintf(stderr, "Unknown NIR instr type: ");
1948 nir_print_instr(instr, stderr);
1949 fprintf(stderr, "\n");
1950 abort();
1951 }
1952 }
1953
1954 static void
1955 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1956 {
1957 nir_foreach_instr(instr, block) {
1958 ntq_emit_instr(c, instr);
1959 }
1960 }
1961
1962 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
1963
1964 static void
1965 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
1966 {
1967 if (!c->vc4->screen->has_control_flow) {
1968 fprintf(stderr,
1969 "loop support requires updated kernel.\n");
1970 ntq_emit_cf_list(c, &loop->body);
1971 return;
1972 }
1973
1974 bool was_top_level = false;
1975 if (c->execute.file == QFILE_NULL) {
1976 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1977 was_top_level = true;
1978 }
1979
1980 struct qblock *save_loop_cont_block = c->loop_cont_block;
1981 struct qblock *save_loop_break_block = c->loop_break_block;
1982
1983 c->loop_cont_block = qir_new_block(c);
1984 c->loop_break_block = qir_new_block(c);
1985
1986 qir_link_blocks(c->cur_block, c->loop_cont_block);
1987 qir_set_emit_block(c, c->loop_cont_block);
1988 ntq_activate_execute_for_block(c);
1989
1990 ntq_emit_cf_list(c, &loop->body);
1991
1992 /* If anything had explicitly continued, or is here at the end of the
1993 * loop, then we need to loop again. SF updates are masked by the
1994 * instruction's condition, so we can do the OR of the two conditions
1995 * within SF.
1996 */
1997 qir_SF(c, c->execute);
1998 struct qinst *cont_check =
1999 qir_SUB_dest(c,
2000 c->undef,
2001 c->execute,
2002 qir_uniform_ui(c, c->loop_cont_block->index));
2003 cont_check->cond = QPU_COND_ZC;
2004 cont_check->sf = true;
2005
2006 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
2007 qir_link_blocks(c->cur_block, c->loop_cont_block);
2008 qir_link_blocks(c->cur_block, c->loop_break_block);
2009
2010 qir_set_emit_block(c, c->loop_break_block);
2011 if (was_top_level)
2012 c->execute = c->undef;
2013 else
2014 ntq_activate_execute_for_block(c);
2015
2016 c->loop_break_block = save_loop_break_block;
2017 c->loop_cont_block = save_loop_cont_block;
2018 }
2019
2020 static void
2021 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
2022 {
2023 fprintf(stderr, "FUNCTIONS not handled.\n");
2024 abort();
2025 }
2026
2027 static void
2028 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
2029 {
2030 foreach_list_typed(nir_cf_node, node, node, list) {
2031 switch (node->type) {
2032 case nir_cf_node_block:
2033 ntq_emit_block(c, nir_cf_node_as_block(node));
2034 break;
2035
2036 case nir_cf_node_if:
2037 ntq_emit_if(c, nir_cf_node_as_if(node));
2038 break;
2039
2040 case nir_cf_node_loop:
2041 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2042 break;
2043
2044 case nir_cf_node_function:
2045 ntq_emit_function(c, nir_cf_node_as_function(node));
2046 break;
2047
2048 default:
2049 fprintf(stderr, "Unknown NIR node type\n");
2050 abort();
2051 }
2052 }
2053 }
2054
2055 static void
2056 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2057 {
2058 ntq_setup_registers(c, &impl->registers);
2059 ntq_emit_cf_list(c, &impl->body);
2060 }
2061
2062 static void
2063 nir_to_qir(struct vc4_compile *c)
2064 {
2065 if (c->stage == QSTAGE_FRAG && c->s->info.fs.uses_discard)
2066 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2067
2068 ntq_setup_inputs(c);
2069 ntq_setup_outputs(c);
2070 ntq_setup_uniforms(c);
2071 ntq_setup_registers(c, &c->s->registers);
2072
2073 /* Find the main function and emit the body. */
2074 nir_foreach_function(function, c->s) {
2075 assert(strcmp(function->name, "main") == 0);
2076 assert(function->impl);
2077 ntq_emit_impl(c, function->impl);
2078 }
2079 }
2080
2081 static const nir_shader_compiler_options nir_options = {
2082 .lower_extract_byte = true,
2083 .lower_extract_word = true,
2084 .lower_ffma = true,
2085 .lower_flrp32 = true,
2086 .lower_fpow = true,
2087 .lower_fsat = true,
2088 .lower_fsqrt = true,
2089 .lower_negate = true,
2090 .native_integers = true,
2091 };
2092
2093 const void *
2094 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2095 enum pipe_shader_ir ir, unsigned shader)
2096 {
2097 return &nir_options;
2098 }
2099
2100 static int
2101 count_nir_instrs(nir_shader *nir)
2102 {
2103 int count = 0;
2104 nir_foreach_function(function, nir) {
2105 if (!function->impl)
2106 continue;
2107 nir_foreach_block(block, function->impl) {
2108 nir_foreach_instr(instr, block)
2109 count++;
2110 }
2111 }
2112 return count;
2113 }
2114
2115 static struct vc4_compile *
2116 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2117 struct vc4_key *key)
2118 {
2119 struct vc4_compile *c = qir_compile_init();
2120
2121 c->vc4 = vc4;
2122 c->stage = stage;
2123 c->shader_state = &key->shader_state->base;
2124 c->program_id = key->shader_state->program_id;
2125 c->variant_id =
2126 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2127
2128 c->key = key;
2129 switch (stage) {
2130 case QSTAGE_FRAG:
2131 c->fs_key = (struct vc4_fs_key *)key;
2132 if (c->fs_key->is_points) {
2133 c->point_x = emit_fragment_varying(c, ~0, 0);
2134 c->point_y = emit_fragment_varying(c, ~0, 0);
2135 } else if (c->fs_key->is_lines) {
2136 c->line_x = emit_fragment_varying(c, ~0, 0);
2137 }
2138 break;
2139 case QSTAGE_VERT:
2140 c->vs_key = (struct vc4_vs_key *)key;
2141 break;
2142 case QSTAGE_COORD:
2143 c->vs_key = (struct vc4_vs_key *)key;
2144 break;
2145 }
2146
2147 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2148
2149 if (stage == QSTAGE_FRAG)
2150 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2151
2152 struct nir_lower_tex_options tex_options = {
2153 /* We would need to implement txs, but we don't want the
2154 * int/float conversions
2155 */
2156 .lower_rect = false,
2157
2158 .lower_txp = ~0,
2159
2160 /* Apply swizzles to all samplers. */
2161 .swizzle_result = ~0,
2162 };
2163
2164 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2165 * The format swizzling applies before sRGB decode, and
2166 * ARB_texture_swizzle is the last thing before returning the sample.
2167 */
2168 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2169 enum pipe_format format = c->key->tex[i].format;
2170
2171 if (!format)
2172 continue;
2173
2174 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2175
2176 for (int j = 0; j < 4; j++) {
2177 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2178
2179 if (arb_swiz <= 3) {
2180 tex_options.swizzles[i][j] =
2181 format_swizzle[arb_swiz];
2182 } else {
2183 tex_options.swizzles[i][j] = arb_swiz;
2184 }
2185 }
2186
2187 if (util_format_is_srgb(format))
2188 tex_options.lower_srgb |= (1 << i);
2189 }
2190
2191 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2192
2193 if (c->fs_key && c->fs_key->light_twoside)
2194 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2195
2196 if (c->vs_key && c->vs_key->clamp_color)
2197 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2198
2199 if (c->key->ucp_enables) {
2200 if (stage == QSTAGE_FRAG) {
2201 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2202 } else {
2203 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
2204 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2205 nir_var_shader_out);
2206 }
2207 }
2208
2209 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2210 * which only handles a vec4 at a time. Similarly, VS output
2211 * scalarizing must happen after nir_lower_clip_vs.
2212 */
2213 if (c->stage == QSTAGE_FRAG)
2214 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2215 else
2216 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2217
2218 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2219 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2220 NIR_PASS_V(c->s, nir_lower_idiv);
2221
2222 vc4_optimize_nir(c->s);
2223
2224 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2225
2226 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2227 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2228 qir_get_stage_name(c->stage),
2229 c->program_id, c->variant_id,
2230 count_nir_instrs(c->s));
2231 }
2232
2233 if (vc4_debug & VC4_DEBUG_NIR) {
2234 fprintf(stderr, "%s prog %d/%d NIR:\n",
2235 qir_get_stage_name(c->stage),
2236 c->program_id, c->variant_id);
2237 nir_print_shader(c->s, stderr);
2238 }
2239
2240 nir_to_qir(c);
2241
2242 switch (stage) {
2243 case QSTAGE_FRAG:
2244 emit_frag_end(c);
2245 break;
2246 case QSTAGE_VERT:
2247 emit_vert_end(c,
2248 c->vs_key->fs_inputs->input_slots,
2249 c->vs_key->fs_inputs->num_inputs);
2250 break;
2251 case QSTAGE_COORD:
2252 emit_coord_end(c);
2253 break;
2254 }
2255
2256 if (vc4_debug & VC4_DEBUG_QIR) {
2257 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2258 qir_get_stage_name(c->stage),
2259 c->program_id, c->variant_id);
2260 qir_dump(c);
2261 fprintf(stderr, "\n");
2262 }
2263
2264 qir_optimize(c);
2265 qir_lower_uniforms(c);
2266
2267 qir_schedule_instructions(c);
2268 qir_emit_uniform_stream_resets(c);
2269
2270 if (vc4_debug & VC4_DEBUG_QIR) {
2271 fprintf(stderr, "%s prog %d/%d QIR:\n",
2272 qir_get_stage_name(c->stage),
2273 c->program_id, c->variant_id);
2274 qir_dump(c);
2275 fprintf(stderr, "\n");
2276 }
2277
2278 qir_reorder_uniforms(c);
2279 vc4_generate_code(vc4, c);
2280
2281 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2282 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2283 qir_get_stage_name(c->stage),
2284 c->program_id, c->variant_id,
2285 c->qpu_inst_count);
2286 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2287 qir_get_stage_name(c->stage),
2288 c->program_id, c->variant_id,
2289 c->num_uniforms);
2290 }
2291
2292 ralloc_free(c->s);
2293
2294 return c;
2295 }
2296
2297 static void *
2298 vc4_shader_state_create(struct pipe_context *pctx,
2299 const struct pipe_shader_state *cso)
2300 {
2301 struct vc4_context *vc4 = vc4_context(pctx);
2302 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2303 if (!so)
2304 return NULL;
2305
2306 so->program_id = vc4->next_uncompiled_program_id++;
2307
2308 nir_shader *s;
2309
2310 if (cso->type == PIPE_SHADER_IR_NIR) {
2311 /* The backend takes ownership of the NIR shader on state
2312 * creation.
2313 */
2314 s = cso->ir.nir;
2315 } else {
2316 assert(cso->type == PIPE_SHADER_IR_TGSI);
2317
2318 if (vc4_debug & VC4_DEBUG_TGSI) {
2319 fprintf(stderr, "prog %d TGSI:\n",
2320 so->program_id);
2321 tgsi_dump(cso->tokens, 0);
2322 fprintf(stderr, "\n");
2323 }
2324 s = tgsi_to_nir(cso->tokens, &nir_options);
2325 }
2326
2327 NIR_PASS_V(s, nir_opt_global_to_local);
2328 NIR_PASS_V(s, nir_convert_to_ssa);
2329 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2330
2331 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2332
2333 vc4_optimize_nir(s);
2334
2335 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_local);
2336
2337 /* Garbage collect dead instructions */
2338 nir_sweep(s);
2339
2340 so->base.type = PIPE_SHADER_IR_NIR;
2341 so->base.ir.nir = s;
2342
2343 if (vc4_debug & VC4_DEBUG_NIR) {
2344 fprintf(stderr, "%s prog %d NIR:\n",
2345 gl_shader_stage_name(s->stage),
2346 so->program_id);
2347 nir_print_shader(s, stderr);
2348 fprintf(stderr, "\n");
2349 }
2350
2351 return so;
2352 }
2353
2354 static void
2355 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2356 struct vc4_compile *c)
2357 {
2358 int count = c->num_uniforms;
2359 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2360
2361 uinfo->count = count;
2362 uinfo->data = ralloc_array(shader, uint32_t, count);
2363 memcpy(uinfo->data, c->uniform_data,
2364 count * sizeof(*uinfo->data));
2365 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2366 memcpy(uinfo->contents, c->uniform_contents,
2367 count * sizeof(*uinfo->contents));
2368 uinfo->num_texture_samples = c->num_texture_samples;
2369
2370 vc4_set_shader_uniform_dirty_flags(shader);
2371 }
2372
2373 static void
2374 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2375 struct vc4_compiled_shader *shader)
2376 {
2377 struct vc4_fs_inputs inputs;
2378
2379 memset(&inputs, 0, sizeof(inputs));
2380 inputs.input_slots = ralloc_array(shader,
2381 struct vc4_varying_slot,
2382 c->num_input_slots);
2383
2384 bool input_live[c->num_input_slots];
2385
2386 memset(input_live, 0, sizeof(input_live));
2387 qir_for_each_inst_inorder(inst, c) {
2388 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2389 if (inst->src[i].file == QFILE_VARY)
2390 input_live[inst->src[i].index] = true;
2391 }
2392 }
2393
2394 for (int i = 0; i < c->num_input_slots; i++) {
2395 struct vc4_varying_slot *slot = &c->input_slots[i];
2396
2397 if (!input_live[i])
2398 continue;
2399
2400 /* Skip non-VS-output inputs. */
2401 if (slot->slot == (uint8_t)~0)
2402 continue;
2403
2404 if (slot->slot == VARYING_SLOT_COL0 ||
2405 slot->slot == VARYING_SLOT_COL1 ||
2406 slot->slot == VARYING_SLOT_BFC0 ||
2407 slot->slot == VARYING_SLOT_BFC1) {
2408 shader->color_inputs |= (1 << inputs.num_inputs);
2409 }
2410
2411 inputs.input_slots[inputs.num_inputs] = *slot;
2412 inputs.num_inputs++;
2413 }
2414 shader->num_inputs = inputs.num_inputs;
2415
2416 /* Add our set of inputs to the set of all inputs seen. This way, we
2417 * can have a single pointer that identifies an FS inputs set,
2418 * allowing VS to avoid recompiling when the FS is recompiled (or a
2419 * new one is bound using separate shader objects) but the inputs
2420 * don't change.
2421 */
2422 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2423 if (entry) {
2424 shader->fs_inputs = entry->key;
2425 ralloc_free(inputs.input_slots);
2426 } else {
2427 struct vc4_fs_inputs *alloc_inputs;
2428
2429 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2430 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2431 ralloc_steal(alloc_inputs, inputs.input_slots);
2432 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2433
2434 shader->fs_inputs = alloc_inputs;
2435 }
2436 }
2437
2438 static struct vc4_compiled_shader *
2439 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2440 struct vc4_key *key)
2441 {
2442 struct hash_table *ht;
2443 uint32_t key_size;
2444 if (stage == QSTAGE_FRAG) {
2445 ht = vc4->fs_cache;
2446 key_size = sizeof(struct vc4_fs_key);
2447 } else {
2448 ht = vc4->vs_cache;
2449 key_size = sizeof(struct vc4_vs_key);
2450 }
2451
2452 struct vc4_compiled_shader *shader;
2453 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2454 if (entry)
2455 return entry->data;
2456
2457 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2458 shader = rzalloc(NULL, struct vc4_compiled_shader);
2459
2460 shader->program_id = vc4->next_compiled_program_id++;
2461 if (stage == QSTAGE_FRAG) {
2462 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2463
2464 /* Note: the temporary clone in c->s has been freed. */
2465 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2466 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2467 shader->disable_early_z = true;
2468 } else {
2469 shader->num_inputs = c->num_inputs;
2470
2471 shader->vattr_offsets[0] = 0;
2472 for (int i = 0; i < 8; i++) {
2473 shader->vattr_offsets[i + 1] =
2474 shader->vattr_offsets[i] + c->vattr_sizes[i];
2475
2476 if (c->vattr_sizes[i])
2477 shader->vattrs_live |= (1 << i);
2478 }
2479 }
2480
2481 copy_uniform_state_to_shader(shader, c);
2482 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2483 c->qpu_inst_count * sizeof(uint64_t));
2484
2485 /* Copy the compiler UBO range state to the compiled shader, dropping
2486 * out arrays that were never referenced by an indirect load.
2487 *
2488 * (Note that QIR dead code elimination of an array access still
2489 * leaves that array alive, though)
2490 */
2491 if (c->num_ubo_ranges) {
2492 shader->num_ubo_ranges = c->num_ubo_ranges;
2493 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2494 c->num_ubo_ranges);
2495 uint32_t j = 0;
2496 for (int i = 0; i < c->num_uniform_ranges; i++) {
2497 struct vc4_compiler_ubo_range *range =
2498 &c->ubo_ranges[i];
2499 if (!range->used)
2500 continue;
2501
2502 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2503 shader->ubo_ranges[j].src_offset = range->src_offset;
2504 shader->ubo_ranges[j].size = range->size;
2505 shader->ubo_size += c->ubo_ranges[i].size;
2506 j++;
2507 }
2508 }
2509 if (shader->ubo_size) {
2510 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2511 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2512 qir_get_stage_name(c->stage),
2513 c->program_id, c->variant_id,
2514 shader->ubo_size / 4);
2515 }
2516 }
2517
2518 qir_compile_destroy(c);
2519
2520 struct vc4_key *dup_key;
2521 dup_key = ralloc_size(shader, key_size);
2522 memcpy(dup_key, key, key_size);
2523 _mesa_hash_table_insert(ht, dup_key, shader);
2524
2525 return shader;
2526 }
2527
2528 static void
2529 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2530 struct vc4_texture_stateobj *texstate)
2531 {
2532 for (int i = 0; i < texstate->num_textures; i++) {
2533 struct pipe_sampler_view *sampler = texstate->textures[i];
2534 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2535 struct pipe_sampler_state *sampler_state =
2536 texstate->samplers[i];
2537
2538 if (!sampler)
2539 continue;
2540
2541 key->tex[i].format = sampler->format;
2542 key->tex[i].swizzle[0] = sampler->swizzle_r;
2543 key->tex[i].swizzle[1] = sampler->swizzle_g;
2544 key->tex[i].swizzle[2] = sampler->swizzle_b;
2545 key->tex[i].swizzle[3] = sampler->swizzle_a;
2546
2547 if (sampler->texture->nr_samples > 1) {
2548 key->tex[i].msaa_width = sampler->texture->width0;
2549 key->tex[i].msaa_height = sampler->texture->height0;
2550 } else if (sampler){
2551 key->tex[i].compare_mode = sampler_state->compare_mode;
2552 key->tex[i].compare_func = sampler_state->compare_func;
2553 key->tex[i].wrap_s = sampler_state->wrap_s;
2554 key->tex[i].wrap_t = sampler_state->wrap_t;
2555 key->tex[i].force_first_level =
2556 vc4_sampler->force_first_level;
2557 }
2558 }
2559
2560 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2561 }
2562
2563 static void
2564 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2565 {
2566 struct vc4_job *job = vc4->job;
2567 struct vc4_fs_key local_key;
2568 struct vc4_fs_key *key = &local_key;
2569
2570 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2571 VC4_DIRTY_BLEND |
2572 VC4_DIRTY_FRAMEBUFFER |
2573 VC4_DIRTY_ZSA |
2574 VC4_DIRTY_RASTERIZER |
2575 VC4_DIRTY_SAMPLE_MASK |
2576 VC4_DIRTY_FRAGTEX |
2577 VC4_DIRTY_UNCOMPILED_FS))) {
2578 return;
2579 }
2580
2581 memset(key, 0, sizeof(*key));
2582 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2583 key->base.shader_state = vc4->prog.bind_fs;
2584 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2585 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2586 prim_mode <= PIPE_PRIM_LINE_STRIP);
2587 key->blend = vc4->blend->rt[0];
2588 if (vc4->blend->logicop_enable) {
2589 key->logicop_func = vc4->blend->logicop_func;
2590 } else {
2591 key->logicop_func = PIPE_LOGICOP_COPY;
2592 }
2593 if (job->msaa) {
2594 key->msaa = vc4->rasterizer->base.multisample;
2595 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2596 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2597 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2598 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2599 }
2600
2601 if (vc4->framebuffer.cbufs[0])
2602 key->color_format = vc4->framebuffer.cbufs[0]->format;
2603
2604 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2605 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2606 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2607 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2608 key->stencil_enabled);
2609 if (vc4->zsa->base.alpha.enabled) {
2610 key->alpha_test = true;
2611 key->alpha_test_func = vc4->zsa->base.alpha.func;
2612 }
2613
2614 if (key->is_points) {
2615 key->point_sprite_mask =
2616 vc4->rasterizer->base.sprite_coord_enable;
2617 key->point_coord_upper_left =
2618 (vc4->rasterizer->base.sprite_coord_mode ==
2619 PIPE_SPRITE_COORD_UPPER_LEFT);
2620 }
2621
2622 key->light_twoside = vc4->rasterizer->base.light_twoside;
2623
2624 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2625 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2626 if (vc4->prog.fs == old_fs)
2627 return;
2628
2629 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2630
2631 if (vc4->rasterizer->base.flatshade &&
2632 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2633 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2634 }
2635
2636 if (old_fs && vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2637 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2638 }
2639
2640 static void
2641 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2642 {
2643 struct vc4_vs_key local_key;
2644 struct vc4_vs_key *key = &local_key;
2645
2646 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2647 VC4_DIRTY_RASTERIZER |
2648 VC4_DIRTY_VERTTEX |
2649 VC4_DIRTY_VTXSTATE |
2650 VC4_DIRTY_UNCOMPILED_VS |
2651 VC4_DIRTY_FS_INPUTS))) {
2652 return;
2653 }
2654
2655 memset(key, 0, sizeof(*key));
2656 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2657 key->base.shader_state = vc4->prog.bind_vs;
2658 key->fs_inputs = vc4->prog.fs->fs_inputs;
2659 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2660
2661 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2662 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2663
2664 key->per_vertex_point_size =
2665 (prim_mode == PIPE_PRIM_POINTS &&
2666 vc4->rasterizer->base.point_size_per_vertex);
2667
2668 struct vc4_compiled_shader *vs =
2669 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2670 if (vs != vc4->prog.vs) {
2671 vc4->prog.vs = vs;
2672 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2673 }
2674
2675 key->is_coord = true;
2676 /* Coord shaders don't care what the FS inputs are. */
2677 key->fs_inputs = NULL;
2678 struct vc4_compiled_shader *cs =
2679 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2680 if (cs != vc4->prog.cs) {
2681 vc4->prog.cs = cs;
2682 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2683 }
2684 }
2685
2686 void
2687 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2688 {
2689 vc4_update_compiled_fs(vc4, prim_mode);
2690 vc4_update_compiled_vs(vc4, prim_mode);
2691 }
2692
2693 static uint32_t
2694 fs_cache_hash(const void *key)
2695 {
2696 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2697 }
2698
2699 static uint32_t
2700 vs_cache_hash(const void *key)
2701 {
2702 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2703 }
2704
2705 static bool
2706 fs_cache_compare(const void *key1, const void *key2)
2707 {
2708 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2709 }
2710
2711 static bool
2712 vs_cache_compare(const void *key1, const void *key2)
2713 {
2714 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2715 }
2716
2717 static uint32_t
2718 fs_inputs_hash(const void *key)
2719 {
2720 const struct vc4_fs_inputs *inputs = key;
2721
2722 return _mesa_hash_data(inputs->input_slots,
2723 sizeof(*inputs->input_slots) *
2724 inputs->num_inputs);
2725 }
2726
2727 static bool
2728 fs_inputs_compare(const void *key1, const void *key2)
2729 {
2730 const struct vc4_fs_inputs *inputs1 = key1;
2731 const struct vc4_fs_inputs *inputs2 = key2;
2732
2733 return (inputs1->num_inputs == inputs2->num_inputs &&
2734 memcmp(inputs1->input_slots,
2735 inputs2->input_slots,
2736 sizeof(*inputs1->input_slots) *
2737 inputs1->num_inputs) == 0);
2738 }
2739
2740 static void
2741 delete_from_cache_if_matches(struct hash_table *ht,
2742 struct hash_entry *entry,
2743 struct vc4_uncompiled_shader *so)
2744 {
2745 const struct vc4_key *key = entry->key;
2746
2747 if (key->shader_state == so) {
2748 struct vc4_compiled_shader *shader = entry->data;
2749 _mesa_hash_table_remove(ht, entry);
2750 vc4_bo_unreference(&shader->bo);
2751 ralloc_free(shader);
2752 }
2753 }
2754
2755 static void
2756 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2757 {
2758 struct vc4_context *vc4 = vc4_context(pctx);
2759 struct vc4_uncompiled_shader *so = hwcso;
2760
2761 struct hash_entry *entry;
2762 hash_table_foreach(vc4->fs_cache, entry)
2763 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2764 hash_table_foreach(vc4->vs_cache, entry)
2765 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2766
2767 ralloc_free(so->base.ir.nir);
2768 free(so);
2769 }
2770
2771 static void
2772 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2773 {
2774 struct vc4_context *vc4 = vc4_context(pctx);
2775 vc4->prog.bind_fs = hwcso;
2776 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2777 }
2778
2779 static void
2780 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2781 {
2782 struct vc4_context *vc4 = vc4_context(pctx);
2783 vc4->prog.bind_vs = hwcso;
2784 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2785 }
2786
2787 void
2788 vc4_program_init(struct pipe_context *pctx)
2789 {
2790 struct vc4_context *vc4 = vc4_context(pctx);
2791
2792 pctx->create_vs_state = vc4_shader_state_create;
2793 pctx->delete_vs_state = vc4_shader_state_delete;
2794
2795 pctx->create_fs_state = vc4_shader_state_create;
2796 pctx->delete_fs_state = vc4_shader_state_delete;
2797
2798 pctx->bind_fs_state = vc4_fp_state_bind;
2799 pctx->bind_vs_state = vc4_vp_state_bind;
2800
2801 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2802 fs_cache_compare);
2803 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2804 vs_cache_compare);
2805 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
2806 fs_inputs_compare);
2807 }
2808
2809 void
2810 vc4_program_fini(struct pipe_context *pctx)
2811 {
2812 struct vc4_context *vc4 = vc4_context(pctx);
2813
2814 struct hash_entry *entry;
2815 hash_table_foreach(vc4->fs_cache, entry) {
2816 struct vc4_compiled_shader *shader = entry->data;
2817 vc4_bo_unreference(&shader->bo);
2818 ralloc_free(shader);
2819 _mesa_hash_table_remove(vc4->fs_cache, entry);
2820 }
2821
2822 hash_table_foreach(vc4->vs_cache, entry) {
2823 struct vc4_compiled_shader *shader = entry->data;
2824 vc4_bo_unreference(&shader->bo);
2825 ralloc_free(shader);
2826 _mesa_hash_table_remove(vc4->vs_cache, entry);
2827 }
2828 }