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tgsi_to_nir: Produce optimized NIR for a given pipe_screen.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/crc32.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "compiler/nir_types.h"
37 #include "nir/tgsi_to_nir.h"
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #include "mesa/state_tracker/st_glsl_types.h"
42
43 static struct qreg
44 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
45 static void
46 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
47
48 static int
49 type_size(const struct glsl_type *type)
50 {
51 return glsl_count_attribute_slots(type, false);
52 }
53
54 static int
55 uniforms_type_size(const struct glsl_type *type)
56 {
57 return st_glsl_storage_type_size(type, false);
58 }
59
60 static void
61 resize_qreg_array(struct vc4_compile *c,
62 struct qreg **regs,
63 uint32_t *size,
64 uint32_t decl_size)
65 {
66 if (*size >= decl_size)
67 return;
68
69 uint32_t old_size = *size;
70 *size = MAX2(*size * 2, decl_size);
71 *regs = reralloc(c, *regs, struct qreg, *size);
72 if (!*regs) {
73 fprintf(stderr, "Malloc failure\n");
74 abort();
75 }
76
77 for (uint32_t i = old_size; i < *size; i++)
78 (*regs)[i] = c->undef;
79 }
80
81 static void
82 ntq_emit_thrsw(struct vc4_compile *c)
83 {
84 if (!c->fs_threaded)
85 return;
86
87 /* Always thread switch after each texture operation for now.
88 *
89 * We could do better by batching a bunch of texture fetches up and
90 * then doing one thread switch and collecting all their results
91 * afterward.
92 */
93 qir_emit_nondef(c, qir_inst(QOP_THRSW, c->undef,
94 c->undef, c->undef));
95 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
96 }
97
98 static struct qreg
99 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
100 {
101 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
102 uint32_t offset = nir_intrinsic_base(intr);
103 struct vc4_compiler_ubo_range *range = NULL;
104 unsigned i;
105 for (i = 0; i < c->num_uniform_ranges; i++) {
106 range = &c->ubo_ranges[i];
107 if (offset >= range->src_offset &&
108 offset < range->src_offset + range->size) {
109 break;
110 }
111 }
112 /* The driver-location-based offset always has to be within a declared
113 * uniform range.
114 */
115 assert(range);
116 if (!range->used) {
117 range->used = true;
118 range->dst_offset = c->next_ubo_dst_offset;
119 c->next_ubo_dst_offset += range->size;
120 c->num_ubo_ranges++;
121 }
122
123 offset -= range->src_offset;
124
125 /* Adjust for where we stored the TGSI register base. */
126 indirect_offset = qir_ADD(c, indirect_offset,
127 qir_uniform_ui(c, (range->dst_offset +
128 offset)));
129
130 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
131 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
132 indirect_offset = qir_MIN_NOIMM(c, indirect_offset,
133 qir_uniform_ui(c, (range->dst_offset +
134 range->size - 4)));
135
136 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
137 indirect_offset,
138 qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
139
140 c->num_texture_samples++;
141
142 ntq_emit_thrsw(c);
143
144 return qir_TEX_RESULT(c);
145 }
146
147 static struct qreg
148 vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
149 {
150 nir_const_value *buffer_index =
151 nir_src_as_const_value(intr->src[0]);
152 assert(buffer_index->u32[0] == 1);
153 assert(c->stage == QSTAGE_FRAG);
154
155 struct qreg offset = ntq_get_src(c, intr->src[1], 0);
156
157 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
158 offset = qir_MAX(c, offset, qir_uniform_ui(c, 0));
159 offset = qir_MIN_NOIMM(c, offset,
160 qir_uniform_ui(c, c->fs_key->ubo_1_size - 4));
161
162 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
163 offset,
164 qir_uniform(c, QUNIFORM_UBO_ADDR, buffer_index->u32[0]));
165
166 c->num_texture_samples++;
167
168 ntq_emit_thrsw(c);
169
170 return qir_TEX_RESULT(c);
171 }
172
173 nir_ssa_def *
174 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
175 {
176 switch (swiz) {
177 default:
178 case PIPE_SWIZZLE_NONE:
179 fprintf(stderr, "warning: unknown swizzle\n");
180 /* FALLTHROUGH */
181 case PIPE_SWIZZLE_0:
182 return nir_imm_float(b, 0.0);
183 case PIPE_SWIZZLE_1:
184 return nir_imm_float(b, 1.0);
185 case PIPE_SWIZZLE_X:
186 case PIPE_SWIZZLE_Y:
187 case PIPE_SWIZZLE_Z:
188 case PIPE_SWIZZLE_W:
189 return srcs[swiz];
190 }
191 }
192
193 static struct qreg *
194 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
195 {
196 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
197 def->num_components);
198 _mesa_hash_table_insert(c->def_ht, def, qregs);
199 return qregs;
200 }
201
202 /**
203 * This function is responsible for getting QIR results into the associated
204 * storage for a NIR instruction.
205 *
206 * If it's a NIR SSA def, then we just set the associated hash table entry to
207 * the new result.
208 *
209 * If it's a NIR reg, then we need to update the existing qreg assigned to the
210 * NIR destination with the incoming value. To do that without introducing
211 * new MOVs, we require that the incoming qreg either be a uniform, or be
212 * SSA-defined by the previous QIR instruction in the block and rewritable by
213 * this function. That lets us sneak ahead and insert the SF flag beforehand
214 * (knowing that the previous instruction doesn't depend on flags) and rewrite
215 * its destination to be the NIR reg's destination
216 */
217 static void
218 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
219 struct qreg result)
220 {
221 struct qinst *last_inst = NULL;
222 if (!list_empty(&c->cur_block->instructions))
223 last_inst = (struct qinst *)c->cur_block->instructions.prev;
224
225 assert(result.file == QFILE_UNIF ||
226 (result.file == QFILE_TEMP &&
227 last_inst && last_inst == c->defs[result.index]));
228
229 if (dest->is_ssa) {
230 assert(chan < dest->ssa.num_components);
231
232 struct qreg *qregs;
233 struct hash_entry *entry =
234 _mesa_hash_table_search(c->def_ht, &dest->ssa);
235
236 if (entry)
237 qregs = entry->data;
238 else
239 qregs = ntq_init_ssa_def(c, &dest->ssa);
240
241 qregs[chan] = result;
242 } else {
243 nir_register *reg = dest->reg.reg;
244 assert(dest->reg.base_offset == 0);
245 assert(reg->num_array_elems == 0);
246 struct hash_entry *entry =
247 _mesa_hash_table_search(c->def_ht, reg);
248 struct qreg *qregs = entry->data;
249
250 /* Insert a MOV if the source wasn't an SSA def in the
251 * previous instruction.
252 */
253 if (result.file == QFILE_UNIF) {
254 result = qir_MOV(c, result);
255 last_inst = c->defs[result.index];
256 }
257
258 /* We know they're both temps, so just rewrite index. */
259 c->defs[last_inst->dst.index] = NULL;
260 last_inst->dst.index = qregs[chan].index;
261
262 /* If we're in control flow, then make this update of the reg
263 * conditional on the execution mask.
264 */
265 if (c->execute.file != QFILE_NULL) {
266 last_inst->dst.index = qregs[chan].index;
267
268 /* Set the flags to the current exec mask. To insert
269 * the SF, we temporarily remove our SSA instruction.
270 */
271 list_del(&last_inst->link);
272 qir_SF(c, c->execute);
273 list_addtail(&last_inst->link,
274 &c->cur_block->instructions);
275
276 last_inst->cond = QPU_COND_ZS;
277 last_inst->cond_is_exec_mask = true;
278 }
279 }
280 }
281
282 static struct qreg *
283 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
284 {
285 if (dest->is_ssa) {
286 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
287 for (int i = 0; i < dest->ssa.num_components; i++)
288 qregs[i] = c->undef;
289 return qregs;
290 } else {
291 nir_register *reg = dest->reg.reg;
292 assert(dest->reg.base_offset == 0);
293 assert(reg->num_array_elems == 0);
294 struct hash_entry *entry =
295 _mesa_hash_table_search(c->def_ht, reg);
296 return entry->data;
297 }
298 }
299
300 static struct qreg
301 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
302 {
303 struct hash_entry *entry;
304 if (src.is_ssa) {
305 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
306 assert(i < src.ssa->num_components);
307 } else {
308 nir_register *reg = src.reg.reg;
309 entry = _mesa_hash_table_search(c->def_ht, reg);
310 assert(reg->num_array_elems == 0);
311 assert(src.reg.base_offset == 0);
312 assert(i < reg->num_components);
313 }
314
315 struct qreg *qregs = entry->data;
316 return qregs[i];
317 }
318
319 static struct qreg
320 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
321 unsigned src)
322 {
323 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
324 unsigned chan = ffs(instr->dest.write_mask) - 1;
325 struct qreg r = ntq_get_src(c, instr->src[src].src,
326 instr->src[src].swizzle[chan]);
327
328 assert(!instr->src[src].abs);
329 assert(!instr->src[src].negate);
330
331 return r;
332 };
333
334 static inline struct qreg
335 qir_SAT(struct vc4_compile *c, struct qreg val)
336 {
337 return qir_FMAX(c,
338 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
339 qir_uniform_f(c, 0.0));
340 }
341
342 static struct qreg
343 ntq_rcp(struct vc4_compile *c, struct qreg x)
344 {
345 struct qreg r = qir_RCP(c, x);
346
347 /* Apply a Newton-Raphson step to improve the accuracy. */
348 r = qir_FMUL(c, r, qir_FSUB(c,
349 qir_uniform_f(c, 2.0),
350 qir_FMUL(c, x, r)));
351
352 return r;
353 }
354
355 static struct qreg
356 ntq_rsq(struct vc4_compile *c, struct qreg x)
357 {
358 struct qreg r = qir_RSQ(c, x);
359
360 /* Apply a Newton-Raphson step to improve the accuracy. */
361 r = qir_FMUL(c, r, qir_FSUB(c,
362 qir_uniform_f(c, 1.5),
363 qir_FMUL(c,
364 qir_uniform_f(c, 0.5),
365 qir_FMUL(c, x,
366 qir_FMUL(c, r, r)))));
367
368 return r;
369 }
370
371 static struct qreg
372 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
373 {
374 struct qreg src0_hi = qir_SHR(c, src0,
375 qir_uniform_ui(c, 24));
376 struct qreg src1_hi = qir_SHR(c, src1,
377 qir_uniform_ui(c, 24));
378
379 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
380 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
381 struct qreg lolo = qir_MUL24(c, src0, src1);
382
383 return qir_ADD(c, lolo, qir_SHL(c,
384 qir_ADD(c, hilo, lohi),
385 qir_uniform_ui(c, 24)));
386 }
387
388 static struct qreg
389 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
390 {
391 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
392 qir_uniform_ui(c, 8)));
393 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
394 }
395
396 /**
397 * Emits a lowered TXF_MS from an MSAA texture.
398 *
399 * The addressing math has been lowered in NIR, and now we just need to read
400 * it like a UBO.
401 */
402 static void
403 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
404 {
405 uint32_t tile_width = 32;
406 uint32_t tile_height = 32;
407 uint32_t tile_size = (tile_height * tile_width *
408 VC4_MAX_SAMPLES * sizeof(uint32_t));
409
410 unsigned unit = instr->texture_index;
411 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
412 uint32_t w_tiles = w / tile_width;
413 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
414 uint32_t h_tiles = h / tile_height;
415 uint32_t size = w_tiles * h_tiles * tile_size;
416
417 struct qreg addr;
418 assert(instr->num_srcs == 1);
419 assert(instr->src[0].src_type == nir_tex_src_coord);
420 addr = ntq_get_src(c, instr->src[0].src, 0);
421
422 /* Perform the clamping required by kernel validation. */
423 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
424 addr = qir_MIN_NOIMM(c, addr, qir_uniform_ui(c, size - 4));
425
426 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
427 addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
428
429 ntq_emit_thrsw(c);
430
431 struct qreg tex = qir_TEX_RESULT(c);
432 c->num_texture_samples++;
433
434 enum pipe_format format = c->key->tex[unit].format;
435 if (util_format_is_depth_or_stencil(format)) {
436 struct qreg scaled = ntq_scale_depth_texture(c, tex);
437 for (int i = 0; i < 4; i++)
438 ntq_store_dest(c, &instr->dest, i, qir_MOV(c, scaled));
439 } else {
440 for (int i = 0; i < 4; i++)
441 ntq_store_dest(c, &instr->dest, i,
442 qir_UNPACK_8_F(c, tex, i));
443 }
444 }
445
446 static void
447 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
448 {
449 struct qreg s, t, r, lod, compare;
450 bool is_txb = false, is_txl = false;
451 unsigned unit = instr->texture_index;
452
453 if (instr->op == nir_texop_txf) {
454 ntq_emit_txf(c, instr);
455 return;
456 }
457
458 for (unsigned i = 0; i < instr->num_srcs; i++) {
459 switch (instr->src[i].src_type) {
460 case nir_tex_src_coord:
461 s = ntq_get_src(c, instr->src[i].src, 0);
462 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
463 t = qir_uniform_f(c, 0.5);
464 else
465 t = ntq_get_src(c, instr->src[i].src, 1);
466 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
467 r = ntq_get_src(c, instr->src[i].src, 2);
468 break;
469 case nir_tex_src_bias:
470 lod = ntq_get_src(c, instr->src[i].src, 0);
471 is_txb = true;
472 break;
473 case nir_tex_src_lod:
474 lod = ntq_get_src(c, instr->src[i].src, 0);
475 is_txl = true;
476 break;
477 case nir_tex_src_comparator:
478 compare = ntq_get_src(c, instr->src[i].src, 0);
479 break;
480 default:
481 unreachable("unknown texture source");
482 }
483 }
484
485 if (c->stage != QSTAGE_FRAG && !is_txl) {
486 /* From the GLSL 1.20 spec:
487 *
488 * "If it is mip-mapped and running on the vertex shader,
489 * then the base texture is used."
490 */
491 is_txl = true;
492 lod = qir_uniform_ui(c, 0);
493 }
494
495 if (c->key->tex[unit].force_first_level) {
496 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
497 is_txl = true;
498 is_txb = false;
499 }
500
501 struct qreg texture_u[] = {
502 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
503 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
504 qir_uniform(c, QUNIFORM_CONSTANT, 0),
505 qir_uniform(c, QUNIFORM_CONSTANT, 0),
506 };
507 uint32_t next_texture_u = 0;
508
509 /* There is no native support for GL texture rectangle coordinates, so
510 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
511 * 1]).
512 */
513 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
514 s = qir_FMUL(c, s,
515 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
516 t = qir_FMUL(c, t,
517 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
518 }
519
520 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
521 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
522 unit | (is_txl << 16));
523 }
524
525 struct qinst *tmu;
526 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
527 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), r);
528 tmu->src[qir_get_tex_uniform_src(tmu)] =
529 texture_u[next_texture_u++];
530 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
531 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
532 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
533 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
534 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0),
535 qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR,
536 unit));
537 tmu->src[qir_get_tex_uniform_src(tmu)] =
538 texture_u[next_texture_u++];
539 }
540
541 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
542 s = qir_SAT(c, s);
543 }
544
545 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
546 t = qir_SAT(c, t);
547 }
548
549 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_T, 0), t);
550 tmu->src[qir_get_tex_uniform_src(tmu)] =
551 texture_u[next_texture_u++];
552
553 if (is_txl || is_txb) {
554 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_B, 0), lod);
555 tmu->src[qir_get_tex_uniform_src(tmu)] =
556 texture_u[next_texture_u++];
557 }
558
559 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_S, 0), s);
560 tmu->src[qir_get_tex_uniform_src(tmu)] = texture_u[next_texture_u++];
561
562 c->num_texture_samples++;
563
564 ntq_emit_thrsw(c);
565
566 struct qreg tex = qir_TEX_RESULT(c);
567
568 enum pipe_format format = c->key->tex[unit].format;
569
570 struct qreg *dest = ntq_get_dest(c, &instr->dest);
571 if (util_format_is_depth_or_stencil(format)) {
572 struct qreg normalized = ntq_scale_depth_texture(c, tex);
573 struct qreg depth_output;
574
575 struct qreg u0 = qir_uniform_f(c, 0.0f);
576 struct qreg u1 = qir_uniform_f(c, 1.0f);
577 if (c->key->tex[unit].compare_mode) {
578 /* From the GL_ARB_shadow spec:
579 *
580 * "Let Dt (D subscript t) be the depth texture
581 * value, in the range [0, 1]. Let R be the
582 * interpolated texture coordinate clamped to the
583 * range [0, 1]."
584 */
585 compare = qir_SAT(c, compare);
586
587 switch (c->key->tex[unit].compare_func) {
588 case PIPE_FUNC_NEVER:
589 depth_output = qir_uniform_f(c, 0.0f);
590 break;
591 case PIPE_FUNC_ALWAYS:
592 depth_output = u1;
593 break;
594 case PIPE_FUNC_EQUAL:
595 qir_SF(c, qir_FSUB(c, compare, normalized));
596 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
597 break;
598 case PIPE_FUNC_NOTEQUAL:
599 qir_SF(c, qir_FSUB(c, compare, normalized));
600 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
601 break;
602 case PIPE_FUNC_GREATER:
603 qir_SF(c, qir_FSUB(c, compare, normalized));
604 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
605 break;
606 case PIPE_FUNC_GEQUAL:
607 qir_SF(c, qir_FSUB(c, normalized, compare));
608 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
609 break;
610 case PIPE_FUNC_LESS:
611 qir_SF(c, qir_FSUB(c, compare, normalized));
612 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
613 break;
614 case PIPE_FUNC_LEQUAL:
615 qir_SF(c, qir_FSUB(c, normalized, compare));
616 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
617 break;
618 }
619 } else {
620 depth_output = normalized;
621 }
622
623 for (int i = 0; i < 4; i++)
624 dest[i] = depth_output;
625 } else {
626 for (int i = 0; i < 4; i++)
627 dest[i] = qir_UNPACK_8_F(c, tex, i);
628 }
629 }
630
631 /**
632 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
633 * to zero).
634 */
635 static struct qreg
636 ntq_ffract(struct vc4_compile *c, struct qreg src)
637 {
638 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
639 struct qreg diff = qir_FSUB(c, src, trunc);
640 qir_SF(c, diff);
641
642 qir_FADD_dest(c, diff,
643 diff, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
644
645 return qir_MOV(c, diff);
646 }
647
648 /**
649 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
650 * zero).
651 */
652 static struct qreg
653 ntq_ffloor(struct vc4_compile *c, struct qreg src)
654 {
655 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
656
657 /* This will be < 0 if we truncated and the truncation was of a value
658 * that was < 0 in the first place.
659 */
660 qir_SF(c, qir_FSUB(c, src, result));
661
662 struct qinst *sub = qir_FSUB_dest(c, result,
663 result, qir_uniform_f(c, 1.0));
664 sub->cond = QPU_COND_NS;
665
666 return qir_MOV(c, result);
667 }
668
669 /**
670 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
671 * zero).
672 */
673 static struct qreg
674 ntq_fceil(struct vc4_compile *c, struct qreg src)
675 {
676 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
677
678 /* This will be < 0 if we truncated and the truncation was of a value
679 * that was > 0 in the first place.
680 */
681 qir_SF(c, qir_FSUB(c, result, src));
682
683 qir_FADD_dest(c, result,
684 result, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
685
686 return qir_MOV(c, result);
687 }
688
689 static struct qreg
690 ntq_shrink_sincos_input_range(struct vc4_compile *c, struct qreg x)
691 {
692 /* Since we're using a Taylor approximation, we want to have a small
693 * number of coefficients and take advantage of sin/cos repeating
694 * every 2pi. We keep our x as close to 0 as we can, since the series
695 * will be less accurate as |x| increases. (Also, be careful of
696 * shifting the input x value to be tricky with sin/cos relations,
697 * because getting accurate values for x==0 is very important for SDL
698 * rendering)
699 */
700 struct qreg scaled_x =
701 qir_FMUL(c, x,
702 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
703 /* Note: FTOI truncates toward 0. */
704 struct qreg x_frac = qir_FSUB(c, scaled_x,
705 qir_ITOF(c, qir_FTOI(c, scaled_x)));
706 /* Map [0.5, 1] to [-0.5, 0] */
707 qir_SF(c, qir_FSUB(c, x_frac, qir_uniform_f(c, 0.5)));
708 qir_FSUB_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NC;
709 /* Map [-1, -0.5] to [0, 0.5] */
710 qir_SF(c, qir_FADD(c, x_frac, qir_uniform_f(c, 0.5)));
711 qir_FADD_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
712
713 return x_frac;
714 }
715
716 static struct qreg
717 ntq_fsin(struct vc4_compile *c, struct qreg src)
718 {
719 float coeff[] = {
720 2.0 * M_PI,
721 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
722 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
723 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
724 pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
725 };
726
727 struct qreg x = ntq_shrink_sincos_input_range(c, src);
728 struct qreg x2 = qir_FMUL(c, x, x);
729 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
730 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
731 x = qir_FMUL(c, x, x2);
732 sum = qir_FADD(c,
733 sum,
734 qir_FMUL(c,
735 x,
736 qir_uniform_f(c, coeff[i])));
737 }
738 return sum;
739 }
740
741 static struct qreg
742 ntq_fcos(struct vc4_compile *c, struct qreg src)
743 {
744 float coeff[] = {
745 1.0f,
746 -pow(2.0 * M_PI, 2) / (2 * 1),
747 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
748 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
749 pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
750 -pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
751 };
752
753 struct qreg x_frac = ntq_shrink_sincos_input_range(c, src);
754 struct qreg sum = qir_uniform_f(c, coeff[0]);
755 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
756 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
757 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
758 if (i != 1)
759 x = qir_FMUL(c, x, x2);
760
761 sum = qir_FADD(c, qir_FMUL(c,
762 x,
763 qir_uniform_f(c, coeff[i])),
764 sum);
765 }
766 return sum;
767 }
768
769 static struct qreg
770 ntq_fsign(struct vc4_compile *c, struct qreg src)
771 {
772 struct qreg t = qir_get_temp(c);
773
774 qir_SF(c, src);
775 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
776 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
777 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
778 return qir_MOV(c, t);
779 }
780
781 static void
782 emit_vertex_input(struct vc4_compile *c, int attr)
783 {
784 enum pipe_format format = c->vs_key->attr_formats[attr];
785 uint32_t attr_size = util_format_get_blocksize(format);
786
787 c->vattr_sizes[attr] = align(attr_size, 4);
788 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
789 c->inputs[attr * 4 + i] =
790 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
791 c->num_inputs++;
792 }
793 }
794
795 static void
796 emit_fragcoord_input(struct vc4_compile *c, int attr)
797 {
798 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
799 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
800 c->inputs[attr * 4 + 2] =
801 qir_FMUL(c,
802 qir_ITOF(c, qir_FRAG_Z(c)),
803 qir_uniform_f(c, 1.0 / 0xffffff));
804 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
805 }
806
807 static struct qreg
808 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
809 uint8_t swizzle)
810 {
811 uint32_t i = c->num_input_slots++;
812 struct qreg vary = {
813 QFILE_VARY,
814 i
815 };
816
817 if (c->num_input_slots >= c->input_slots_array_size) {
818 c->input_slots_array_size =
819 MAX2(4, c->input_slots_array_size * 2);
820
821 c->input_slots = reralloc(c, c->input_slots,
822 struct vc4_varying_slot,
823 c->input_slots_array_size);
824 }
825
826 c->input_slots[i].slot = slot;
827 c->input_slots[i].swizzle = swizzle;
828
829 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
830 }
831
832 static void
833 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
834 {
835 for (int i = 0; i < 4; i++) {
836 c->inputs[attr * 4 + i] =
837 emit_fragment_varying(c, slot, i);
838 c->num_inputs++;
839 }
840 }
841
842 static void
843 add_output(struct vc4_compile *c,
844 uint32_t decl_offset,
845 uint8_t slot,
846 uint8_t swizzle)
847 {
848 uint32_t old_array_size = c->outputs_array_size;
849 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
850 decl_offset + 1);
851
852 if (old_array_size != c->outputs_array_size) {
853 c->output_slots = reralloc(c,
854 c->output_slots,
855 struct vc4_varying_slot,
856 c->outputs_array_size);
857 }
858
859 c->output_slots[decl_offset].slot = slot;
860 c->output_slots[decl_offset].swizzle = swizzle;
861 }
862
863 static void
864 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
865 {
866 unsigned array_id = c->num_uniform_ranges++;
867 if (array_id >= c->ubo_ranges_array_size) {
868 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
869 array_id + 1);
870 c->ubo_ranges = reralloc(c, c->ubo_ranges,
871 struct vc4_compiler_ubo_range,
872 c->ubo_ranges_array_size);
873 }
874
875 c->ubo_ranges[array_id].dst_offset = 0;
876 c->ubo_ranges[array_id].src_offset = start;
877 c->ubo_ranges[array_id].size = size;
878 c->ubo_ranges[array_id].used = false;
879 }
880
881 static bool
882 ntq_src_is_only_ssa_def_user(nir_src *src)
883 {
884 if (!src->is_ssa)
885 return false;
886
887 if (!list_empty(&src->ssa->if_uses))
888 return false;
889
890 return (src->ssa->uses.next == &src->use_link &&
891 src->ssa->uses.next->next == &src->ssa->uses);
892 }
893
894 /**
895 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
896 * bit set.
897 *
898 * However, as an optimization, it tries to find the instructions generating
899 * the sources to be packed and just emit the pack flag there, if possible.
900 */
901 static void
902 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
903 {
904 struct qreg result = qir_get_temp(c);
905 struct nir_alu_instr *vec4 = NULL;
906
907 /* If packing from a vec4 op (as expected), identify it so that we can
908 * peek back at what generated its sources.
909 */
910 if (instr->src[0].src.is_ssa &&
911 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
912 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
913 nir_op_vec4) {
914 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
915 }
916
917 /* If the pack is replicating the same channel 4 times, use the 8888
918 * pack flag. This is common for blending using the alpha
919 * channel.
920 */
921 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
922 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
923 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
924 struct qreg rep = ntq_get_src(c,
925 instr->src[0].src,
926 instr->src[0].swizzle[0]);
927 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
928 return;
929 }
930
931 for (int i = 0; i < 4; i++) {
932 int swiz = instr->src[0].swizzle[i];
933 struct qreg src;
934 if (vec4) {
935 src = ntq_get_src(c, vec4->src[swiz].src,
936 vec4->src[swiz].swizzle[0]);
937 } else {
938 src = ntq_get_src(c, instr->src[0].src, swiz);
939 }
940
941 if (vec4 &&
942 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
943 src.file == QFILE_TEMP &&
944 c->defs[src.index] &&
945 qir_is_mul(c->defs[src.index]) &&
946 !c->defs[src.index]->dst.pack) {
947 struct qinst *rewrite = c->defs[src.index];
948 c->defs[src.index] = NULL;
949 rewrite->dst = result;
950 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
951 continue;
952 }
953
954 qir_PACK_8_F(c, result, src, i);
955 }
956
957 ntq_store_dest(c, &instr->dest.dest, 0, qir_MOV(c, result));
958 }
959
960 /** Handles sign-extended bitfield extracts for 16 bits. */
961 static struct qreg
962 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
963 struct qreg bits)
964 {
965 assert(bits.file == QFILE_UNIF &&
966 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
967 c->uniform_data[bits.index] == 16);
968
969 assert(offset.file == QFILE_UNIF &&
970 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
971 int offset_bit = c->uniform_data[offset.index];
972 assert(offset_bit % 16 == 0);
973
974 return qir_UNPACK_16_I(c, base, offset_bit / 16);
975 }
976
977 /** Handles unsigned bitfield extracts for 8 bits. */
978 static struct qreg
979 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
980 struct qreg bits)
981 {
982 assert(bits.file == QFILE_UNIF &&
983 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
984 c->uniform_data[bits.index] == 8);
985
986 assert(offset.file == QFILE_UNIF &&
987 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
988 int offset_bit = c->uniform_data[offset.index];
989 assert(offset_bit % 8 == 0);
990
991 return qir_UNPACK_8_I(c, base, offset_bit / 8);
992 }
993
994 /**
995 * If compare_instr is a valid comparison instruction, emits the
996 * compare_instr's comparison and returns the sel_instr's return value based
997 * on the compare_instr's result.
998 */
999 static bool
1000 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
1001 nir_alu_instr *compare_instr,
1002 nir_alu_instr *sel_instr)
1003 {
1004 enum qpu_cond cond;
1005
1006 switch (compare_instr->op) {
1007 case nir_op_feq32:
1008 case nir_op_ieq32:
1009 case nir_op_seq:
1010 cond = QPU_COND_ZS;
1011 break;
1012 case nir_op_fne32:
1013 case nir_op_ine32:
1014 case nir_op_sne:
1015 cond = QPU_COND_ZC;
1016 break;
1017 case nir_op_fge32:
1018 case nir_op_ige32:
1019 case nir_op_uge32:
1020 case nir_op_sge:
1021 cond = QPU_COND_NC;
1022 break;
1023 case nir_op_flt32:
1024 case nir_op_ilt32:
1025 case nir_op_slt:
1026 cond = QPU_COND_NS;
1027 break;
1028 default:
1029 return false;
1030 }
1031
1032 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
1033 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
1034
1035 unsigned unsized_type =
1036 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
1037 if (unsized_type == nir_type_float)
1038 qir_SF(c, qir_FSUB(c, src0, src1));
1039 else
1040 qir_SF(c, qir_SUB(c, src0, src1));
1041
1042 switch (sel_instr->op) {
1043 case nir_op_seq:
1044 case nir_op_sne:
1045 case nir_op_sge:
1046 case nir_op_slt:
1047 *dest = qir_SEL(c, cond,
1048 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
1049 break;
1050
1051 case nir_op_b32csel:
1052 *dest = qir_SEL(c, cond,
1053 ntq_get_alu_src(c, sel_instr, 1),
1054 ntq_get_alu_src(c, sel_instr, 2));
1055 break;
1056
1057 default:
1058 *dest = qir_SEL(c, cond,
1059 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
1060 break;
1061 }
1062
1063 /* Make the temporary for nir_store_dest(). */
1064 *dest = qir_MOV(c, *dest);
1065
1066 return true;
1067 }
1068
1069 /**
1070 * Attempts to fold a comparison generating a boolean result into the
1071 * condition code for selecting between two values, instead of comparing the
1072 * boolean result against 0 to generate the condition code.
1073 */
1074 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
1075 struct qreg *src)
1076 {
1077 if (!instr->src[0].src.is_ssa)
1078 goto out;
1079 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
1080 goto out;
1081 nir_alu_instr *compare =
1082 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
1083 if (!compare)
1084 goto out;
1085
1086 struct qreg dest;
1087 if (ntq_emit_comparison(c, &dest, compare, instr))
1088 return dest;
1089
1090 out:
1091 qir_SF(c, src[0]);
1092 return qir_MOV(c, qir_SEL(c, QPU_COND_NS, src[1], src[2]));
1093 }
1094
1095 static struct qreg
1096 ntq_fddx(struct vc4_compile *c, struct qreg src)
1097 {
1098 /* Make sure that we have a bare temp to use for MUL rotation, so it
1099 * can be allocated to an accumulator.
1100 */
1101 if (src.pack || src.file != QFILE_TEMP)
1102 src = qir_MOV(c, src);
1103
1104 struct qreg from_left = qir_ROT_MUL(c, src, 1);
1105 struct qreg from_right = qir_ROT_MUL(c, src, 15);
1106
1107 /* Distinguish left/right pixels of the quad. */
1108 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
1109 qir_uniform_ui(c, 1)));
1110
1111 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1112 qir_FSUB(c, from_right, src),
1113 qir_FSUB(c, src, from_left)));
1114 }
1115
1116 static struct qreg
1117 ntq_fddy(struct vc4_compile *c, struct qreg src)
1118 {
1119 if (src.pack || src.file != QFILE_TEMP)
1120 src = qir_MOV(c, src);
1121
1122 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
1123 struct qreg from_top = qir_ROT_MUL(c, src, 14);
1124
1125 /* Distinguish top/bottom pixels of the quad. */
1126 qir_SF(c, qir_AND(c,
1127 qir_reg(QFILE_QPU_ELEMENT, 0),
1128 qir_uniform_ui(c, 2)));
1129
1130 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1131 qir_FSUB(c, from_top, src),
1132 qir_FSUB(c, src, from_bottom)));
1133 }
1134
1135 static void
1136 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
1137 {
1138 /* This should always be lowered to ALU operations for VC4. */
1139 assert(!instr->dest.saturate);
1140
1141 /* Vectors are special in that they have non-scalarized writemasks,
1142 * and just take the first swizzle channel for each argument in order
1143 * into each writemask channel.
1144 */
1145 if (instr->op == nir_op_vec2 ||
1146 instr->op == nir_op_vec3 ||
1147 instr->op == nir_op_vec4) {
1148 struct qreg srcs[4];
1149 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1150 srcs[i] = ntq_get_src(c, instr->src[i].src,
1151 instr->src[i].swizzle[0]);
1152 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1153 ntq_store_dest(c, &instr->dest.dest, i,
1154 qir_MOV(c, srcs[i]));
1155 return;
1156 }
1157
1158 if (instr->op == nir_op_pack_unorm_4x8) {
1159 ntq_emit_pack_unorm_4x8(c, instr);
1160 return;
1161 }
1162
1163 if (instr->op == nir_op_unpack_unorm_4x8) {
1164 struct qreg src = ntq_get_src(c, instr->src[0].src,
1165 instr->src[0].swizzle[0]);
1166 for (int i = 0; i < 4; i++) {
1167 if (instr->dest.write_mask & (1 << i))
1168 ntq_store_dest(c, &instr->dest.dest, i,
1169 qir_UNPACK_8_F(c, src, i));
1170 }
1171 return;
1172 }
1173
1174 /* General case: We can just grab the one used channel per src. */
1175 struct qreg src[nir_op_infos[instr->op].num_inputs];
1176 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1177 src[i] = ntq_get_alu_src(c, instr, i);
1178 }
1179
1180 struct qreg result;
1181
1182 switch (instr->op) {
1183 case nir_op_fmov:
1184 case nir_op_imov:
1185 result = qir_MOV(c, src[0]);
1186 break;
1187 case nir_op_fmul:
1188 result = qir_FMUL(c, src[0], src[1]);
1189 break;
1190 case nir_op_fadd:
1191 result = qir_FADD(c, src[0], src[1]);
1192 break;
1193 case nir_op_fsub:
1194 result = qir_FSUB(c, src[0], src[1]);
1195 break;
1196 case nir_op_fmin:
1197 result = qir_FMIN(c, src[0], src[1]);
1198 break;
1199 case nir_op_fmax:
1200 result = qir_FMAX(c, src[0], src[1]);
1201 break;
1202
1203 case nir_op_f2i32:
1204 case nir_op_f2u32:
1205 result = qir_FTOI(c, src[0]);
1206 break;
1207 case nir_op_i2f32:
1208 case nir_op_u2f32:
1209 result = qir_ITOF(c, src[0]);
1210 break;
1211 case nir_op_b2f32:
1212 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1213 break;
1214 case nir_op_b2i32:
1215 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1216 break;
1217 case nir_op_i2b32:
1218 case nir_op_f2b32:
1219 qir_SF(c, src[0]);
1220 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC,
1221 qir_uniform_ui(c, ~0),
1222 qir_uniform_ui(c, 0)));
1223 break;
1224
1225 case nir_op_iadd:
1226 result = qir_ADD(c, src[0], src[1]);
1227 break;
1228 case nir_op_ushr:
1229 result = qir_SHR(c, src[0], src[1]);
1230 break;
1231 case nir_op_isub:
1232 result = qir_SUB(c, src[0], src[1]);
1233 break;
1234 case nir_op_ishr:
1235 result = qir_ASR(c, src[0], src[1]);
1236 break;
1237 case nir_op_ishl:
1238 result = qir_SHL(c, src[0], src[1]);
1239 break;
1240 case nir_op_imin:
1241 result = qir_MIN(c, src[0], src[1]);
1242 break;
1243 case nir_op_imax:
1244 result = qir_MAX(c, src[0], src[1]);
1245 break;
1246 case nir_op_iand:
1247 result = qir_AND(c, src[0], src[1]);
1248 break;
1249 case nir_op_ior:
1250 result = qir_OR(c, src[0], src[1]);
1251 break;
1252 case nir_op_ixor:
1253 result = qir_XOR(c, src[0], src[1]);
1254 break;
1255 case nir_op_inot:
1256 result = qir_NOT(c, src[0]);
1257 break;
1258
1259 case nir_op_imul:
1260 result = ntq_umul(c, src[0], src[1]);
1261 break;
1262
1263 case nir_op_seq:
1264 case nir_op_sne:
1265 case nir_op_sge:
1266 case nir_op_slt:
1267 case nir_op_feq32:
1268 case nir_op_fne32:
1269 case nir_op_fge32:
1270 case nir_op_flt32:
1271 case nir_op_ieq32:
1272 case nir_op_ine32:
1273 case nir_op_ige32:
1274 case nir_op_uge32:
1275 case nir_op_ilt32:
1276 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1277 fprintf(stderr, "Bad comparison instruction\n");
1278 }
1279 break;
1280
1281 case nir_op_b32csel:
1282 result = ntq_emit_bcsel(c, instr, src);
1283 break;
1284 case nir_op_fcsel:
1285 qir_SF(c, src[0]);
1286 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC, src[1], src[2]));
1287 break;
1288
1289 case nir_op_frcp:
1290 result = ntq_rcp(c, src[0]);
1291 break;
1292 case nir_op_frsq:
1293 result = ntq_rsq(c, src[0]);
1294 break;
1295 case nir_op_fexp2:
1296 result = qir_EXP2(c, src[0]);
1297 break;
1298 case nir_op_flog2:
1299 result = qir_LOG2(c, src[0]);
1300 break;
1301
1302 case nir_op_ftrunc:
1303 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1304 break;
1305 case nir_op_fceil:
1306 result = ntq_fceil(c, src[0]);
1307 break;
1308 case nir_op_ffract:
1309 result = ntq_ffract(c, src[0]);
1310 break;
1311 case nir_op_ffloor:
1312 result = ntq_ffloor(c, src[0]);
1313 break;
1314
1315 case nir_op_fsin:
1316 result = ntq_fsin(c, src[0]);
1317 break;
1318 case nir_op_fcos:
1319 result = ntq_fcos(c, src[0]);
1320 break;
1321
1322 case nir_op_fsign:
1323 result = ntq_fsign(c, src[0]);
1324 break;
1325
1326 case nir_op_fabs:
1327 result = qir_FMAXABS(c, src[0], src[0]);
1328 break;
1329 case nir_op_iabs:
1330 result = qir_MAX(c, src[0],
1331 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1332 break;
1333
1334 case nir_op_ibitfield_extract:
1335 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1336 break;
1337
1338 case nir_op_ubitfield_extract:
1339 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1340 break;
1341
1342 case nir_op_usadd_4x8:
1343 result = qir_V8ADDS(c, src[0], src[1]);
1344 break;
1345
1346 case nir_op_ussub_4x8:
1347 result = qir_V8SUBS(c, src[0], src[1]);
1348 break;
1349
1350 case nir_op_umin_4x8:
1351 result = qir_V8MIN(c, src[0], src[1]);
1352 break;
1353
1354 case nir_op_umax_4x8:
1355 result = qir_V8MAX(c, src[0], src[1]);
1356 break;
1357
1358 case nir_op_umul_unorm_4x8:
1359 result = qir_V8MULD(c, src[0], src[1]);
1360 break;
1361
1362 case nir_op_fddx:
1363 case nir_op_fddx_coarse:
1364 case nir_op_fddx_fine:
1365 result = ntq_fddx(c, src[0]);
1366 break;
1367
1368 case nir_op_fddy:
1369 case nir_op_fddy_coarse:
1370 case nir_op_fddy_fine:
1371 result = ntq_fddy(c, src[0]);
1372 break;
1373
1374 default:
1375 fprintf(stderr, "unknown NIR ALU inst: ");
1376 nir_print_instr(&instr->instr, stderr);
1377 fprintf(stderr, "\n");
1378 abort();
1379 }
1380
1381 /* We have a scalar result, so the instruction should only have a
1382 * single channel written to.
1383 */
1384 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1385 ntq_store_dest(c, &instr->dest.dest,
1386 ffs(instr->dest.write_mask) - 1, result);
1387 }
1388
1389 static void
1390 emit_frag_end(struct vc4_compile *c)
1391 {
1392 struct qreg color;
1393 if (c->output_color_index != -1) {
1394 color = c->outputs[c->output_color_index];
1395 } else {
1396 color = qir_uniform_ui(c, 0);
1397 }
1398
1399 uint32_t discard_cond = QPU_COND_ALWAYS;
1400 if (c->s->info.fs.uses_discard) {
1401 qir_SF(c, c->discard);
1402 discard_cond = QPU_COND_ZS;
1403 }
1404
1405 if (c->fs_key->stencil_enabled) {
1406 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1407 qir_uniform(c, QUNIFORM_STENCIL, 0));
1408 if (c->fs_key->stencil_twoside) {
1409 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1410 qir_uniform(c, QUNIFORM_STENCIL, 1));
1411 }
1412 if (c->fs_key->stencil_full_writemasks) {
1413 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1414 qir_uniform(c, QUNIFORM_STENCIL, 2));
1415 }
1416 }
1417
1418 if (c->output_sample_mask_index != -1) {
1419 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1420 }
1421
1422 if (c->fs_key->depth_enabled) {
1423 if (c->output_position_index != -1) {
1424 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1425 qir_FMUL(c,
1426 c->outputs[c->output_position_index],
1427 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1428 } else {
1429 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1430 qir_FRAG_Z(c))->cond = discard_cond;
1431 }
1432 }
1433
1434 if (!c->msaa_per_sample_output) {
1435 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1436 color)->cond = discard_cond;
1437 } else {
1438 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1439 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1440 c->sample_colors[i])->cond = discard_cond;
1441 }
1442 }
1443 }
1444
1445 static void
1446 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1447 {
1448 struct qreg packed = qir_get_temp(c);
1449
1450 for (int i = 0; i < 2; i++) {
1451 struct qreg scale =
1452 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1453
1454 struct qreg packed_chan = packed;
1455 packed_chan.pack = QPU_PACK_A_16A + i;
1456
1457 qir_FTOI_dest(c, packed_chan,
1458 qir_FMUL(c,
1459 qir_FMUL(c,
1460 c->outputs[c->output_position_index + i],
1461 scale),
1462 rcp_w));
1463 }
1464
1465 qir_VPM_WRITE(c, packed);
1466 }
1467
1468 static void
1469 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1470 {
1471 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1472 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1473
1474 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1475 c->outputs[c->output_position_index + 2],
1476 zscale),
1477 rcp_w),
1478 zoffset));
1479 }
1480
1481 static void
1482 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1483 {
1484 qir_VPM_WRITE(c, rcp_w);
1485 }
1486
1487 static void
1488 emit_point_size_write(struct vc4_compile *c)
1489 {
1490 struct qreg point_size;
1491
1492 if (c->output_point_size_index != -1)
1493 point_size = c->outputs[c->output_point_size_index];
1494 else
1495 point_size = qir_uniform_f(c, 1.0);
1496
1497 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1498 * BCM21553).
1499 */
1500 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1501
1502 qir_VPM_WRITE(c, point_size);
1503 }
1504
1505 /**
1506 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1507 *
1508 * The simulator insists that there be at least one vertex attribute, so
1509 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1510 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1511 * to consume it here.
1512 */
1513 static void
1514 emit_stub_vpm_read(struct vc4_compile *c)
1515 {
1516 if (c->num_inputs)
1517 return;
1518
1519 c->vattr_sizes[0] = 4;
1520 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1521 c->num_inputs++;
1522 }
1523
1524 static void
1525 emit_vert_end(struct vc4_compile *c,
1526 struct vc4_varying_slot *fs_inputs,
1527 uint32_t num_fs_inputs)
1528 {
1529 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1530
1531 emit_stub_vpm_read(c);
1532
1533 emit_scaled_viewport_write(c, rcp_w);
1534 emit_zs_write(c, rcp_w);
1535 emit_rcp_wc_write(c, rcp_w);
1536 if (c->vs_key->per_vertex_point_size)
1537 emit_point_size_write(c);
1538
1539 for (int i = 0; i < num_fs_inputs; i++) {
1540 struct vc4_varying_slot *input = &fs_inputs[i];
1541 int j;
1542
1543 for (j = 0; j < c->num_outputs; j++) {
1544 struct vc4_varying_slot *output =
1545 &c->output_slots[j];
1546
1547 if (input->slot == output->slot &&
1548 input->swizzle == output->swizzle) {
1549 qir_VPM_WRITE(c, c->outputs[j]);
1550 break;
1551 }
1552 }
1553 /* Emit padding if we didn't find a declared VS output for
1554 * this FS input.
1555 */
1556 if (j == c->num_outputs)
1557 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1558 }
1559 }
1560
1561 static void
1562 emit_coord_end(struct vc4_compile *c)
1563 {
1564 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1565
1566 emit_stub_vpm_read(c);
1567
1568 for (int i = 0; i < 4; i++)
1569 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1570
1571 emit_scaled_viewport_write(c, rcp_w);
1572 emit_zs_write(c, rcp_w);
1573 emit_rcp_wc_write(c, rcp_w);
1574 if (c->vs_key->per_vertex_point_size)
1575 emit_point_size_write(c);
1576 }
1577
1578 static void
1579 vc4_optimize_nir(struct nir_shader *s)
1580 {
1581 bool progress;
1582
1583 do {
1584 progress = false;
1585
1586 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1587 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1588 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1589 NIR_PASS(progress, s, nir_copy_prop);
1590 NIR_PASS(progress, s, nir_opt_remove_phis);
1591 NIR_PASS(progress, s, nir_opt_dce);
1592 NIR_PASS(progress, s, nir_opt_dead_cf);
1593 NIR_PASS(progress, s, nir_opt_cse);
1594 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1595 NIR_PASS(progress, s, nir_opt_algebraic);
1596 NIR_PASS(progress, s, nir_opt_constant_folding);
1597 NIR_PASS(progress, s, nir_opt_undef);
1598 NIR_PASS(progress, s, nir_opt_loop_unroll,
1599 nir_var_shader_in |
1600 nir_var_shader_out |
1601 nir_var_function_temp);
1602 } while (progress);
1603 }
1604
1605 static int
1606 driver_location_compare(const void *in_a, const void *in_b)
1607 {
1608 const nir_variable *const *a = in_a;
1609 const nir_variable *const *b = in_b;
1610
1611 return (*a)->data.driver_location - (*b)->data.driver_location;
1612 }
1613
1614 static void
1615 ntq_setup_inputs(struct vc4_compile *c)
1616 {
1617 unsigned num_entries = 0;
1618 nir_foreach_variable(var, &c->s->inputs)
1619 num_entries++;
1620
1621 nir_variable *vars[num_entries];
1622
1623 unsigned i = 0;
1624 nir_foreach_variable(var, &c->s->inputs)
1625 vars[i++] = var;
1626
1627 /* Sort the variables so that we emit the input setup in
1628 * driver_location order. This is required for VPM reads, whose data
1629 * is fetched into the VPM in driver_location (TGSI register index)
1630 * order.
1631 */
1632 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1633
1634 for (unsigned i = 0; i < num_entries; i++) {
1635 nir_variable *var = vars[i];
1636 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1637 unsigned loc = var->data.driver_location;
1638
1639 assert(array_len == 1);
1640 (void)array_len;
1641 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1642 (loc + 1) * 4);
1643
1644 if (c->stage == QSTAGE_FRAG) {
1645 if (var->data.location == VARYING_SLOT_POS) {
1646 emit_fragcoord_input(c, loc);
1647 } else if (var->data.location == VARYING_SLOT_PNTC ||
1648 (var->data.location >= VARYING_SLOT_VAR0 &&
1649 (c->fs_key->point_sprite_mask &
1650 (1 << (var->data.location -
1651 VARYING_SLOT_VAR0))))) {
1652 c->inputs[loc * 4 + 0] = c->point_x;
1653 c->inputs[loc * 4 + 1] = c->point_y;
1654 } else {
1655 emit_fragment_input(c, loc, var->data.location);
1656 }
1657 } else {
1658 emit_vertex_input(c, loc);
1659 }
1660 }
1661 }
1662
1663 static void
1664 ntq_setup_outputs(struct vc4_compile *c)
1665 {
1666 nir_foreach_variable(var, &c->s->outputs) {
1667 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1668 unsigned loc = var->data.driver_location * 4;
1669
1670 assert(array_len == 1);
1671 (void)array_len;
1672
1673 for (int i = 0; i < 4; i++)
1674 add_output(c, loc + i, var->data.location, i);
1675
1676 if (c->stage == QSTAGE_FRAG) {
1677 switch (var->data.location) {
1678 case FRAG_RESULT_COLOR:
1679 case FRAG_RESULT_DATA0:
1680 c->output_color_index = loc;
1681 break;
1682 case FRAG_RESULT_DEPTH:
1683 c->output_position_index = loc;
1684 break;
1685 case FRAG_RESULT_SAMPLE_MASK:
1686 c->output_sample_mask_index = loc;
1687 break;
1688 }
1689 } else {
1690 switch (var->data.location) {
1691 case VARYING_SLOT_POS:
1692 c->output_position_index = loc;
1693 break;
1694 case VARYING_SLOT_PSIZ:
1695 c->output_point_size_index = loc;
1696 break;
1697 }
1698 }
1699 }
1700 }
1701
1702 static void
1703 ntq_setup_uniforms(struct vc4_compile *c)
1704 {
1705 nir_foreach_variable(var, &c->s->uniforms) {
1706 uint32_t vec4_count = uniforms_type_size(var->type);
1707 unsigned vec4_size = 4 * sizeof(float);
1708
1709 declare_uniform_range(c, var->data.driver_location * vec4_size,
1710 vec4_count * vec4_size);
1711
1712 }
1713 }
1714
1715 /**
1716 * Sets up the mapping from nir_register to struct qreg *.
1717 *
1718 * Each nir_register gets a struct qreg per 32-bit component being stored.
1719 */
1720 static void
1721 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1722 {
1723 foreach_list_typed(nir_register, nir_reg, node, list) {
1724 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1725 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1726 array_len *
1727 nir_reg->num_components);
1728
1729 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1730
1731 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1732 qregs[i] = qir_get_temp(c);
1733 }
1734 }
1735
1736 static void
1737 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1738 {
1739 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1740 for (int i = 0; i < instr->def.num_components; i++)
1741 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1742
1743 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1744 }
1745
1746 static void
1747 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1748 {
1749 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1750
1751 /* QIR needs there to be *some* value, so pick 0 (same as for
1752 * ntq_setup_registers().
1753 */
1754 for (int i = 0; i < instr->def.num_components; i++)
1755 qregs[i] = qir_uniform_ui(c, 0);
1756 }
1757
1758 static void
1759 ntq_emit_color_read(struct vc4_compile *c, nir_intrinsic_instr *instr)
1760 {
1761 assert(nir_src_as_const_value(instr->src[0])->u32[0] == 0);
1762
1763 /* Reads of the per-sample color need to be done in
1764 * order.
1765 */
1766 int sample_index = (nir_intrinsic_base(instr) -
1767 VC4_NIR_TLB_COLOR_READ_INPUT);
1768 for (int i = 0; i <= sample_index; i++) {
1769 if (c->color_reads[i].file == QFILE_NULL) {
1770 c->color_reads[i] =
1771 qir_TLB_COLOR_READ(c);
1772 }
1773 }
1774 ntq_store_dest(c, &instr->dest, 0,
1775 qir_MOV(c, c->color_reads[sample_index]));
1776 }
1777
1778 static void
1779 ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
1780 {
1781 assert(instr->num_components == 1);
1782
1783 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
1784 assert(const_offset && "vc4 doesn't support indirect inputs");
1785
1786 if (c->stage == QSTAGE_FRAG &&
1787 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1788 ntq_emit_color_read(c, instr);
1789 return;
1790 }
1791
1792 uint32_t offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1793 int comp = nir_intrinsic_component(instr);
1794 ntq_store_dest(c, &instr->dest, 0,
1795 qir_MOV(c, c->inputs[offset * 4 + comp]));
1796 }
1797
1798 static void
1799 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1800 {
1801 nir_const_value *const_offset;
1802 unsigned offset;
1803
1804 switch (instr->intrinsic) {
1805 case nir_intrinsic_load_uniform:
1806 assert(instr->num_components == 1);
1807 const_offset = nir_src_as_const_value(instr->src[0]);
1808 if (const_offset) {
1809 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1810 assert(offset % 4 == 0);
1811 /* We need dwords */
1812 offset = offset / 4;
1813 ntq_store_dest(c, &instr->dest, 0,
1814 qir_uniform(c, QUNIFORM_UNIFORM,
1815 offset));
1816 } else {
1817 ntq_store_dest(c, &instr->dest, 0,
1818 indirect_uniform_load(c, instr));
1819 }
1820 break;
1821
1822 case nir_intrinsic_load_ubo:
1823 assert(instr->num_components == 1);
1824 ntq_store_dest(c, &instr->dest, 0, vc4_ubo_load(c, instr));
1825 break;
1826
1827 case nir_intrinsic_load_user_clip_plane:
1828 for (int i = 0; i < instr->num_components; i++) {
1829 ntq_store_dest(c, &instr->dest, i,
1830 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1831 nir_intrinsic_ucp_id(instr) *
1832 4 + i));
1833 }
1834 break;
1835
1836 case nir_intrinsic_load_blend_const_color_r_float:
1837 case nir_intrinsic_load_blend_const_color_g_float:
1838 case nir_intrinsic_load_blend_const_color_b_float:
1839 case nir_intrinsic_load_blend_const_color_a_float:
1840 ntq_store_dest(c, &instr->dest, 0,
1841 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1842 (instr->intrinsic -
1843 nir_intrinsic_load_blend_const_color_r_float),
1844 0));
1845 break;
1846
1847 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1848 ntq_store_dest(c, &instr->dest, 0,
1849 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1850 0));
1851 break;
1852
1853 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1854 ntq_store_dest(c, &instr->dest, 0,
1855 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1856 0));
1857 break;
1858
1859 case nir_intrinsic_load_alpha_ref_float:
1860 ntq_store_dest(c, &instr->dest, 0,
1861 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1862 break;
1863
1864 case nir_intrinsic_load_sample_mask_in:
1865 ntq_store_dest(c, &instr->dest, 0,
1866 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1867 break;
1868
1869 case nir_intrinsic_load_front_face:
1870 /* The register contains 0 (front) or 1 (back), and we need to
1871 * turn it into a NIR bool where true means front.
1872 */
1873 ntq_store_dest(c, &instr->dest, 0,
1874 qir_ADD(c,
1875 qir_uniform_ui(c, -1),
1876 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1877 break;
1878
1879 case nir_intrinsic_load_input:
1880 ntq_emit_load_input(c, instr);
1881 break;
1882
1883 case nir_intrinsic_store_output:
1884 const_offset = nir_src_as_const_value(instr->src[1]);
1885 assert(const_offset && "vc4 doesn't support indirect outputs");
1886 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1887
1888 /* MSAA color outputs are the only case where we have an
1889 * output that's not lowered to being a store of a single 32
1890 * bit value.
1891 */
1892 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1893 assert(offset == c->output_color_index);
1894 for (int i = 0; i < 4; i++) {
1895 c->sample_colors[i] =
1896 qir_MOV(c, ntq_get_src(c, instr->src[0],
1897 i));
1898 }
1899 } else {
1900 offset = offset * 4 + nir_intrinsic_component(instr);
1901 assert(instr->num_components == 1);
1902 c->outputs[offset] =
1903 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1904 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1905 }
1906 break;
1907
1908 case nir_intrinsic_discard:
1909 if (c->execute.file != QFILE_NULL) {
1910 qir_SF(c, c->execute);
1911 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1912 qir_uniform_ui(c, ~0));
1913 } else {
1914 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1915 }
1916 break;
1917
1918 case nir_intrinsic_discard_if: {
1919 /* true (~0) if we're discarding */
1920 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1921
1922 if (c->execute.file != QFILE_NULL) {
1923 /* execute == 0 means the channel is active. Invert
1924 * the condition so that we can use zero as "executing
1925 * and discarding."
1926 */
1927 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1928 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1929 } else {
1930 qir_OR_dest(c, c->discard, c->discard,
1931 ntq_get_src(c, instr->src[0], 0));
1932 }
1933
1934 break;
1935 }
1936
1937 default:
1938 fprintf(stderr, "Unknown intrinsic: ");
1939 nir_print_instr(&instr->instr, stderr);
1940 fprintf(stderr, "\n");
1941 break;
1942 }
1943 }
1944
1945 /* Clears (activates) the execute flags for any channels whose jump target
1946 * matches this block.
1947 */
1948 static void
1949 ntq_activate_execute_for_block(struct vc4_compile *c)
1950 {
1951 qir_SF(c, qir_SUB(c,
1952 c->execute,
1953 qir_uniform_ui(c, c->cur_block->index)));
1954 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1955 }
1956
1957 static void
1958 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1959 {
1960 if (!c->vc4->screen->has_control_flow) {
1961 fprintf(stderr,
1962 "IF statement support requires updated kernel.\n");
1963 return;
1964 }
1965
1966 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1967 bool empty_else_block =
1968 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1969 exec_list_is_empty(&nir_else_block->instr_list));
1970
1971 struct qblock *then_block = qir_new_block(c);
1972 struct qblock *after_block = qir_new_block(c);
1973 struct qblock *else_block;
1974 if (empty_else_block)
1975 else_block = after_block;
1976 else
1977 else_block = qir_new_block(c);
1978
1979 bool was_top_level = false;
1980 if (c->execute.file == QFILE_NULL) {
1981 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1982 was_top_level = true;
1983 }
1984
1985 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1986 * 0) channels, and then update execute flags for those to point to
1987 * the ELSE block.
1988 */
1989 qir_SF(c, qir_OR(c,
1990 c->execute,
1991 ntq_get_src(c, if_stmt->condition, 0)));
1992 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1993 qir_uniform_ui(c, else_block->index));
1994
1995 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1996 * through.
1997 */
1998 qir_SF(c, c->execute);
1999 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
2000 qir_link_blocks(c->cur_block, else_block);
2001 qir_link_blocks(c->cur_block, then_block);
2002
2003 /* Process the THEN block. */
2004 qir_set_emit_block(c, then_block);
2005 ntq_emit_cf_list(c, &if_stmt->then_list);
2006
2007 if (!empty_else_block) {
2008 /* Handle the end of the THEN block. First, all currently
2009 * active channels update their execute flags to point to
2010 * ENDIF
2011 */
2012 qir_SF(c, c->execute);
2013 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
2014 qir_uniform_ui(c, after_block->index));
2015
2016 /* If everything points at ENDIF, then jump there immediately. */
2017 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
2018 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
2019 qir_link_blocks(c->cur_block, after_block);
2020 qir_link_blocks(c->cur_block, else_block);
2021
2022 qir_set_emit_block(c, else_block);
2023 ntq_activate_execute_for_block(c);
2024 ntq_emit_cf_list(c, &if_stmt->else_list);
2025 }
2026
2027 qir_link_blocks(c->cur_block, after_block);
2028
2029 qir_set_emit_block(c, after_block);
2030 if (was_top_level) {
2031 c->execute = c->undef;
2032 c->last_top_block = c->cur_block;
2033 } else {
2034 ntq_activate_execute_for_block(c);
2035 }
2036 }
2037
2038 static void
2039 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
2040 {
2041 struct qblock *jump_block;
2042 switch (jump->type) {
2043 case nir_jump_break:
2044 jump_block = c->loop_break_block;
2045 break;
2046 case nir_jump_continue:
2047 jump_block = c->loop_cont_block;
2048 break;
2049 default:
2050 unreachable("Unsupported jump type\n");
2051 }
2052
2053 qir_SF(c, c->execute);
2054 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
2055 qir_uniform_ui(c, jump_block->index));
2056
2057 /* Jump to the destination block if everyone has taken the jump. */
2058 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, jump_block->index)));
2059 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
2060 struct qblock *new_block = qir_new_block(c);
2061 qir_link_blocks(c->cur_block, jump_block);
2062 qir_link_blocks(c->cur_block, new_block);
2063 qir_set_emit_block(c, new_block);
2064 }
2065
2066 static void
2067 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
2068 {
2069 switch (instr->type) {
2070 case nir_instr_type_alu:
2071 ntq_emit_alu(c, nir_instr_as_alu(instr));
2072 break;
2073
2074 case nir_instr_type_intrinsic:
2075 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2076 break;
2077
2078 case nir_instr_type_load_const:
2079 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2080 break;
2081
2082 case nir_instr_type_ssa_undef:
2083 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2084 break;
2085
2086 case nir_instr_type_tex:
2087 ntq_emit_tex(c, nir_instr_as_tex(instr));
2088 break;
2089
2090 case nir_instr_type_jump:
2091 ntq_emit_jump(c, nir_instr_as_jump(instr));
2092 break;
2093
2094 default:
2095 fprintf(stderr, "Unknown NIR instr type: ");
2096 nir_print_instr(instr, stderr);
2097 fprintf(stderr, "\n");
2098 abort();
2099 }
2100 }
2101
2102 static void
2103 ntq_emit_block(struct vc4_compile *c, nir_block *block)
2104 {
2105 nir_foreach_instr(instr, block) {
2106 ntq_emit_instr(c, instr);
2107 }
2108 }
2109
2110 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
2111
2112 static void
2113 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
2114 {
2115 if (!c->vc4->screen->has_control_flow) {
2116 fprintf(stderr,
2117 "loop support requires updated kernel.\n");
2118 ntq_emit_cf_list(c, &loop->body);
2119 return;
2120 }
2121
2122 bool was_top_level = false;
2123 if (c->execute.file == QFILE_NULL) {
2124 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
2125 was_top_level = true;
2126 }
2127
2128 struct qblock *save_loop_cont_block = c->loop_cont_block;
2129 struct qblock *save_loop_break_block = c->loop_break_block;
2130
2131 c->loop_cont_block = qir_new_block(c);
2132 c->loop_break_block = qir_new_block(c);
2133
2134 qir_link_blocks(c->cur_block, c->loop_cont_block);
2135 qir_set_emit_block(c, c->loop_cont_block);
2136 ntq_activate_execute_for_block(c);
2137
2138 ntq_emit_cf_list(c, &loop->body);
2139
2140 /* If anything had explicitly continued, or is here at the end of the
2141 * loop, then we need to loop again. SF updates are masked by the
2142 * instruction's condition, so we can do the OR of the two conditions
2143 * within SF.
2144 */
2145 qir_SF(c, c->execute);
2146 struct qinst *cont_check =
2147 qir_SUB_dest(c,
2148 c->undef,
2149 c->execute,
2150 qir_uniform_ui(c, c->loop_cont_block->index));
2151 cont_check->cond = QPU_COND_ZC;
2152 cont_check->sf = true;
2153
2154 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
2155 qir_link_blocks(c->cur_block, c->loop_cont_block);
2156 qir_link_blocks(c->cur_block, c->loop_break_block);
2157
2158 qir_set_emit_block(c, c->loop_break_block);
2159 if (was_top_level) {
2160 c->execute = c->undef;
2161 c->last_top_block = c->cur_block;
2162 } else {
2163 ntq_activate_execute_for_block(c);
2164 }
2165
2166 c->loop_break_block = save_loop_break_block;
2167 c->loop_cont_block = save_loop_cont_block;
2168 }
2169
2170 static void
2171 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
2172 {
2173 fprintf(stderr, "FUNCTIONS not handled.\n");
2174 abort();
2175 }
2176
2177 static void
2178 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
2179 {
2180 foreach_list_typed(nir_cf_node, node, node, list) {
2181 switch (node->type) {
2182 case nir_cf_node_block:
2183 ntq_emit_block(c, nir_cf_node_as_block(node));
2184 break;
2185
2186 case nir_cf_node_if:
2187 ntq_emit_if(c, nir_cf_node_as_if(node));
2188 break;
2189
2190 case nir_cf_node_loop:
2191 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2192 break;
2193
2194 case nir_cf_node_function:
2195 ntq_emit_function(c, nir_cf_node_as_function(node));
2196 break;
2197
2198 default:
2199 fprintf(stderr, "Unknown NIR node type\n");
2200 abort();
2201 }
2202 }
2203 }
2204
2205 static void
2206 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2207 {
2208 ntq_setup_registers(c, &impl->registers);
2209 ntq_emit_cf_list(c, &impl->body);
2210 }
2211
2212 static void
2213 nir_to_qir(struct vc4_compile *c)
2214 {
2215 if (c->stage == QSTAGE_FRAG && c->s->info.fs.uses_discard)
2216 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2217
2218 ntq_setup_inputs(c);
2219 ntq_setup_outputs(c);
2220 ntq_setup_uniforms(c);
2221 ntq_setup_registers(c, &c->s->registers);
2222
2223 /* Find the main function and emit the body. */
2224 nir_foreach_function(function, c->s) {
2225 assert(strcmp(function->name, "main") == 0);
2226 assert(function->impl);
2227 ntq_emit_impl(c, function->impl);
2228 }
2229 }
2230
2231 static const nir_shader_compiler_options nir_options = {
2232 .lower_all_io_to_temps = true,
2233 .lower_extract_byte = true,
2234 .lower_extract_word = true,
2235 .lower_fdiv = true,
2236 .lower_ffma = true,
2237 .lower_flrp32 = true,
2238 .lower_fpow = true,
2239 .lower_fsat = true,
2240 .lower_fsqrt = true,
2241 .lower_ldexp = true,
2242 .lower_negate = true,
2243 .native_integers = true,
2244 .max_unroll_iterations = 32,
2245 };
2246
2247 const void *
2248 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2249 enum pipe_shader_ir ir,
2250 enum pipe_shader_type shader)
2251 {
2252 return &nir_options;
2253 }
2254
2255 static int
2256 count_nir_instrs(nir_shader *nir)
2257 {
2258 int count = 0;
2259 nir_foreach_function(function, nir) {
2260 if (!function->impl)
2261 continue;
2262 nir_foreach_block(block, function->impl) {
2263 nir_foreach_instr(instr, block)
2264 count++;
2265 }
2266 }
2267 return count;
2268 }
2269
2270 static struct vc4_compile *
2271 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2272 struct vc4_key *key, bool fs_threaded)
2273 {
2274 struct vc4_compile *c = qir_compile_init();
2275
2276 c->vc4 = vc4;
2277 c->stage = stage;
2278 c->shader_state = &key->shader_state->base;
2279 c->program_id = key->shader_state->program_id;
2280 c->variant_id =
2281 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2282 c->fs_threaded = fs_threaded;
2283
2284 c->key = key;
2285 switch (stage) {
2286 case QSTAGE_FRAG:
2287 c->fs_key = (struct vc4_fs_key *)key;
2288 if (c->fs_key->is_points) {
2289 c->point_x = emit_fragment_varying(c, ~0, 0);
2290 c->point_y = emit_fragment_varying(c, ~0, 0);
2291 } else if (c->fs_key->is_lines) {
2292 c->line_x = emit_fragment_varying(c, ~0, 0);
2293 }
2294 break;
2295 case QSTAGE_VERT:
2296 c->vs_key = (struct vc4_vs_key *)key;
2297 break;
2298 case QSTAGE_COORD:
2299 c->vs_key = (struct vc4_vs_key *)key;
2300 break;
2301 }
2302
2303 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2304
2305 if (stage == QSTAGE_FRAG) {
2306 if (c->fs_key->alpha_test_func != COMPARE_FUNC_ALWAYS) {
2307 NIR_PASS_V(c->s, nir_lower_alpha_test,
2308 c->fs_key->alpha_test_func,
2309 c->fs_key->sample_alpha_to_one &&
2310 c->fs_key->msaa);
2311 }
2312 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2313 }
2314
2315 struct nir_lower_tex_options tex_options = {
2316 /* We would need to implement txs, but we don't want the
2317 * int/float conversions
2318 */
2319 .lower_rect = false,
2320
2321 .lower_txp = ~0,
2322
2323 /* Apply swizzles to all samplers. */
2324 .swizzle_result = ~0,
2325 };
2326
2327 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2328 * The format swizzling applies before sRGB decode, and
2329 * ARB_texture_swizzle is the last thing before returning the sample.
2330 */
2331 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2332 enum pipe_format format = c->key->tex[i].format;
2333
2334 if (!format)
2335 continue;
2336
2337 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2338
2339 for (int j = 0; j < 4; j++) {
2340 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2341
2342 if (arb_swiz <= 3) {
2343 tex_options.swizzles[i][j] =
2344 format_swizzle[arb_swiz];
2345 } else {
2346 tex_options.swizzles[i][j] = arb_swiz;
2347 }
2348 }
2349
2350 if (util_format_is_srgb(format))
2351 tex_options.lower_srgb |= (1 << i);
2352 }
2353
2354 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2355
2356 if (c->fs_key && c->fs_key->light_twoside)
2357 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2358
2359 if (c->vs_key && c->vs_key->clamp_color)
2360 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2361
2362 if (c->key->ucp_enables) {
2363 if (stage == QSTAGE_FRAG) {
2364 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2365 } else {
2366 NIR_PASS_V(c->s, nir_lower_clip_vs,
2367 c->key->ucp_enables, false);
2368 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2369 nir_var_shader_out);
2370 }
2371 }
2372
2373 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2374 * which only handles a vec4 at a time. Similarly, VS output
2375 * scalarizing must happen after nir_lower_clip_vs.
2376 */
2377 if (c->stage == QSTAGE_FRAG)
2378 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2379 else
2380 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2381
2382 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2383 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2384 NIR_PASS_V(c->s, nir_lower_idiv);
2385
2386 vc4_optimize_nir(c->s);
2387
2388 NIR_PASS_V(c->s, nir_lower_bool_to_int32);
2389
2390 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2391
2392 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2393 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2394 qir_get_stage_name(c->stage),
2395 c->program_id, c->variant_id,
2396 count_nir_instrs(c->s));
2397 }
2398
2399 if (vc4_debug & VC4_DEBUG_NIR) {
2400 fprintf(stderr, "%s prog %d/%d NIR:\n",
2401 qir_get_stage_name(c->stage),
2402 c->program_id, c->variant_id);
2403 nir_print_shader(c->s, stderr);
2404 }
2405
2406 nir_to_qir(c);
2407
2408 switch (stage) {
2409 case QSTAGE_FRAG:
2410 /* FS threading requires that the thread execute
2411 * QPU_SIG_LAST_THREAD_SWITCH exactly once before terminating
2412 * (with no other THRSW afterwards, obviously). If we didn't
2413 * fetch a texture at a top level block, this wouldn't be
2414 * true.
2415 */
2416 if (c->fs_threaded && !c->last_thrsw_at_top_level) {
2417 c->failed = true;
2418 return c;
2419 }
2420
2421 emit_frag_end(c);
2422 break;
2423 case QSTAGE_VERT:
2424 emit_vert_end(c,
2425 c->vs_key->fs_inputs->input_slots,
2426 c->vs_key->fs_inputs->num_inputs);
2427 break;
2428 case QSTAGE_COORD:
2429 emit_coord_end(c);
2430 break;
2431 }
2432
2433 if (vc4_debug & VC4_DEBUG_QIR) {
2434 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2435 qir_get_stage_name(c->stage),
2436 c->program_id, c->variant_id);
2437 qir_dump(c);
2438 fprintf(stderr, "\n");
2439 }
2440
2441 qir_optimize(c);
2442 qir_lower_uniforms(c);
2443
2444 qir_schedule_instructions(c);
2445 qir_emit_uniform_stream_resets(c);
2446
2447 if (vc4_debug & VC4_DEBUG_QIR) {
2448 fprintf(stderr, "%s prog %d/%d QIR:\n",
2449 qir_get_stage_name(c->stage),
2450 c->program_id, c->variant_id);
2451 qir_dump(c);
2452 fprintf(stderr, "\n");
2453 }
2454
2455 qir_reorder_uniforms(c);
2456 vc4_generate_code(vc4, c);
2457
2458 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2459 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2460 qir_get_stage_name(c->stage),
2461 c->program_id, c->variant_id,
2462 c->qpu_inst_count);
2463 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2464 qir_get_stage_name(c->stage),
2465 c->program_id, c->variant_id,
2466 c->num_uniforms);
2467 }
2468
2469 ralloc_free(c->s);
2470
2471 return c;
2472 }
2473
2474 static void *
2475 vc4_shader_state_create(struct pipe_context *pctx,
2476 const struct pipe_shader_state *cso)
2477 {
2478 struct vc4_context *vc4 = vc4_context(pctx);
2479 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2480 if (!so)
2481 return NULL;
2482
2483 so->program_id = vc4->next_uncompiled_program_id++;
2484
2485 nir_shader *s;
2486
2487 if (cso->type == PIPE_SHADER_IR_NIR) {
2488 /* The backend takes ownership of the NIR shader on state
2489 * creation.
2490 */
2491 s = cso->ir.nir;
2492
2493 NIR_PASS_V(s, nir_lower_io, nir_var_uniform,
2494 uniforms_type_size,
2495 (nir_lower_io_options)0);
2496 } else {
2497 assert(cso->type == PIPE_SHADER_IR_TGSI);
2498
2499 if (vc4_debug & VC4_DEBUG_TGSI) {
2500 fprintf(stderr, "prog %d TGSI:\n",
2501 so->program_id);
2502 tgsi_dump(cso->tokens, 0);
2503 fprintf(stderr, "\n");
2504 }
2505 s = tgsi_to_nir(cso->tokens, pctx->screen);
2506 }
2507
2508 NIR_PASS_V(s, nir_lower_io, nir_var_all & ~nir_var_uniform,
2509 type_size,
2510 (nir_lower_io_options)0);
2511
2512 NIR_PASS_V(s, nir_opt_global_to_local);
2513 NIR_PASS_V(s, nir_lower_regs_to_ssa);
2514 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2515
2516 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2517
2518 vc4_optimize_nir(s);
2519
2520 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp);
2521
2522 /* Garbage collect dead instructions */
2523 nir_sweep(s);
2524
2525 so->base.type = PIPE_SHADER_IR_NIR;
2526 so->base.ir.nir = s;
2527
2528 if (vc4_debug & VC4_DEBUG_NIR) {
2529 fprintf(stderr, "%s prog %d NIR:\n",
2530 gl_shader_stage_name(s->info.stage),
2531 so->program_id);
2532 nir_print_shader(s, stderr);
2533 fprintf(stderr, "\n");
2534 }
2535
2536 return so;
2537 }
2538
2539 static void
2540 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2541 struct vc4_compile *c)
2542 {
2543 int count = c->num_uniforms;
2544 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2545
2546 uinfo->count = count;
2547 uinfo->data = ralloc_array(shader, uint32_t, count);
2548 memcpy(uinfo->data, c->uniform_data,
2549 count * sizeof(*uinfo->data));
2550 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2551 memcpy(uinfo->contents, c->uniform_contents,
2552 count * sizeof(*uinfo->contents));
2553 uinfo->num_texture_samples = c->num_texture_samples;
2554
2555 vc4_set_shader_uniform_dirty_flags(shader);
2556 }
2557
2558 static void
2559 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2560 struct vc4_compiled_shader *shader)
2561 {
2562 struct vc4_fs_inputs inputs;
2563
2564 memset(&inputs, 0, sizeof(inputs));
2565 inputs.input_slots = ralloc_array(shader,
2566 struct vc4_varying_slot,
2567 c->num_input_slots);
2568
2569 bool input_live[c->num_input_slots];
2570
2571 memset(input_live, 0, sizeof(input_live));
2572 qir_for_each_inst_inorder(inst, c) {
2573 for (int i = 0; i < qir_get_nsrc(inst); i++) {
2574 if (inst->src[i].file == QFILE_VARY)
2575 input_live[inst->src[i].index] = true;
2576 }
2577 }
2578
2579 for (int i = 0; i < c->num_input_slots; i++) {
2580 struct vc4_varying_slot *slot = &c->input_slots[i];
2581
2582 if (!input_live[i])
2583 continue;
2584
2585 /* Skip non-VS-output inputs. */
2586 if (slot->slot == (uint8_t)~0)
2587 continue;
2588
2589 if (slot->slot == VARYING_SLOT_COL0 ||
2590 slot->slot == VARYING_SLOT_COL1 ||
2591 slot->slot == VARYING_SLOT_BFC0 ||
2592 slot->slot == VARYING_SLOT_BFC1) {
2593 shader->color_inputs |= (1 << inputs.num_inputs);
2594 }
2595
2596 inputs.input_slots[inputs.num_inputs] = *slot;
2597 inputs.num_inputs++;
2598 }
2599 shader->num_inputs = inputs.num_inputs;
2600
2601 /* Add our set of inputs to the set of all inputs seen. This way, we
2602 * can have a single pointer that identifies an FS inputs set,
2603 * allowing VS to avoid recompiling when the FS is recompiled (or a
2604 * new one is bound using separate shader objects) but the inputs
2605 * don't change.
2606 */
2607 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2608 if (entry) {
2609 shader->fs_inputs = entry->key;
2610 ralloc_free(inputs.input_slots);
2611 } else {
2612 struct vc4_fs_inputs *alloc_inputs;
2613
2614 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2615 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2616 ralloc_steal(alloc_inputs, inputs.input_slots);
2617 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2618
2619 shader->fs_inputs = alloc_inputs;
2620 }
2621 }
2622
2623 static struct vc4_compiled_shader *
2624 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2625 struct vc4_key *key)
2626 {
2627 struct hash_table *ht;
2628 uint32_t key_size;
2629 bool try_threading;
2630
2631 if (stage == QSTAGE_FRAG) {
2632 ht = vc4->fs_cache;
2633 key_size = sizeof(struct vc4_fs_key);
2634 try_threading = vc4->screen->has_threaded_fs;
2635 } else {
2636 ht = vc4->vs_cache;
2637 key_size = sizeof(struct vc4_vs_key);
2638 try_threading = false;
2639 }
2640
2641 struct vc4_compiled_shader *shader;
2642 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2643 if (entry)
2644 return entry->data;
2645
2646 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key, try_threading);
2647 /* If the FS failed to compile threaded, fall back to single threaded. */
2648 if (try_threading && c->failed) {
2649 qir_compile_destroy(c);
2650 c = vc4_shader_ntq(vc4, stage, key, false);
2651 }
2652
2653 shader = rzalloc(NULL, struct vc4_compiled_shader);
2654
2655 shader->program_id = vc4->next_compiled_program_id++;
2656 if (stage == QSTAGE_FRAG) {
2657 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2658
2659 /* Note: the temporary clone in c->s has been freed. */
2660 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2661 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2662 shader->disable_early_z = true;
2663 } else {
2664 shader->num_inputs = c->num_inputs;
2665
2666 shader->vattr_offsets[0] = 0;
2667 for (int i = 0; i < 8; i++) {
2668 shader->vattr_offsets[i + 1] =
2669 shader->vattr_offsets[i] + c->vattr_sizes[i];
2670
2671 if (c->vattr_sizes[i])
2672 shader->vattrs_live |= (1 << i);
2673 }
2674 }
2675
2676 shader->failed = c->failed;
2677 if (c->failed) {
2678 shader->failed = true;
2679 } else {
2680 copy_uniform_state_to_shader(shader, c);
2681 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2682 c->qpu_inst_count *
2683 sizeof(uint64_t));
2684 }
2685
2686 shader->fs_threaded = c->fs_threaded;
2687
2688 /* Copy the compiler UBO range state to the compiled shader, dropping
2689 * out arrays that were never referenced by an indirect load.
2690 *
2691 * (Note that QIR dead code elimination of an array access still
2692 * leaves that array alive, though)
2693 */
2694 if (c->num_ubo_ranges) {
2695 shader->num_ubo_ranges = c->num_ubo_ranges;
2696 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2697 c->num_ubo_ranges);
2698 uint32_t j = 0;
2699 for (int i = 0; i < c->num_uniform_ranges; i++) {
2700 struct vc4_compiler_ubo_range *range =
2701 &c->ubo_ranges[i];
2702 if (!range->used)
2703 continue;
2704
2705 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2706 shader->ubo_ranges[j].src_offset = range->src_offset;
2707 shader->ubo_ranges[j].size = range->size;
2708 shader->ubo_size += c->ubo_ranges[i].size;
2709 j++;
2710 }
2711 }
2712 if (shader->ubo_size) {
2713 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2714 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2715 qir_get_stage_name(c->stage),
2716 c->program_id, c->variant_id,
2717 shader->ubo_size / 4);
2718 }
2719 }
2720
2721 if ((vc4_debug & VC4_DEBUG_SHADERDB) && stage == QSTAGE_FRAG) {
2722 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d FS threads\n",
2723 qir_get_stage_name(c->stage),
2724 c->program_id, c->variant_id,
2725 1 + shader->fs_threaded);
2726 }
2727
2728 qir_compile_destroy(c);
2729
2730 struct vc4_key *dup_key;
2731 dup_key = rzalloc_size(shader, key_size); /* TODO: don't use rzalloc */
2732 memcpy(dup_key, key, key_size);
2733 _mesa_hash_table_insert(ht, dup_key, shader);
2734
2735 return shader;
2736 }
2737
2738 static void
2739 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2740 struct vc4_texture_stateobj *texstate)
2741 {
2742 for (int i = 0; i < texstate->num_textures; i++) {
2743 struct pipe_sampler_view *sampler = texstate->textures[i];
2744 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2745 struct pipe_sampler_state *sampler_state =
2746 texstate->samplers[i];
2747
2748 if (!sampler)
2749 continue;
2750
2751 key->tex[i].format = sampler->format;
2752 key->tex[i].swizzle[0] = sampler->swizzle_r;
2753 key->tex[i].swizzle[1] = sampler->swizzle_g;
2754 key->tex[i].swizzle[2] = sampler->swizzle_b;
2755 key->tex[i].swizzle[3] = sampler->swizzle_a;
2756
2757 if (sampler->texture->nr_samples > 1) {
2758 key->tex[i].msaa_width = sampler->texture->width0;
2759 key->tex[i].msaa_height = sampler->texture->height0;
2760 } else if (sampler){
2761 key->tex[i].compare_mode = sampler_state->compare_mode;
2762 key->tex[i].compare_func = sampler_state->compare_func;
2763 key->tex[i].wrap_s = sampler_state->wrap_s;
2764 key->tex[i].wrap_t = sampler_state->wrap_t;
2765 key->tex[i].force_first_level =
2766 vc4_sampler->force_first_level;
2767 }
2768 }
2769
2770 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2771 }
2772
2773 static void
2774 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2775 {
2776 struct vc4_job *job = vc4->job;
2777 struct vc4_fs_key local_key;
2778 struct vc4_fs_key *key = &local_key;
2779
2780 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2781 VC4_DIRTY_BLEND |
2782 VC4_DIRTY_FRAMEBUFFER |
2783 VC4_DIRTY_ZSA |
2784 VC4_DIRTY_RASTERIZER |
2785 VC4_DIRTY_SAMPLE_MASK |
2786 VC4_DIRTY_FRAGTEX |
2787 VC4_DIRTY_UNCOMPILED_FS |
2788 VC4_DIRTY_UBO_1_SIZE))) {
2789 return;
2790 }
2791
2792 memset(key, 0, sizeof(*key));
2793 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2794 key->base.shader_state = vc4->prog.bind_fs;
2795 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2796 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2797 prim_mode <= PIPE_PRIM_LINE_STRIP);
2798 key->blend = vc4->blend->rt[0];
2799 if (vc4->blend->logicop_enable) {
2800 key->logicop_func = vc4->blend->logicop_func;
2801 } else {
2802 key->logicop_func = PIPE_LOGICOP_COPY;
2803 }
2804 if (job->msaa) {
2805 key->msaa = vc4->rasterizer->base.multisample;
2806 key->sample_coverage = (vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2807 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2808 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2809 }
2810
2811 if (vc4->framebuffer.cbufs[0])
2812 key->color_format = vc4->framebuffer.cbufs[0]->format;
2813
2814 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2815 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2816 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2817 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2818 key->stencil_enabled);
2819 if (vc4->zsa->base.alpha.enabled)
2820 key->alpha_test_func = vc4->zsa->base.alpha.func;
2821 else
2822 key->alpha_test_func = COMPARE_FUNC_ALWAYS;
2823
2824 if (key->is_points) {
2825 key->point_sprite_mask =
2826 vc4->rasterizer->base.sprite_coord_enable;
2827 key->point_coord_upper_left =
2828 (vc4->rasterizer->base.sprite_coord_mode ==
2829 PIPE_SPRITE_COORD_UPPER_LEFT);
2830 }
2831
2832 key->ubo_1_size = vc4->constbuf[PIPE_SHADER_FRAGMENT].cb[1].buffer_size;
2833 key->light_twoside = vc4->rasterizer->base.light_twoside;
2834
2835 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2836 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2837 if (vc4->prog.fs == old_fs)
2838 return;
2839
2840 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2841
2842 if (vc4->rasterizer->base.flatshade &&
2843 (!old_fs || vc4->prog.fs->color_inputs != old_fs->color_inputs)) {
2844 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2845 }
2846
2847 if (!old_fs || vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2848 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2849 }
2850
2851 static void
2852 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2853 {
2854 struct vc4_vs_key local_key;
2855 struct vc4_vs_key *key = &local_key;
2856
2857 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2858 VC4_DIRTY_RASTERIZER |
2859 VC4_DIRTY_VERTTEX |
2860 VC4_DIRTY_VTXSTATE |
2861 VC4_DIRTY_UNCOMPILED_VS |
2862 VC4_DIRTY_FS_INPUTS))) {
2863 return;
2864 }
2865
2866 memset(key, 0, sizeof(*key));
2867 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2868 key->base.shader_state = vc4->prog.bind_vs;
2869 key->fs_inputs = vc4->prog.fs->fs_inputs;
2870 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2871
2872 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2873 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2874
2875 key->per_vertex_point_size =
2876 (prim_mode == PIPE_PRIM_POINTS &&
2877 vc4->rasterizer->base.point_size_per_vertex);
2878
2879 struct vc4_compiled_shader *vs =
2880 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2881 if (vs != vc4->prog.vs) {
2882 vc4->prog.vs = vs;
2883 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2884 }
2885
2886 key->is_coord = true;
2887 /* Coord shaders don't care what the FS inputs are. */
2888 key->fs_inputs = NULL;
2889 struct vc4_compiled_shader *cs =
2890 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2891 if (cs != vc4->prog.cs) {
2892 vc4->prog.cs = cs;
2893 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2894 }
2895 }
2896
2897 bool
2898 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2899 {
2900 vc4_update_compiled_fs(vc4, prim_mode);
2901 vc4_update_compiled_vs(vc4, prim_mode);
2902
2903 return !(vc4->prog.cs->failed ||
2904 vc4->prog.vs->failed ||
2905 vc4->prog.fs->failed);
2906 }
2907
2908 static uint32_t
2909 fs_cache_hash(const void *key)
2910 {
2911 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2912 }
2913
2914 static uint32_t
2915 vs_cache_hash(const void *key)
2916 {
2917 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2918 }
2919
2920 static bool
2921 fs_cache_compare(const void *key1, const void *key2)
2922 {
2923 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2924 }
2925
2926 static bool
2927 vs_cache_compare(const void *key1, const void *key2)
2928 {
2929 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2930 }
2931
2932 static uint32_t
2933 fs_inputs_hash(const void *key)
2934 {
2935 const struct vc4_fs_inputs *inputs = key;
2936
2937 return _mesa_hash_data(inputs->input_slots,
2938 sizeof(*inputs->input_slots) *
2939 inputs->num_inputs);
2940 }
2941
2942 static bool
2943 fs_inputs_compare(const void *key1, const void *key2)
2944 {
2945 const struct vc4_fs_inputs *inputs1 = key1;
2946 const struct vc4_fs_inputs *inputs2 = key2;
2947
2948 return (inputs1->num_inputs == inputs2->num_inputs &&
2949 memcmp(inputs1->input_slots,
2950 inputs2->input_slots,
2951 sizeof(*inputs1->input_slots) *
2952 inputs1->num_inputs) == 0);
2953 }
2954
2955 static void
2956 delete_from_cache_if_matches(struct hash_table *ht,
2957 struct vc4_compiled_shader **last_compile,
2958 struct hash_entry *entry,
2959 struct vc4_uncompiled_shader *so)
2960 {
2961 const struct vc4_key *key = entry->key;
2962
2963 if (key->shader_state == so) {
2964 struct vc4_compiled_shader *shader = entry->data;
2965 _mesa_hash_table_remove(ht, entry);
2966 vc4_bo_unreference(&shader->bo);
2967
2968 if (shader == *last_compile)
2969 *last_compile = NULL;
2970
2971 ralloc_free(shader);
2972 }
2973 }
2974
2975 static void
2976 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2977 {
2978 struct vc4_context *vc4 = vc4_context(pctx);
2979 struct vc4_uncompiled_shader *so = hwcso;
2980
2981 hash_table_foreach(vc4->fs_cache, entry) {
2982 delete_from_cache_if_matches(vc4->fs_cache, &vc4->prog.fs,
2983 entry, so);
2984 }
2985 hash_table_foreach(vc4->vs_cache, entry) {
2986 delete_from_cache_if_matches(vc4->vs_cache, &vc4->prog.vs,
2987 entry, so);
2988 }
2989
2990 ralloc_free(so->base.ir.nir);
2991 free(so);
2992 }
2993
2994 static void
2995 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2996 {
2997 struct vc4_context *vc4 = vc4_context(pctx);
2998 vc4->prog.bind_fs = hwcso;
2999 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
3000 }
3001
3002 static void
3003 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
3004 {
3005 struct vc4_context *vc4 = vc4_context(pctx);
3006 vc4->prog.bind_vs = hwcso;
3007 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
3008 }
3009
3010 void
3011 vc4_program_init(struct pipe_context *pctx)
3012 {
3013 struct vc4_context *vc4 = vc4_context(pctx);
3014
3015 pctx->create_vs_state = vc4_shader_state_create;
3016 pctx->delete_vs_state = vc4_shader_state_delete;
3017
3018 pctx->create_fs_state = vc4_shader_state_create;
3019 pctx->delete_fs_state = vc4_shader_state_delete;
3020
3021 pctx->bind_fs_state = vc4_fp_state_bind;
3022 pctx->bind_vs_state = vc4_vp_state_bind;
3023
3024 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
3025 fs_cache_compare);
3026 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
3027 vs_cache_compare);
3028 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
3029 fs_inputs_compare);
3030 }
3031
3032 void
3033 vc4_program_fini(struct pipe_context *pctx)
3034 {
3035 struct vc4_context *vc4 = vc4_context(pctx);
3036
3037 hash_table_foreach(vc4->fs_cache, entry) {
3038 struct vc4_compiled_shader *shader = entry->data;
3039 vc4_bo_unreference(&shader->bo);
3040 ralloc_free(shader);
3041 _mesa_hash_table_remove(vc4->fs_cache, entry);
3042 }
3043
3044 hash_table_foreach(vc4->vs_cache, entry) {
3045 struct vc4_compiled_shader *shader = entry->data;
3046 vc4_bo_unreference(&shader->bo);
3047 ralloc_free(shader);
3048 _mesa_hash_table_remove(vc4->vs_cache, entry);
3049 }
3050 }