2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
40 #ifdef USE_VC4_SIMULATOR
41 #include "simpenrose/simpenrose.h"
45 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
);
47 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
50 resize_qreg_array(struct vc4_compile
*c
,
55 if (*size
>= decl_size
)
58 uint32_t old_size
= *size
;
59 *size
= MAX2(*size
* 2, decl_size
);
60 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
62 fprintf(stderr
, "Malloc failure\n");
66 for (uint32_t i
= old_size
; i
< *size
; i
++)
67 (*regs
)[i
] = c
->undef
;
71 indirect_uniform_load(struct vc4_compile
*c
, nir_intrinsic_instr
*intr
)
73 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
74 uint32_t offset
= nir_intrinsic_base(intr
);
75 struct vc4_compiler_ubo_range
*range
= NULL
;
77 for (i
= 0; i
< c
->num_uniform_ranges
; i
++) {
78 range
= &c
->ubo_ranges
[i
];
79 if (offset
>= range
->src_offset
&&
80 offset
< range
->src_offset
+ range
->size
) {
84 /* The driver-location-based offset always has to be within a declared
90 range
->dst_offset
= c
->next_ubo_dst_offset
;
91 c
->next_ubo_dst_offset
+= range
->size
;
95 offset
-= range
->src_offset
;
97 /* Adjust for where we stored the TGSI register base. */
98 indirect_offset
= qir_ADD(c
, indirect_offset
,
99 qir_uniform_ui(c
, (range
->dst_offset
+
102 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
103 indirect_offset
= qir_MAX(c
, indirect_offset
, qir_uniform_ui(c
, 0));
104 indirect_offset
= qir_MIN(c
, indirect_offset
,
105 qir_uniform_ui(c
, (range
->dst_offset
+
108 qir_TEX_DIRECT(c
, indirect_offset
, qir_uniform(c
, QUNIFORM_UBO_ADDR
, 0));
109 c
->num_texture_samples
++;
110 return qir_TEX_RESULT(c
);
114 vc4_nir_get_swizzled_channel(nir_builder
*b
, nir_ssa_def
**srcs
, int swiz
)
118 case PIPE_SWIZZLE_NONE
:
119 fprintf(stderr
, "warning: unknown swizzle\n");
122 return nir_imm_float(b
, 0.0);
124 return nir_imm_float(b
, 1.0);
134 ntq_init_ssa_def(struct vc4_compile
*c
, nir_ssa_def
*def
)
136 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
137 def
->num_components
);
138 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
143 ntq_store_dest(struct vc4_compile
*c
, nir_dest
*dest
, int chan
,
147 assert(chan
< dest
->ssa
.num_components
);
150 struct hash_entry
*entry
=
151 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
156 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
158 qregs
[chan
] = result
;
160 nir_register
*reg
= dest
->reg
.reg
;
161 assert(dest
->reg
.base_offset
== 0);
162 assert(reg
->num_array_elems
== 0);
163 struct hash_entry
*entry
=
164 _mesa_hash_table_search(c
->def_ht
, reg
);
165 struct qreg
*qregs
= entry
->data
;
167 /* Conditionally move the result to the destination if the
170 if (c
->execute
.file
!= QFILE_NULL
) {
171 qir_SF(c
, c
->execute
);
172 qir_MOV_cond(c
, QPU_COND_ZS
, qregs
[chan
], result
);
174 qir_MOV_dest(c
, qregs
[chan
], result
);
180 ntq_get_dest(struct vc4_compile
*c
, nir_dest
*dest
)
183 struct qreg
*qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
184 for (int i
= 0; i
< dest
->ssa
.num_components
; i
++)
188 nir_register
*reg
= dest
->reg
.reg
;
189 assert(dest
->reg
.base_offset
== 0);
190 assert(reg
->num_array_elems
== 0);
191 struct hash_entry
*entry
=
192 _mesa_hash_table_search(c
->def_ht
, reg
);
198 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
)
200 struct hash_entry
*entry
;
202 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
203 assert(i
< src
.ssa
->num_components
);
205 nir_register
*reg
= src
.reg
.reg
;
206 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
207 assert(reg
->num_array_elems
== 0);
208 assert(src
.reg
.base_offset
== 0);
209 assert(i
< reg
->num_components
);
212 struct qreg
*qregs
= entry
->data
;
217 ntq_get_alu_src(struct vc4_compile
*c
, nir_alu_instr
*instr
,
220 assert(util_is_power_of_two(instr
->dest
.write_mask
));
221 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
222 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
223 instr
->src
[src
].swizzle
[chan
]);
225 assert(!instr
->src
[src
].abs
);
226 assert(!instr
->src
[src
].negate
);
231 static inline struct qreg
232 qir_SAT(struct vc4_compile
*c
, struct qreg val
)
235 qir_FMIN(c
, val
, qir_uniform_f(c
, 1.0)),
236 qir_uniform_f(c
, 0.0));
240 ntq_rcp(struct vc4_compile
*c
, struct qreg x
)
242 struct qreg r
= qir_RCP(c
, x
);
244 /* Apply a Newton-Raphson step to improve the accuracy. */
245 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
246 qir_uniform_f(c
, 2.0),
253 ntq_rsq(struct vc4_compile
*c
, struct qreg x
)
255 struct qreg r
= qir_RSQ(c
, x
);
257 /* Apply a Newton-Raphson step to improve the accuracy. */
258 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
259 qir_uniform_f(c
, 1.5),
261 qir_uniform_f(c
, 0.5),
263 qir_FMUL(c
, r
, r
)))));
269 ntq_umul(struct vc4_compile
*c
, struct qreg src0
, struct qreg src1
)
271 struct qreg src0_hi
= qir_SHR(c
, src0
,
272 qir_uniform_ui(c
, 24));
273 struct qreg src1_hi
= qir_SHR(c
, src1
,
274 qir_uniform_ui(c
, 24));
276 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1
);
277 struct qreg lohi
= qir_MUL24(c
, src0
, src1_hi
);
278 struct qreg lolo
= qir_MUL24(c
, src0
, src1
);
280 return qir_ADD(c
, lolo
, qir_SHL(c
,
281 qir_ADD(c
, hilo
, lohi
),
282 qir_uniform_ui(c
, 24)));
286 ntq_scale_depth_texture(struct vc4_compile
*c
, struct qreg src
)
288 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, src
,
289 qir_uniform_ui(c
, 8)));
290 return qir_FMUL(c
, depthf
, qir_uniform_f(c
, 1.0f
/0xffffff));
294 * Emits a lowered TXF_MS from an MSAA texture.
296 * The addressing math has been lowered in NIR, and now we just need to read
300 ntq_emit_txf(struct vc4_compile
*c
, nir_tex_instr
*instr
)
302 uint32_t tile_width
= 32;
303 uint32_t tile_height
= 32;
304 uint32_t tile_size
= (tile_height
* tile_width
*
305 VC4_MAX_SAMPLES
* sizeof(uint32_t));
307 unsigned unit
= instr
->texture_index
;
308 uint32_t w
= align(c
->key
->tex
[unit
].msaa_width
, tile_width
);
309 uint32_t w_tiles
= w
/ tile_width
;
310 uint32_t h
= align(c
->key
->tex
[unit
].msaa_height
, tile_height
);
311 uint32_t h_tiles
= h
/ tile_height
;
312 uint32_t size
= w_tiles
* h_tiles
* tile_size
;
315 assert(instr
->num_srcs
== 1);
316 assert(instr
->src
[0].src_type
== nir_tex_src_coord
);
317 addr
= ntq_get_src(c
, instr
->src
[0].src
, 0);
319 /* Perform the clamping required by kernel validation. */
320 addr
= qir_MAX(c
, addr
, qir_uniform_ui(c
, 0));
321 addr
= qir_MIN(c
, addr
, qir_uniform_ui(c
, size
- 4));
323 qir_TEX_DIRECT(c
, addr
, qir_uniform(c
, QUNIFORM_TEXTURE_MSAA_ADDR
, unit
));
325 struct qreg tex
= qir_TEX_RESULT(c
);
326 c
->num_texture_samples
++;
329 enum pipe_format format
= c
->key
->tex
[unit
].format
;
330 if (util_format_is_depth_or_stencil(format
)) {
331 struct qreg scaled
= ntq_scale_depth_texture(c
, tex
);
332 for (int i
= 0; i
< 4; i
++)
335 for (int i
= 0; i
< 4; i
++)
336 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
339 for (int i
= 0; i
< 4; i
++)
340 ntq_store_dest(c
, &instr
->dest
, i
, dest
[i
]);
344 ntq_emit_tex(struct vc4_compile
*c
, nir_tex_instr
*instr
)
346 struct qreg s
, t
, r
, lod
, compare
;
347 bool is_txb
= false, is_txl
= false;
348 unsigned unit
= instr
->texture_index
;
350 if (instr
->op
== nir_texop_txf
) {
351 ntq_emit_txf(c
, instr
);
355 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
356 switch (instr
->src
[i
].src_type
) {
357 case nir_tex_src_coord
:
358 s
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
359 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
)
360 t
= qir_uniform_f(c
, 0.5);
362 t
= ntq_get_src(c
, instr
->src
[i
].src
, 1);
363 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
364 r
= ntq_get_src(c
, instr
->src
[i
].src
, 2);
366 case nir_tex_src_bias
:
367 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
370 case nir_tex_src_lod
:
371 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
374 case nir_tex_src_comparitor
:
375 compare
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
378 unreachable("unknown texture source");
382 if (c
->key
->tex
[unit
].force_first_level
) {
383 lod
= qir_uniform(c
, QUNIFORM_TEXTURE_FIRST_LEVEL
, unit
);
388 struct qreg texture_u
[] = {
389 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
390 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
391 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
392 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
394 uint32_t next_texture_u
= 0;
396 /* There is no native support for GL texture rectangle coordinates, so
397 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
400 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
) {
402 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_X
, unit
));
404 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_Y
, unit
));
407 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
|| is_txl
) {
408 texture_u
[2] = qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
,
409 unit
| (is_txl
<< 16));
412 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
413 qir_TEX_R(c
, r
, texture_u
[next_texture_u
++]);
414 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
415 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
416 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
417 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
418 qir_TEX_R(c
, qir_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
, unit
),
419 texture_u
[next_texture_u
++]);
422 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
426 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
430 qir_TEX_T(c
, t
, texture_u
[next_texture_u
++]);
432 if (is_txl
|| is_txb
)
433 qir_TEX_B(c
, lod
, texture_u
[next_texture_u
++]);
435 qir_TEX_S(c
, s
, texture_u
[next_texture_u
++]);
437 c
->num_texture_samples
++;
438 struct qreg tex
= qir_TEX_RESULT(c
);
440 enum pipe_format format
= c
->key
->tex
[unit
].format
;
442 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
);
443 if (util_format_is_depth_or_stencil(format
)) {
444 struct qreg normalized
= ntq_scale_depth_texture(c
, tex
);
445 struct qreg depth_output
;
447 struct qreg u0
= qir_uniform_f(c
, 0.0f
);
448 struct qreg u1
= qir_uniform_f(c
, 1.0f
);
449 if (c
->key
->tex
[unit
].compare_mode
) {
450 switch (c
->key
->tex
[unit
].compare_func
) {
451 case PIPE_FUNC_NEVER
:
452 depth_output
= qir_uniform_f(c
, 0.0f
);
454 case PIPE_FUNC_ALWAYS
:
457 case PIPE_FUNC_EQUAL
:
458 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
459 depth_output
= qir_SEL(c
, QPU_COND_ZS
, u1
, u0
);
461 case PIPE_FUNC_NOTEQUAL
:
462 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
463 depth_output
= qir_SEL(c
, QPU_COND_ZC
, u1
, u0
);
465 case PIPE_FUNC_GREATER
:
466 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
467 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
469 case PIPE_FUNC_GEQUAL
:
470 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
471 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
474 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
475 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
477 case PIPE_FUNC_LEQUAL
:
478 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
479 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
483 depth_output
= normalized
;
486 for (int i
= 0; i
< 4; i
++)
487 dest
[i
] = depth_output
;
489 for (int i
= 0; i
< 4; i
++)
490 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
495 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
499 ntq_ffract(struct vc4_compile
*c
, struct qreg src
)
501 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
502 struct qreg diff
= qir_FSUB(c
, src
, trunc
);
504 return qir_SEL(c
, QPU_COND_NS
,
505 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)), diff
);
509 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
513 ntq_ffloor(struct vc4_compile
*c
, struct qreg src
)
515 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
517 /* This will be < 0 if we truncated and the truncation was of a value
518 * that was < 0 in the first place.
520 qir_SF(c
, qir_FSUB(c
, src
, trunc
));
522 return qir_SEL(c
, QPU_COND_NS
,
523 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
527 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
531 ntq_fceil(struct vc4_compile
*c
, struct qreg src
)
533 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
535 /* This will be < 0 if we truncated and the truncation was of a value
536 * that was > 0 in the first place.
538 qir_SF(c
, qir_FSUB(c
, trunc
, src
));
540 return qir_SEL(c
, QPU_COND_NS
,
541 qir_FADD(c
, trunc
, qir_uniform_f(c
, 1.0)), trunc
);
545 ntq_fsin(struct vc4_compile
*c
, struct qreg src
)
549 pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
550 -pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
551 pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
552 -pow(2.0 * M_PI
, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
555 struct qreg scaled_x
=
558 qir_uniform_f(c
, 1.0 / (M_PI
* 2.0)));
560 struct qreg x
= qir_FADD(c
,
561 ntq_ffract(c
, scaled_x
),
562 qir_uniform_f(c
, -0.5));
563 struct qreg x2
= qir_FMUL(c
, x
, x
);
564 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
565 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
566 x
= qir_FMUL(c
, x
, x2
);
571 qir_uniform_f(c
, coeff
[i
])));
577 ntq_fcos(struct vc4_compile
*c
, struct qreg src
)
581 pow(2.0 * M_PI
, 2) / (2 * 1),
582 -pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
583 pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
584 -pow(2.0 * M_PI
, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
585 pow(2.0 * M_PI
, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
588 struct qreg scaled_x
=
590 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
591 struct qreg x_frac
= qir_FADD(c
,
592 ntq_ffract(c
, scaled_x
),
593 qir_uniform_f(c
, -0.5));
595 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
596 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
597 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
598 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
600 x
= qir_FMUL(c
, x
, x2
);
602 struct qreg mul
= qir_FMUL(c
,
604 qir_uniform_f(c
, coeff
[i
]));
608 sum
= qir_FADD(c
, sum
, mul
);
614 ntq_fsign(struct vc4_compile
*c
, struct qreg src
)
616 struct qreg t
= qir_get_temp(c
);
619 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 0.0));
620 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_ZC
;
621 qir_MOV_dest(c
, t
, qir_uniform_f(c
, -1.0))->cond
= QPU_COND_NS
;
626 emit_vertex_input(struct vc4_compile
*c
, int attr
)
628 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
629 uint32_t attr_size
= util_format_get_blocksize(format
);
631 c
->vattr_sizes
[attr
] = align(attr_size
, 4);
632 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
633 c
->inputs
[attr
* 4 + i
] =
634 qir_MOV(c
, qir_reg(QFILE_VPM
, attr
* 4 + i
));
640 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
642 c
->inputs
[attr
* 4 + 0] = qir_ITOF(c
, qir_reg(QFILE_FRAG_X
, 0));
643 c
->inputs
[attr
* 4 + 1] = qir_ITOF(c
, qir_reg(QFILE_FRAG_Y
, 0));
644 c
->inputs
[attr
* 4 + 2] =
646 qir_ITOF(c
, qir_FRAG_Z(c
)),
647 qir_uniform_f(c
, 1.0 / 0xffffff));
648 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
652 emit_fragment_varying(struct vc4_compile
*c
, gl_varying_slot slot
,
655 uint32_t i
= c
->num_input_slots
++;
661 if (c
->num_input_slots
>= c
->input_slots_array_size
) {
662 c
->input_slots_array_size
=
663 MAX2(4, c
->input_slots_array_size
* 2);
665 c
->input_slots
= reralloc(c
, c
->input_slots
,
666 struct vc4_varying_slot
,
667 c
->input_slots_array_size
);
670 c
->input_slots
[i
].slot
= slot
;
671 c
->input_slots
[i
].swizzle
= swizzle
;
673 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
677 emit_fragment_input(struct vc4_compile
*c
, int attr
, gl_varying_slot slot
)
679 for (int i
= 0; i
< 4; i
++) {
680 c
->inputs
[attr
* 4 + i
] =
681 emit_fragment_varying(c
, slot
, i
);
687 add_output(struct vc4_compile
*c
,
688 uint32_t decl_offset
,
692 uint32_t old_array_size
= c
->outputs_array_size
;
693 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
696 if (old_array_size
!= c
->outputs_array_size
) {
697 c
->output_slots
= reralloc(c
,
699 struct vc4_varying_slot
,
700 c
->outputs_array_size
);
703 c
->output_slots
[decl_offset
].slot
= slot
;
704 c
->output_slots
[decl_offset
].swizzle
= swizzle
;
708 declare_uniform_range(struct vc4_compile
*c
, uint32_t start
, uint32_t size
)
710 unsigned array_id
= c
->num_uniform_ranges
++;
711 if (array_id
>= c
->ubo_ranges_array_size
) {
712 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
714 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
715 struct vc4_compiler_ubo_range
,
716 c
->ubo_ranges_array_size
);
719 c
->ubo_ranges
[array_id
].dst_offset
= 0;
720 c
->ubo_ranges
[array_id
].src_offset
= start
;
721 c
->ubo_ranges
[array_id
].size
= size
;
722 c
->ubo_ranges
[array_id
].used
= false;
726 ntq_src_is_only_ssa_def_user(nir_src
*src
)
731 if (!list_empty(&src
->ssa
->if_uses
))
734 return (src
->ssa
->uses
.next
== &src
->use_link
&&
735 src
->ssa
->uses
.next
->next
== &src
->ssa
->uses
);
739 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
742 * However, as an optimization, it tries to find the instructions generating
743 * the sources to be packed and just emit the pack flag there, if possible.
746 ntq_emit_pack_unorm_4x8(struct vc4_compile
*c
, nir_alu_instr
*instr
)
748 struct qreg result
= qir_get_temp(c
);
749 struct nir_alu_instr
*vec4
= NULL
;
751 /* If packing from a vec4 op (as expected), identify it so that we can
752 * peek back at what generated its sources.
754 if (instr
->src
[0].src
.is_ssa
&&
755 instr
->src
[0].src
.ssa
->parent_instr
->type
== nir_instr_type_alu
&&
756 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
)->op
==
758 vec4
= nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
761 /* If the pack is replicating the same channel 4 times, use the 8888
762 * pack flag. This is common for blending using the alpha
765 if (instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[1] &&
766 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[2] &&
767 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[3]) {
768 struct qreg rep
= ntq_get_src(c
,
770 instr
->src
[0].swizzle
[0]);
771 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_PACK_8888_F(c
, rep
));
775 for (int i
= 0; i
< 4; i
++) {
776 int swiz
= instr
->src
[0].swizzle
[i
];
779 src
= ntq_get_src(c
, vec4
->src
[swiz
].src
,
780 vec4
->src
[swiz
].swizzle
[0]);
782 src
= ntq_get_src(c
, instr
->src
[0].src
, swiz
);
786 ntq_src_is_only_ssa_def_user(&vec4
->src
[swiz
].src
) &&
787 src
.file
== QFILE_TEMP
&&
788 c
->defs
[src
.index
] &&
789 qir_is_mul(c
->defs
[src
.index
]) &&
790 !c
->defs
[src
.index
]->dst
.pack
) {
791 struct qinst
*rewrite
= c
->defs
[src
.index
];
792 c
->defs
[src
.index
] = NULL
;
793 rewrite
->dst
= result
;
794 rewrite
->dst
.pack
= QPU_PACK_MUL_8A
+ i
;
798 qir_PACK_8_F(c
, result
, src
, i
);
801 ntq_store_dest(c
, &instr
->dest
.dest
, 0, result
);
804 /** Handles sign-extended bitfield extracts for 16 bits. */
806 ntq_emit_ibfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
809 assert(bits
.file
== QFILE_UNIF
&&
810 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
811 c
->uniform_data
[bits
.index
] == 16);
813 assert(offset
.file
== QFILE_UNIF
&&
814 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
815 int offset_bit
= c
->uniform_data
[offset
.index
];
816 assert(offset_bit
% 16 == 0);
818 return qir_UNPACK_16_I(c
, base
, offset_bit
/ 16);
821 /** Handles unsigned bitfield extracts for 8 bits. */
823 ntq_emit_ubfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
826 assert(bits
.file
== QFILE_UNIF
&&
827 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
828 c
->uniform_data
[bits
.index
] == 8);
830 assert(offset
.file
== QFILE_UNIF
&&
831 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
832 int offset_bit
= c
->uniform_data
[offset
.index
];
833 assert(offset_bit
% 8 == 0);
835 return qir_UNPACK_8_I(c
, base
, offset_bit
/ 8);
839 * If compare_instr is a valid comparison instruction, emits the
840 * compare_instr's comparison and returns the sel_instr's return value based
841 * on the compare_instr's result.
844 ntq_emit_comparison(struct vc4_compile
*c
, struct qreg
*dest
,
845 nir_alu_instr
*compare_instr
,
846 nir_alu_instr
*sel_instr
)
850 switch (compare_instr
->op
) {
876 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
877 struct qreg src1
= ntq_get_alu_src(c
, compare_instr
, 1);
879 unsigned unsized_type
=
880 nir_alu_type_get_base_type(nir_op_infos
[compare_instr
->op
].input_types
[0]);
881 if (unsized_type
== nir_type_float
)
882 qir_SF(c
, qir_FSUB(c
, src0
, src1
));
884 qir_SF(c
, qir_SUB(c
, src0
, src1
));
886 switch (sel_instr
->op
) {
891 *dest
= qir_SEL(c
, cond
,
892 qir_uniform_f(c
, 1.0), qir_uniform_f(c
, 0.0));
896 *dest
= qir_SEL(c
, cond
,
897 ntq_get_alu_src(c
, sel_instr
, 1),
898 ntq_get_alu_src(c
, sel_instr
, 2));
902 *dest
= qir_SEL(c
, cond
,
903 qir_uniform_ui(c
, ~0), qir_uniform_ui(c
, 0));
911 * Attempts to fold a comparison generating a boolean result into the
912 * condition code for selecting between two values, instead of comparing the
913 * boolean result against 0 to generate the condition code.
915 static struct qreg
ntq_emit_bcsel(struct vc4_compile
*c
, nir_alu_instr
*instr
,
918 if (!instr
->src
[0].src
.is_ssa
)
920 nir_alu_instr
*compare
=
921 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
926 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
931 return qir_SEL(c
, QPU_COND_NS
, src
[1], src
[2]);
935 ntq_emit_alu(struct vc4_compile
*c
, nir_alu_instr
*instr
)
937 /* This should always be lowered to ALU operations for VC4. */
938 assert(!instr
->dest
.saturate
);
940 /* Vectors are special in that they have non-scalarized writemasks,
941 * and just take the first swizzle channel for each argument in order
942 * into each writemask channel.
944 if (instr
->op
== nir_op_vec2
||
945 instr
->op
== nir_op_vec3
||
946 instr
->op
== nir_op_vec4
) {
948 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
949 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
950 instr
->src
[i
].swizzle
[0]);
951 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
952 ntq_store_dest(c
, &instr
->dest
.dest
, i
, srcs
[i
]);
956 if (instr
->op
== nir_op_pack_unorm_4x8
) {
957 ntq_emit_pack_unorm_4x8(c
, instr
);
961 if (instr
->op
== nir_op_unpack_unorm_4x8
) {
962 struct qreg src
= ntq_get_src(c
, instr
->src
[0].src
,
963 instr
->src
[0].swizzle
[0]);
964 for (int i
= 0; i
< 4; i
++) {
965 if (instr
->dest
.write_mask
& (1 << i
))
966 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
967 qir_UNPACK_8_F(c
, src
, i
));
972 /* General case: We can just grab the one used channel per src. */
973 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
974 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
975 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
983 result
= qir_MOV(c
, src
[0]);
986 result
= qir_FMUL(c
, src
[0], src
[1]);
989 result
= qir_FADD(c
, src
[0], src
[1]);
992 result
= qir_FSUB(c
, src
[0], src
[1]);
995 result
= qir_FMIN(c
, src
[0], src
[1]);
998 result
= qir_FMAX(c
, src
[0], src
[1]);
1003 result
= qir_FTOI(c
, src
[0]);
1007 result
= qir_ITOF(c
, src
[0]);
1010 result
= qir_AND(c
, src
[0], qir_uniform_f(c
, 1.0));
1013 result
= qir_AND(c
, src
[0], qir_uniform_ui(c
, 1));
1018 result
= qir_SEL(c
, QPU_COND_ZC
,
1019 qir_uniform_ui(c
, ~0),
1020 qir_uniform_ui(c
, 0));
1024 result
= qir_ADD(c
, src
[0], src
[1]);
1027 result
= qir_SHR(c
, src
[0], src
[1]);
1030 result
= qir_SUB(c
, src
[0], src
[1]);
1033 result
= qir_ASR(c
, src
[0], src
[1]);
1036 result
= qir_SHL(c
, src
[0], src
[1]);
1039 result
= qir_MIN(c
, src
[0], src
[1]);
1042 result
= qir_MAX(c
, src
[0], src
[1]);
1045 result
= qir_AND(c
, src
[0], src
[1]);
1048 result
= qir_OR(c
, src
[0], src
[1]);
1051 result
= qir_XOR(c
, src
[0], src
[1]);
1054 result
= qir_NOT(c
, src
[0]);
1058 result
= ntq_umul(c
, src
[0], src
[1]);
1074 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
1075 fprintf(stderr
, "Bad comparison instruction\n");
1080 result
= ntq_emit_bcsel(c
, instr
, src
);
1084 result
= qir_SEL(c
, QPU_COND_ZC
, src
[1], src
[2]);
1088 result
= ntq_rcp(c
, src
[0]);
1091 result
= ntq_rsq(c
, src
[0]);
1094 result
= qir_EXP2(c
, src
[0]);
1097 result
= qir_LOG2(c
, src
[0]);
1101 result
= qir_ITOF(c
, qir_FTOI(c
, src
[0]));
1104 result
= ntq_fceil(c
, src
[0]);
1107 result
= ntq_ffract(c
, src
[0]);
1110 result
= ntq_ffloor(c
, src
[0]);
1114 result
= ntq_fsin(c
, src
[0]);
1117 result
= ntq_fcos(c
, src
[0]);
1121 result
= ntq_fsign(c
, src
[0]);
1125 result
= qir_FMAXABS(c
, src
[0], src
[0]);
1128 result
= qir_MAX(c
, src
[0],
1129 qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0]));
1132 case nir_op_ibitfield_extract
:
1133 result
= ntq_emit_ibfe(c
, src
[0], src
[1], src
[2]);
1136 case nir_op_ubitfield_extract
:
1137 result
= ntq_emit_ubfe(c
, src
[0], src
[1], src
[2]);
1140 case nir_op_usadd_4x8
:
1141 result
= qir_V8ADDS(c
, src
[0], src
[1]);
1144 case nir_op_ussub_4x8
:
1145 result
= qir_V8SUBS(c
, src
[0], src
[1]);
1148 case nir_op_umin_4x8
:
1149 result
= qir_V8MIN(c
, src
[0], src
[1]);
1152 case nir_op_umax_4x8
:
1153 result
= qir_V8MAX(c
, src
[0], src
[1]);
1156 case nir_op_umul_unorm_4x8
:
1157 result
= qir_V8MULD(c
, src
[0], src
[1]);
1161 fprintf(stderr
, "unknown NIR ALU inst: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1167 /* We have a scalar result, so the instruction should only have a
1168 * single channel written to.
1170 assert(util_is_power_of_two(instr
->dest
.write_mask
));
1171 ntq_store_dest(c
, &instr
->dest
.dest
,
1172 ffs(instr
->dest
.write_mask
) - 1, result
);
1176 emit_frag_end(struct vc4_compile
*c
)
1179 if (c
->output_color_index
!= -1) {
1180 color
= c
->outputs
[c
->output_color_index
];
1182 color
= qir_uniform_ui(c
, 0);
1185 uint32_t discard_cond
= QPU_COND_ALWAYS
;
1186 if (c
->discard
.file
!= QFILE_NULL
) {
1187 qir_SF(c
, c
->discard
);
1188 discard_cond
= QPU_COND_ZS
;
1191 if (c
->fs_key
->stencil_enabled
) {
1192 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1193 qir_uniform(c
, QUNIFORM_STENCIL
, 0));
1194 if (c
->fs_key
->stencil_twoside
) {
1195 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1196 qir_uniform(c
, QUNIFORM_STENCIL
, 1));
1198 if (c
->fs_key
->stencil_full_writemasks
) {
1199 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1200 qir_uniform(c
, QUNIFORM_STENCIL
, 2));
1204 if (c
->output_sample_mask_index
!= -1) {
1205 qir_MS_MASK(c
, c
->outputs
[c
->output_sample_mask_index
]);
1208 if (c
->fs_key
->depth_enabled
) {
1209 if (c
->output_position_index
!= -1) {
1210 qir_FTOI_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1212 c
->outputs
[c
->output_position_index
],
1213 qir_uniform_f(c
, 0xffffff)))->cond
= discard_cond
;
1215 qir_MOV_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1216 qir_FRAG_Z(c
))->cond
= discard_cond
;
1220 if (!c
->msaa_per_sample_output
) {
1221 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE
, 0),
1222 color
)->cond
= discard_cond
;
1224 for (int i
= 0; i
< VC4_MAX_SAMPLES
; i
++) {
1225 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE_MS
, 0),
1226 c
->sample_colors
[i
])->cond
= discard_cond
;
1232 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1234 struct qreg packed
= qir_get_temp(c
);
1236 for (int i
= 0; i
< 2; i
++) {
1238 qir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1240 struct qreg packed_chan
= packed
;
1241 packed_chan
.pack
= QPU_PACK_A_16A
+ i
;
1243 qir_FTOI_dest(c
, packed_chan
,
1246 c
->outputs
[c
->output_position_index
+ i
],
1251 qir_VPM_WRITE(c
, packed
);
1255 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1257 struct qreg zscale
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1258 struct qreg zoffset
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1260 qir_VPM_WRITE(c
, qir_FADD(c
, qir_FMUL(c
, qir_FMUL(c
,
1261 c
->outputs
[c
->output_position_index
+ 2],
1268 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1270 qir_VPM_WRITE(c
, rcp_w
);
1274 emit_point_size_write(struct vc4_compile
*c
)
1276 struct qreg point_size
;
1278 if (c
->output_point_size_index
!= -1)
1279 point_size
= c
->outputs
[c
->output_point_size_index
];
1281 point_size
= qir_uniform_f(c
, 1.0);
1283 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1286 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1288 qir_VPM_WRITE(c
, point_size
);
1292 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1294 * The simulator insists that there be at least one vertex attribute, so
1295 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1296 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1297 * to consume it here.
1300 emit_stub_vpm_read(struct vc4_compile
*c
)
1305 c
->vattr_sizes
[0] = 4;
1306 (void)qir_MOV(c
, qir_reg(QFILE_VPM
, 0));
1311 emit_vert_end(struct vc4_compile
*c
,
1312 struct vc4_varying_slot
*fs_inputs
,
1313 uint32_t num_fs_inputs
)
1315 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1317 emit_stub_vpm_read(c
);
1319 emit_scaled_viewport_write(c
, rcp_w
);
1320 emit_zs_write(c
, rcp_w
);
1321 emit_rcp_wc_write(c
, rcp_w
);
1322 if (c
->vs_key
->per_vertex_point_size
)
1323 emit_point_size_write(c
);
1325 for (int i
= 0; i
< num_fs_inputs
; i
++) {
1326 struct vc4_varying_slot
*input
= &fs_inputs
[i
];
1329 for (j
= 0; j
< c
->num_outputs
; j
++) {
1330 struct vc4_varying_slot
*output
=
1331 &c
->output_slots
[j
];
1333 if (input
->slot
== output
->slot
&&
1334 input
->swizzle
== output
->swizzle
) {
1335 qir_VPM_WRITE(c
, c
->outputs
[j
]);
1339 /* Emit padding if we didn't find a declared VS output for
1342 if (j
== c
->num_outputs
)
1343 qir_VPM_WRITE(c
, qir_uniform_f(c
, 0.0));
1348 emit_coord_end(struct vc4_compile
*c
)
1350 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1352 emit_stub_vpm_read(c
);
1354 for (int i
= 0; i
< 4; i
++)
1355 qir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
]);
1357 emit_scaled_viewport_write(c
, rcp_w
);
1358 emit_zs_write(c
, rcp_w
);
1359 emit_rcp_wc_write(c
, rcp_w
);
1360 if (c
->vs_key
->per_vertex_point_size
)
1361 emit_point_size_write(c
);
1365 vc4_optimize_nir(struct nir_shader
*s
)
1372 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1373 NIR_PASS_V(s
, nir_lower_alu_to_scalar
);
1374 NIR_PASS_V(s
, nir_lower_phis_to_scalar
);
1376 NIR_PASS(progress
, s
, nir_copy_prop
);
1377 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1378 NIR_PASS(progress
, s
, nir_opt_dce
);
1379 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1380 NIR_PASS(progress
, s
, nir_opt_cse
);
1381 NIR_PASS(progress
, s
, nir_opt_peephole_select
);
1382 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1383 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1384 NIR_PASS(progress
, s
, nir_opt_undef
);
1389 driver_location_compare(const void *in_a
, const void *in_b
)
1391 const nir_variable
*const *a
= in_a
;
1392 const nir_variable
*const *b
= in_b
;
1394 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1398 ntq_setup_inputs(struct vc4_compile
*c
)
1400 unsigned num_entries
= 0;
1401 nir_foreach_variable(var
, &c
->s
->inputs
)
1404 nir_variable
*vars
[num_entries
];
1407 nir_foreach_variable(var
, &c
->s
->inputs
)
1410 /* Sort the variables so that we emit the input setup in
1411 * driver_location order. This is required for VPM reads, whose data
1412 * is fetched into the VPM in driver_location (TGSI register index)
1415 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1417 for (unsigned i
= 0; i
< num_entries
; i
++) {
1418 nir_variable
*var
= vars
[i
];
1419 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1420 unsigned loc
= var
->data
.driver_location
;
1422 assert(array_len
== 1);
1424 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1427 if (c
->stage
== QSTAGE_FRAG
) {
1428 if (var
->data
.location
== VARYING_SLOT_POS
) {
1429 emit_fragcoord_input(c
, loc
);
1430 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1431 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1432 (c
->fs_key
->point_sprite_mask
&
1433 (1 << (var
->data
.location
-
1434 VARYING_SLOT_VAR0
))))) {
1435 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1436 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1438 emit_fragment_input(c
, loc
, var
->data
.location
);
1441 emit_vertex_input(c
, loc
);
1447 ntq_setup_outputs(struct vc4_compile
*c
)
1449 nir_foreach_variable(var
, &c
->s
->outputs
) {
1450 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1451 unsigned loc
= var
->data
.driver_location
* 4;
1453 assert(array_len
== 1);
1456 for (int i
= 0; i
< 4; i
++)
1457 add_output(c
, loc
+ i
, var
->data
.location
, i
);
1459 if (c
->stage
== QSTAGE_FRAG
) {
1460 switch (var
->data
.location
) {
1461 case FRAG_RESULT_COLOR
:
1462 case FRAG_RESULT_DATA0
:
1463 c
->output_color_index
= loc
;
1465 case FRAG_RESULT_DEPTH
:
1466 c
->output_position_index
= loc
;
1468 case FRAG_RESULT_SAMPLE_MASK
:
1469 c
->output_sample_mask_index
= loc
;
1473 switch (var
->data
.location
) {
1474 case VARYING_SLOT_POS
:
1475 c
->output_position_index
= loc
;
1477 case VARYING_SLOT_PSIZ
:
1478 c
->output_point_size_index
= loc
;
1486 ntq_setup_uniforms(struct vc4_compile
*c
)
1488 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1489 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1490 unsigned array_elem_size
= 4 * sizeof(float);
1492 declare_uniform_range(c
, var
->data
.driver_location
* array_elem_size
,
1493 array_len
* array_elem_size
);
1499 * Sets up the mapping from nir_register to struct qreg *.
1501 * Each nir_register gets a struct qreg per 32-bit component being stored.
1504 ntq_setup_registers(struct vc4_compile
*c
, struct exec_list
*list
)
1506 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1507 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1508 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1510 nir_reg
->num_components
);
1512 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1514 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1515 qregs
[i
] = qir_get_temp(c
);
1520 ntq_emit_load_const(struct vc4_compile
*c
, nir_load_const_instr
*instr
)
1522 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1523 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1524 qregs
[i
] = qir_uniform_ui(c
, instr
->value
.u32
[i
]);
1526 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1530 ntq_emit_ssa_undef(struct vc4_compile
*c
, nir_ssa_undef_instr
*instr
)
1532 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1534 /* QIR needs there to be *some* value, so pick 0 (same as for
1535 * ntq_setup_registers().
1537 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1538 qregs
[i
] = qir_uniform_ui(c
, 0);
1542 ntq_emit_intrinsic(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1544 nir_const_value
*const_offset
;
1547 switch (instr
->intrinsic
) {
1548 case nir_intrinsic_load_uniform
:
1549 assert(instr
->num_components
== 1);
1550 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1552 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1553 assert(offset
% 4 == 0);
1554 /* We need dwords */
1555 offset
= offset
/ 4;
1556 ntq_store_dest(c
, &instr
->dest
, 0,
1557 qir_uniform(c
, QUNIFORM_UNIFORM
,
1560 ntq_store_dest(c
, &instr
->dest
, 0,
1561 indirect_uniform_load(c
, instr
));
1565 case nir_intrinsic_load_user_clip_plane
:
1566 for (int i
= 0; i
< instr
->num_components
; i
++) {
1567 ntq_store_dest(c
, &instr
->dest
, i
,
1568 qir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1569 nir_intrinsic_ucp_id(instr
) *
1574 case nir_intrinsic_load_blend_const_color_r_float
:
1575 case nir_intrinsic_load_blend_const_color_g_float
:
1576 case nir_intrinsic_load_blend_const_color_b_float
:
1577 case nir_intrinsic_load_blend_const_color_a_float
:
1578 ntq_store_dest(c
, &instr
->dest
, 0,
1579 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_X
+
1581 nir_intrinsic_load_blend_const_color_r_float
),
1585 case nir_intrinsic_load_blend_const_color_rgba8888_unorm
:
1586 ntq_store_dest(c
, &instr
->dest
, 0,
1587 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_RGBA
,
1591 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm
:
1592 ntq_store_dest(c
, &instr
->dest
, 0,
1593 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_AAAA
,
1597 case nir_intrinsic_load_alpha_ref_float
:
1598 ntq_store_dest(c
, &instr
->dest
, 0,
1599 qir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1602 case nir_intrinsic_load_sample_mask_in
:
1603 ntq_store_dest(c
, &instr
->dest
, 0,
1604 qir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1607 case nir_intrinsic_load_front_face
:
1608 /* The register contains 0 (front) or 1 (back), and we need to
1609 * turn it into a NIR bool where true means front.
1611 ntq_store_dest(c
, &instr
->dest
, 0,
1613 qir_uniform_ui(c
, -1),
1614 qir_reg(QFILE_FRAG_REV_FLAG
, 0)));
1617 case nir_intrinsic_load_input
:
1618 assert(instr
->num_components
== 1);
1619 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1620 assert(const_offset
&& "vc4 doesn't support indirect inputs");
1621 if (c
->stage
== QSTAGE_FRAG
&&
1622 nir_intrinsic_base(instr
) >= VC4_NIR_TLB_COLOR_READ_INPUT
) {
1623 assert(const_offset
->u32
[0] == 0);
1624 /* Reads of the per-sample color need to be done in
1627 int sample_index
= (nir_intrinsic_base(instr
) -
1628 VC4_NIR_TLB_COLOR_READ_INPUT
);
1629 for (int i
= 0; i
<= sample_index
; i
++) {
1630 if (c
->color_reads
[i
].file
== QFILE_NULL
) {
1632 qir_TLB_COLOR_READ(c
);
1635 ntq_store_dest(c
, &instr
->dest
, 0,
1636 c
->color_reads
[sample_index
]);
1638 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1639 int comp
= nir_intrinsic_component(instr
);
1640 ntq_store_dest(c
, &instr
->dest
, 0,
1641 c
->inputs
[offset
* 4 + comp
]);
1645 case nir_intrinsic_store_output
:
1646 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1647 assert(const_offset
&& "vc4 doesn't support indirect outputs");
1648 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1650 /* MSAA color outputs are the only case where we have an
1651 * output that's not lowered to being a store of a single 32
1654 if (c
->stage
== QSTAGE_FRAG
&& instr
->num_components
== 4) {
1655 assert(offset
== c
->output_color_index
);
1656 for (int i
= 0; i
< 4; i
++) {
1657 c
->sample_colors
[i
] =
1658 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0],
1662 offset
= offset
* 4 + nir_intrinsic_component(instr
);
1663 assert(instr
->num_components
== 1);
1664 c
->outputs
[offset
] =
1665 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0], 0));
1666 c
->num_outputs
= MAX2(c
->num_outputs
, offset
+ 1);
1670 case nir_intrinsic_discard
:
1671 c
->discard
= qir_uniform_ui(c
, ~0);
1674 case nir_intrinsic_discard_if
:
1675 if (c
->discard
.file
== QFILE_NULL
)
1676 c
->discard
= qir_uniform_ui(c
, 0);
1677 c
->discard
= qir_OR(c
, c
->discard
,
1678 ntq_get_src(c
, instr
->src
[0], 0));
1682 fprintf(stderr
, "Unknown intrinsic: ");
1683 nir_print_instr(&instr
->instr
, stderr
);
1684 fprintf(stderr
, "\n");
1689 /* Clears (activates) the execute flags for any channels whose jump target
1690 * matches this block.
1693 ntq_activate_execute_for_block(struct vc4_compile
*c
)
1695 qir_SF(c
, qir_SUB(c
,
1697 qir_uniform_ui(c
, c
->cur_block
->index
)));
1698 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
, qir_uniform_ui(c
, 0));
1702 ntq_emit_if(struct vc4_compile
*c
, nir_if
*if_stmt
)
1704 if (!c
->vc4
->screen
->has_control_flow
) {
1706 "IF statement support requires updated kernel.\n");
1710 nir_cf_node
*nir_first_else_node
= nir_if_first_else_node(if_stmt
);
1711 nir_cf_node
*nir_last_else_node
= nir_if_last_else_node(if_stmt
);
1712 nir_block
*nir_else_block
= nir_cf_node_as_block(nir_first_else_node
);
1713 bool empty_else_block
=
1714 (nir_first_else_node
== nir_last_else_node
&&
1715 exec_list_is_empty(&nir_else_block
->instr_list
));
1717 struct qblock
*then_block
= qir_new_block(c
);
1718 struct qblock
*after_block
= qir_new_block(c
);
1719 struct qblock
*else_block
;
1720 if (empty_else_block
)
1721 else_block
= after_block
;
1723 else_block
= qir_new_block(c
);
1725 bool was_top_level
= false;
1726 if (c
->execute
.file
== QFILE_NULL
) {
1727 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1728 was_top_level
= true;
1731 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1732 * 0) channels, and then update execute flags for those to point to
1737 ntq_get_src(c
, if_stmt
->condition
, 0)));
1738 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1739 qir_uniform_ui(c
, else_block
->index
));
1741 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1744 qir_SF(c
, c
->execute
);
1745 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZC
);
1746 qir_link_blocks(c
->cur_block
, else_block
);
1747 qir_link_blocks(c
->cur_block
, then_block
);
1749 /* Process the THEN block. */
1750 qir_set_emit_block(c
, then_block
);
1751 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1753 if (!empty_else_block
) {
1754 /* Handle the end of the THEN block. First, all currently
1755 * active channels update their execute flags to point to
1758 qir_SF(c
, c
->execute
);
1759 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1760 qir_uniform_ui(c
, after_block
->index
));
1762 /* If everything points at ENDIF, then jump there immediately. */
1763 qir_SF(c
, qir_SUB(c
, c
->execute
, qir_uniform_ui(c
, after_block
->index
)));
1764 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZS
);
1765 qir_link_blocks(c
->cur_block
, after_block
);
1766 qir_link_blocks(c
->cur_block
, else_block
);
1768 qir_set_emit_block(c
, else_block
);
1769 ntq_activate_execute_for_block(c
);
1770 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1773 qir_link_blocks(c
->cur_block
, after_block
);
1775 qir_set_emit_block(c
, after_block
);
1777 c
->execute
= c
->undef
;
1779 ntq_activate_execute_for_block(c
);
1784 ntq_emit_jump(struct vc4_compile
*c
, nir_jump_instr
*jump
)
1786 switch (jump
->type
) {
1787 case nir_jump_break
:
1788 qir_SF(c
, c
->execute
);
1789 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1790 qir_uniform_ui(c
, c
->loop_break_block
->index
));
1793 case nir_jump_continue
:
1794 qir_SF(c
, c
->execute
);
1795 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1796 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1799 case nir_jump_return
:
1800 unreachable("All returns shouold be lowered\n");
1805 ntq_emit_instr(struct vc4_compile
*c
, nir_instr
*instr
)
1807 switch (instr
->type
) {
1808 case nir_instr_type_alu
:
1809 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1812 case nir_instr_type_intrinsic
:
1813 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1816 case nir_instr_type_load_const
:
1817 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1820 case nir_instr_type_ssa_undef
:
1821 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1824 case nir_instr_type_tex
:
1825 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1828 case nir_instr_type_jump
:
1829 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1833 fprintf(stderr
, "Unknown NIR instr type: ");
1834 nir_print_instr(instr
, stderr
);
1835 fprintf(stderr
, "\n");
1841 ntq_emit_block(struct vc4_compile
*c
, nir_block
*block
)
1843 nir_foreach_instr(instr
, block
) {
1844 ntq_emit_instr(c
, instr
);
1848 static void ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
1851 ntq_emit_loop(struct vc4_compile
*c
, nir_loop
*loop
)
1853 if (!c
->vc4
->screen
->has_control_flow
) {
1855 "loop support requires updated kernel.\n");
1856 ntq_emit_cf_list(c
, &loop
->body
);
1860 bool was_top_level
= false;
1861 if (c
->execute
.file
== QFILE_NULL
) {
1862 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1863 was_top_level
= true;
1866 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
1867 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
1869 c
->loop_cont_block
= qir_new_block(c
);
1870 c
->loop_break_block
= qir_new_block(c
);
1872 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1873 qir_set_emit_block(c
, c
->loop_cont_block
);
1874 ntq_activate_execute_for_block(c
);
1876 ntq_emit_cf_list(c
, &loop
->body
);
1878 /* If anything had explicitly continued, or is here at the end of the
1879 * loop, then we need to loop again. SF updates are masked by the
1880 * instruction's condition, so we can do the OR of the two conditions
1883 qir_SF(c
, c
->execute
);
1884 struct qinst
*cont_check
=
1888 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1889 cont_check
->cond
= QPU_COND_ZC
;
1890 cont_check
->sf
= true;
1892 qir_BRANCH(c
, QPU_COND_BRANCH_ANY_ZS
);
1893 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1894 qir_link_blocks(c
->cur_block
, c
->loop_break_block
);
1896 qir_set_emit_block(c
, c
->loop_break_block
);
1898 c
->execute
= c
->undef
;
1900 ntq_activate_execute_for_block(c
);
1902 c
->loop_break_block
= save_loop_break_block
;
1903 c
->loop_cont_block
= save_loop_cont_block
;
1907 ntq_emit_function(struct vc4_compile
*c
, nir_function_impl
*func
)
1909 fprintf(stderr
, "FUNCTIONS not handled.\n");
1914 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
)
1916 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1917 switch (node
->type
) {
1918 case nir_cf_node_block
:
1919 ntq_emit_block(c
, nir_cf_node_as_block(node
));
1922 case nir_cf_node_if
:
1923 ntq_emit_if(c
, nir_cf_node_as_if(node
));
1926 case nir_cf_node_loop
:
1927 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
1930 case nir_cf_node_function
:
1931 ntq_emit_function(c
, nir_cf_node_as_function(node
));
1935 fprintf(stderr
, "Unknown NIR node type\n");
1942 ntq_emit_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
1944 ntq_setup_registers(c
, &impl
->registers
);
1945 ntq_emit_cf_list(c
, &impl
->body
);
1949 nir_to_qir(struct vc4_compile
*c
)
1951 ntq_setup_inputs(c
);
1952 ntq_setup_outputs(c
);
1953 ntq_setup_uniforms(c
);
1954 ntq_setup_registers(c
, &c
->s
->registers
);
1956 /* Find the main function and emit the body. */
1957 nir_foreach_function(function
, c
->s
) {
1958 assert(strcmp(function
->name
, "main") == 0);
1959 assert(function
->impl
);
1960 ntq_emit_impl(c
, function
->impl
);
1964 static const nir_shader_compiler_options nir_options
= {
1965 .lower_extract_byte
= true,
1966 .lower_extract_word
= true,
1968 .lower_flrp32
= true,
1971 .lower_fsqrt
= true,
1972 .lower_negate
= true,
1976 count_nir_instrs(nir_shader
*nir
)
1979 nir_foreach_function(function
, nir
) {
1980 if (!function
->impl
)
1982 nir_foreach_block(block
, function
->impl
) {
1983 nir_foreach_instr(instr
, block
)
1990 static struct vc4_compile
*
1991 vc4_shader_ntq(struct vc4_context
*vc4
, enum qstage stage
,
1992 struct vc4_key
*key
)
1994 struct vc4_compile
*c
= qir_compile_init();
1998 c
->shader_state
= &key
->shader_state
->base
;
1999 c
->program_id
= key
->shader_state
->program_id
;
2001 p_atomic_inc_return(&key
->shader_state
->compiled_variant_count
);
2006 c
->fs_key
= (struct vc4_fs_key
*)key
;
2007 if (c
->fs_key
->is_points
) {
2008 c
->point_x
= emit_fragment_varying(c
, ~0, 0);
2009 c
->point_y
= emit_fragment_varying(c
, ~0, 0);
2010 } else if (c
->fs_key
->is_lines
) {
2011 c
->line_x
= emit_fragment_varying(c
, ~0, 0);
2015 c
->vs_key
= (struct vc4_vs_key
*)key
;
2018 c
->vs_key
= (struct vc4_vs_key
*)key
;
2022 c
->s
= nir_shader_clone(c
, key
->shader_state
->base
.ir
.nir
);
2024 if (stage
== QSTAGE_FRAG
)
2025 NIR_PASS_V(c
->s
, vc4_nir_lower_blend
, c
);
2027 struct nir_lower_tex_options tex_options
= {
2028 /* We would need to implement txs, but we don't want the
2029 * int/float conversions
2031 .lower_rect
= false,
2035 /* Apply swizzles to all samplers. */
2036 .swizzle_result
= ~0,
2039 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2040 * The format swizzling applies before sRGB decode, and
2041 * ARB_texture_swizzle is the last thing before returning the sample.
2043 for (int i
= 0; i
< ARRAY_SIZE(key
->tex
); i
++) {
2044 enum pipe_format format
= c
->key
->tex
[i
].format
;
2049 const uint8_t *format_swizzle
= vc4_get_format_swizzle(format
);
2051 for (int j
= 0; j
< 4; j
++) {
2052 uint8_t arb_swiz
= c
->key
->tex
[i
].swizzle
[j
];
2054 if (arb_swiz
<= 3) {
2055 tex_options
.swizzles
[i
][j
] =
2056 format_swizzle
[arb_swiz
];
2058 tex_options
.swizzles
[i
][j
] = arb_swiz
;
2062 if (util_format_is_srgb(format
))
2063 tex_options
.lower_srgb
|= (1 << i
);
2066 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
2068 if (c
->fs_key
&& c
->fs_key
->light_twoside
)
2069 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
2071 if (c
->vs_key
&& c
->vs_key
->clamp_color
)
2072 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
2074 if (c
->key
->ucp_enables
) {
2075 if (stage
== QSTAGE_FRAG
) {
2076 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
);
2078 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
);
2079 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
2080 nir_var_shader_out
);
2084 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2085 * which only handles a vec4 at a time. Similarly, VS output
2086 * scalarizing must happen after nir_lower_clip_vs.
2088 if (c
->stage
== QSTAGE_FRAG
)
2089 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
2091 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
2093 NIR_PASS_V(c
->s
, vc4_nir_lower_io
, c
);
2094 NIR_PASS_V(c
->s
, vc4_nir_lower_txf_ms
, c
);
2095 NIR_PASS_V(c
->s
, nir_lower_idiv
);
2097 vc4_optimize_nir(c
->s
);
2099 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
2101 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2102 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2103 qir_get_stage_name(c
->stage
),
2104 c
->program_id
, c
->variant_id
,
2105 count_nir_instrs(c
->s
));
2108 if (vc4_debug
& VC4_DEBUG_NIR
) {
2109 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2110 qir_get_stage_name(c
->stage
),
2111 c
->program_id
, c
->variant_id
);
2112 nir_print_shader(c
->s
, stderr
);
2123 c
->vs_key
->fs_inputs
->input_slots
,
2124 c
->vs_key
->fs_inputs
->num_inputs
);
2131 if (vc4_debug
& VC4_DEBUG_QIR
) {
2132 fprintf(stderr
, "%s prog %d/%d pre-opt QIR:\n",
2133 qir_get_stage_name(c
->stage
),
2134 c
->program_id
, c
->variant_id
);
2136 fprintf(stderr
, "\n");
2140 qir_lower_uniforms(c
);
2142 qir_schedule_instructions(c
);
2143 qir_emit_uniform_stream_resets(c
);
2145 if (vc4_debug
& VC4_DEBUG_QIR
) {
2146 fprintf(stderr
, "%s prog %d/%d QIR:\n",
2147 qir_get_stage_name(c
->stage
),
2148 c
->program_id
, c
->variant_id
);
2150 fprintf(stderr
, "\n");
2153 qir_reorder_uniforms(c
);
2154 vc4_generate_code(vc4
, c
);
2156 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2157 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2158 qir_get_stage_name(c
->stage
),
2159 c
->program_id
, c
->variant_id
,
2161 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2162 qir_get_stage_name(c
->stage
),
2163 c
->program_id
, c
->variant_id
,
2173 vc4_shader_state_create(struct pipe_context
*pctx
,
2174 const struct pipe_shader_state
*cso
)
2176 struct vc4_context
*vc4
= vc4_context(pctx
);
2177 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
2181 so
->program_id
= vc4
->next_uncompiled_program_id
++;
2183 if (vc4_debug
& VC4_DEBUG_TGSI
) {
2184 fprintf(stderr
, "prog %d TGSI:\n",
2186 tgsi_dump(cso
->tokens
, 0);
2187 fprintf(stderr
, "\n");
2190 nir_shader
*s
= tgsi_to_nir(cso
->tokens
, &nir_options
);
2192 NIR_PASS_V(s
, nir_opt_global_to_local
);
2193 NIR_PASS_V(s
, nir_convert_to_ssa
);
2194 NIR_PASS_V(s
, nir_normalize_cubemap_coords
);
2196 NIR_PASS_V(s
, nir_lower_load_const_to_scalar
);
2198 vc4_optimize_nir(s
);
2200 NIR_PASS_V(s
, nir_remove_dead_variables
, nir_var_local
);
2202 /* Garbage collect dead instructions */
2205 so
->base
.type
= PIPE_SHADER_IR_NIR
;
2206 so
->base
.ir
.nir
= s
;
2208 if (vc4_debug
& VC4_DEBUG_NIR
) {
2209 fprintf(stderr
, "%s prog %d NIR:\n",
2210 gl_shader_stage_name(s
->stage
),
2212 nir_print_shader(s
, stderr
);
2213 fprintf(stderr
, "\n");
2220 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
2221 struct vc4_compile
*c
)
2223 int count
= c
->num_uniforms
;
2224 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
2226 uinfo
->count
= count
;
2227 uinfo
->data
= ralloc_array(shader
, uint32_t, count
);
2228 memcpy(uinfo
->data
, c
->uniform_data
,
2229 count
* sizeof(*uinfo
->data
));
2230 uinfo
->contents
= ralloc_array(shader
, enum quniform_contents
, count
);
2231 memcpy(uinfo
->contents
, c
->uniform_contents
,
2232 count
* sizeof(*uinfo
->contents
));
2233 uinfo
->num_texture_samples
= c
->num_texture_samples
;
2235 vc4_set_shader_uniform_dirty_flags(shader
);
2239 vc4_setup_compiled_fs_inputs(struct vc4_context
*vc4
, struct vc4_compile
*c
,
2240 struct vc4_compiled_shader
*shader
)
2242 struct vc4_fs_inputs inputs
;
2244 memset(&inputs
, 0, sizeof(inputs
));
2245 inputs
.input_slots
= ralloc_array(shader
,
2246 struct vc4_varying_slot
,
2247 c
->num_input_slots
);
2249 bool input_live
[c
->num_input_slots
];
2251 memset(input_live
, 0, sizeof(input_live
));
2252 qir_for_each_inst_inorder(inst
, c
) {
2253 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
2254 if (inst
->src
[i
].file
== QFILE_VARY
)
2255 input_live
[inst
->src
[i
].index
] = true;
2259 for (int i
= 0; i
< c
->num_input_slots
; i
++) {
2260 struct vc4_varying_slot
*slot
= &c
->input_slots
[i
];
2265 /* Skip non-VS-output inputs. */
2266 if (slot
->slot
== (uint8_t)~0)
2269 if (slot
->slot
== VARYING_SLOT_COL0
||
2270 slot
->slot
== VARYING_SLOT_COL1
||
2271 slot
->slot
== VARYING_SLOT_BFC0
||
2272 slot
->slot
== VARYING_SLOT_BFC1
) {
2273 shader
->color_inputs
|= (1 << inputs
.num_inputs
);
2276 inputs
.input_slots
[inputs
.num_inputs
] = *slot
;
2277 inputs
.num_inputs
++;
2279 shader
->num_inputs
= inputs
.num_inputs
;
2281 /* Add our set of inputs to the set of all inputs seen. This way, we
2282 * can have a single pointer that identifies an FS inputs set,
2283 * allowing VS to avoid recompiling when the FS is recompiled (or a
2284 * new one is bound using separate shader objects) but the inputs
2287 struct set_entry
*entry
= _mesa_set_search(vc4
->fs_inputs_set
, &inputs
);
2289 shader
->fs_inputs
= entry
->key
;
2290 ralloc_free(inputs
.input_slots
);
2292 struct vc4_fs_inputs
*alloc_inputs
;
2294 alloc_inputs
= rzalloc(vc4
->fs_inputs_set
, struct vc4_fs_inputs
);
2295 memcpy(alloc_inputs
, &inputs
, sizeof(inputs
));
2296 ralloc_steal(alloc_inputs
, inputs
.input_slots
);
2297 _mesa_set_add(vc4
->fs_inputs_set
, alloc_inputs
);
2299 shader
->fs_inputs
= alloc_inputs
;
2303 static struct vc4_compiled_shader
*
2304 vc4_get_compiled_shader(struct vc4_context
*vc4
, enum qstage stage
,
2305 struct vc4_key
*key
)
2307 struct hash_table
*ht
;
2309 if (stage
== QSTAGE_FRAG
) {
2311 key_size
= sizeof(struct vc4_fs_key
);
2314 key_size
= sizeof(struct vc4_vs_key
);
2317 struct vc4_compiled_shader
*shader
;
2318 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
2322 struct vc4_compile
*c
= vc4_shader_ntq(vc4
, stage
, key
);
2323 shader
= rzalloc(NULL
, struct vc4_compiled_shader
);
2325 shader
->program_id
= vc4
->next_compiled_program_id
++;
2326 if (stage
== QSTAGE_FRAG
) {
2327 vc4_setup_compiled_fs_inputs(vc4
, c
, shader
);
2329 /* Note: the temporary clone in c->s has been freed. */
2330 nir_shader
*orig_shader
= key
->shader_state
->base
.ir
.nir
;
2331 if (orig_shader
->info
.outputs_written
& (1 << FRAG_RESULT_DEPTH
))
2332 shader
->disable_early_z
= true;
2334 shader
->num_inputs
= c
->num_inputs
;
2336 shader
->vattr_offsets
[0] = 0;
2337 for (int i
= 0; i
< 8; i
++) {
2338 shader
->vattr_offsets
[i
+ 1] =
2339 shader
->vattr_offsets
[i
] + c
->vattr_sizes
[i
];
2341 if (c
->vattr_sizes
[i
])
2342 shader
->vattrs_live
|= (1 << i
);
2346 copy_uniform_state_to_shader(shader
, c
);
2347 shader
->bo
= vc4_bo_alloc_shader(vc4
->screen
, c
->qpu_insts
,
2348 c
->qpu_inst_count
* sizeof(uint64_t));
2350 /* Copy the compiler UBO range state to the compiled shader, dropping
2351 * out arrays that were never referenced by an indirect load.
2353 * (Note that QIR dead code elimination of an array access still
2354 * leaves that array alive, though)
2356 if (c
->num_ubo_ranges
) {
2357 shader
->num_ubo_ranges
= c
->num_ubo_ranges
;
2358 shader
->ubo_ranges
= ralloc_array(shader
, struct vc4_ubo_range
,
2361 for (int i
= 0; i
< c
->num_uniform_ranges
; i
++) {
2362 struct vc4_compiler_ubo_range
*range
=
2367 shader
->ubo_ranges
[j
].dst_offset
= range
->dst_offset
;
2368 shader
->ubo_ranges
[j
].src_offset
= range
->src_offset
;
2369 shader
->ubo_ranges
[j
].size
= range
->size
;
2370 shader
->ubo_size
+= c
->ubo_ranges
[i
].size
;
2374 if (shader
->ubo_size
) {
2375 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2376 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2377 qir_get_stage_name(c
->stage
),
2378 c
->program_id
, c
->variant_id
,
2379 shader
->ubo_size
/ 4);
2383 qir_compile_destroy(c
);
2385 struct vc4_key
*dup_key
;
2386 dup_key
= ralloc_size(shader
, key_size
);
2387 memcpy(dup_key
, key
, key_size
);
2388 _mesa_hash_table_insert(ht
, dup_key
, shader
);
2394 vc4_setup_shared_key(struct vc4_context
*vc4
, struct vc4_key
*key
,
2395 struct vc4_texture_stateobj
*texstate
)
2397 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
2398 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
2399 struct vc4_sampler_view
*vc4_sampler
= vc4_sampler_view(sampler
);
2400 struct pipe_sampler_state
*sampler_state
=
2401 texstate
->samplers
[i
];
2406 key
->tex
[i
].format
= sampler
->format
;
2407 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
2408 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
2409 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
2410 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
2412 if (sampler
->texture
->nr_samples
> 1) {
2413 key
->tex
[i
].msaa_width
= sampler
->texture
->width0
;
2414 key
->tex
[i
].msaa_height
= sampler
->texture
->height0
;
2415 } else if (sampler
){
2416 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
2417 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
2418 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
2419 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
2420 key
->tex
[i
].force_first_level
=
2421 vc4_sampler
->force_first_level
;
2425 key
->ucp_enables
= vc4
->rasterizer
->base
.clip_plane_enable
;
2429 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2431 struct vc4_fs_key local_key
;
2432 struct vc4_fs_key
*key
= &local_key
;
2434 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2436 VC4_DIRTY_FRAMEBUFFER
|
2438 VC4_DIRTY_RASTERIZER
|
2439 VC4_DIRTY_SAMPLE_MASK
|
2441 VC4_DIRTY_UNCOMPILED_FS
))) {
2445 memset(key
, 0, sizeof(*key
));
2446 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->fragtex
);
2447 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
2448 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
2449 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
2450 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
2451 key
->blend
= vc4
->blend
->rt
[0];
2452 if (vc4
->blend
->logicop_enable
) {
2453 key
->logicop_func
= vc4
->blend
->logicop_func
;
2455 key
->logicop_func
= PIPE_LOGICOP_COPY
;
2458 key
->msaa
= vc4
->rasterizer
->base
.multisample
;
2459 key
->sample_coverage
= (vc4
->rasterizer
->base
.multisample
&&
2460 vc4
->sample_mask
!= (1 << VC4_MAX_SAMPLES
) - 1);
2461 key
->sample_alpha_to_coverage
= vc4
->blend
->alpha_to_coverage
;
2462 key
->sample_alpha_to_one
= vc4
->blend
->alpha_to_one
;
2465 if (vc4
->framebuffer
.cbufs
[0])
2466 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
2468 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
2469 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
2470 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
2471 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
2472 key
->stencil_enabled
);
2473 if (vc4
->zsa
->base
.alpha
.enabled
) {
2474 key
->alpha_test
= true;
2475 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
2478 if (key
->is_points
) {
2479 key
->point_sprite_mask
=
2480 vc4
->rasterizer
->base
.sprite_coord_enable
;
2481 key
->point_coord_upper_left
=
2482 (vc4
->rasterizer
->base
.sprite_coord_mode
==
2483 PIPE_SPRITE_COORD_UPPER_LEFT
);
2486 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
2488 struct vc4_compiled_shader
*old_fs
= vc4
->prog
.fs
;
2489 vc4
->prog
.fs
= vc4_get_compiled_shader(vc4
, QSTAGE_FRAG
, &key
->base
);
2490 if (vc4
->prog
.fs
== old_fs
)
2493 vc4
->dirty
|= VC4_DIRTY_COMPILED_FS
;
2495 if (vc4
->rasterizer
->base
.flatshade
&&
2496 old_fs
&& vc4
->prog
.fs
->color_inputs
!= old_fs
->color_inputs
) {
2497 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
2500 if (old_fs
&& vc4
->prog
.fs
->fs_inputs
!= old_fs
->fs_inputs
)
2501 vc4
->dirty
|= VC4_DIRTY_FS_INPUTS
;
2505 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2507 struct vc4_vs_key local_key
;
2508 struct vc4_vs_key
*key
= &local_key
;
2510 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2511 VC4_DIRTY_RASTERIZER
|
2513 VC4_DIRTY_VTXSTATE
|
2514 VC4_DIRTY_UNCOMPILED_VS
|
2515 VC4_DIRTY_FS_INPUTS
))) {
2519 memset(key
, 0, sizeof(*key
));
2520 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->verttex
);
2521 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
2522 key
->fs_inputs
= vc4
->prog
.fs
->fs_inputs
;
2523 key
->clamp_color
= vc4
->rasterizer
->base
.clamp_vertex_color
;
2525 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
2526 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
2528 key
->per_vertex_point_size
=
2529 (prim_mode
== PIPE_PRIM_POINTS
&&
2530 vc4
->rasterizer
->base
.point_size_per_vertex
);
2532 struct vc4_compiled_shader
*vs
=
2533 vc4_get_compiled_shader(vc4
, QSTAGE_VERT
, &key
->base
);
2534 if (vs
!= vc4
->prog
.vs
) {
2536 vc4
->dirty
|= VC4_DIRTY_COMPILED_VS
;
2539 key
->is_coord
= true;
2540 /* Coord shaders don't care what the FS inputs are. */
2541 key
->fs_inputs
= NULL
;
2542 struct vc4_compiled_shader
*cs
=
2543 vc4_get_compiled_shader(vc4
, QSTAGE_COORD
, &key
->base
);
2544 if (cs
!= vc4
->prog
.cs
) {
2546 vc4
->dirty
|= VC4_DIRTY_COMPILED_CS
;
2551 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
2553 vc4_update_compiled_fs(vc4
, prim_mode
);
2554 vc4_update_compiled_vs(vc4
, prim_mode
);
2558 fs_cache_hash(const void *key
)
2560 return _mesa_hash_data(key
, sizeof(struct vc4_fs_key
));
2564 vs_cache_hash(const void *key
)
2566 return _mesa_hash_data(key
, sizeof(struct vc4_vs_key
));
2570 fs_cache_compare(const void *key1
, const void *key2
)
2572 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
)) == 0;
2576 vs_cache_compare(const void *key1
, const void *key2
)
2578 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
)) == 0;
2582 fs_inputs_hash(const void *key
)
2584 const struct vc4_fs_inputs
*inputs
= key
;
2586 return _mesa_hash_data(inputs
->input_slots
,
2587 sizeof(*inputs
->input_slots
) *
2588 inputs
->num_inputs
);
2592 fs_inputs_compare(const void *key1
, const void *key2
)
2594 const struct vc4_fs_inputs
*inputs1
= key1
;
2595 const struct vc4_fs_inputs
*inputs2
= key2
;
2597 return (inputs1
->num_inputs
== inputs2
->num_inputs
&&
2598 memcmp(inputs1
->input_slots
,
2599 inputs2
->input_slots
,
2600 sizeof(*inputs1
->input_slots
) *
2601 inputs1
->num_inputs
) == 0);
2605 delete_from_cache_if_matches(struct hash_table
*ht
,
2606 struct hash_entry
*entry
,
2607 struct vc4_uncompiled_shader
*so
)
2609 const struct vc4_key
*key
= entry
->key
;
2611 if (key
->shader_state
== so
) {
2612 struct vc4_compiled_shader
*shader
= entry
->data
;
2613 _mesa_hash_table_remove(ht
, entry
);
2614 vc4_bo_unreference(&shader
->bo
);
2615 ralloc_free(shader
);
2620 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
2622 struct vc4_context
*vc4
= vc4_context(pctx
);
2623 struct vc4_uncompiled_shader
*so
= hwcso
;
2625 struct hash_entry
*entry
;
2626 hash_table_foreach(vc4
->fs_cache
, entry
)
2627 delete_from_cache_if_matches(vc4
->fs_cache
, entry
, so
);
2628 hash_table_foreach(vc4
->vs_cache
, entry
)
2629 delete_from_cache_if_matches(vc4
->vs_cache
, entry
, so
);
2631 ralloc_free(so
->base
.ir
.nir
);
2636 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2638 struct vc4_context
*vc4
= vc4_context(pctx
);
2639 vc4
->prog
.bind_fs
= hwcso
;
2640 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_FS
;
2644 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2646 struct vc4_context
*vc4
= vc4_context(pctx
);
2647 vc4
->prog
.bind_vs
= hwcso
;
2648 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_VS
;
2652 vc4_program_init(struct pipe_context
*pctx
)
2654 struct vc4_context
*vc4
= vc4_context(pctx
);
2656 pctx
->create_vs_state
= vc4_shader_state_create
;
2657 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2659 pctx
->create_fs_state
= vc4_shader_state_create
;
2660 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2662 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2663 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2665 vc4
->fs_cache
= _mesa_hash_table_create(pctx
, fs_cache_hash
,
2667 vc4
->vs_cache
= _mesa_hash_table_create(pctx
, vs_cache_hash
,
2669 vc4
->fs_inputs_set
= _mesa_set_create(pctx
, fs_inputs_hash
,
2674 vc4_program_fini(struct pipe_context
*pctx
)
2676 struct vc4_context
*vc4
= vc4_context(pctx
);
2678 struct hash_entry
*entry
;
2679 hash_table_foreach(vc4
->fs_cache
, entry
) {
2680 struct vc4_compiled_shader
*shader
= entry
->data
;
2681 vc4_bo_unreference(&shader
->bo
);
2682 ralloc_free(shader
);
2683 _mesa_hash_table_remove(vc4
->fs_cache
, entry
);
2686 hash_table_foreach(vc4
->vs_cache
, entry
) {
2687 struct vc4_compiled_shader
*shader
= entry
->data
;
2688 vc4_bo_unreference(&shader
->bo
);
2689 ralloc_free(shader
);
2690 _mesa_hash_table_remove(vc4
->vs_cache
, entry
);