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vc4: Use proper type sizes for uniforms.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
38 #include "vc4_qpu.h"
39 #include "vc4_qir.h"
40 #include "mesa/state_tracker/st_glsl_types.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 static struct qreg
46 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
47 static void
48 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
49
50 static void
51 resize_qreg_array(struct vc4_compile *c,
52 struct qreg **regs,
53 uint32_t *size,
54 uint32_t decl_size)
55 {
56 if (*size >= decl_size)
57 return;
58
59 uint32_t old_size = *size;
60 *size = MAX2(*size * 2, decl_size);
61 *regs = reralloc(c, *regs, struct qreg, *size);
62 if (!*regs) {
63 fprintf(stderr, "Malloc failure\n");
64 abort();
65 }
66
67 for (uint32_t i = old_size; i < *size; i++)
68 (*regs)[i] = c->undef;
69 }
70
71 static struct qreg
72 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
73 {
74 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
75 uint32_t offset = nir_intrinsic_base(intr);
76 struct vc4_compiler_ubo_range *range = NULL;
77 unsigned i;
78 for (i = 0; i < c->num_uniform_ranges; i++) {
79 range = &c->ubo_ranges[i];
80 if (offset >= range->src_offset &&
81 offset < range->src_offset + range->size) {
82 break;
83 }
84 }
85 /* The driver-location-based offset always has to be within a declared
86 * uniform range.
87 */
88 assert(range);
89 if (!range->used) {
90 range->used = true;
91 range->dst_offset = c->next_ubo_dst_offset;
92 c->next_ubo_dst_offset += range->size;
93 c->num_ubo_ranges++;
94 }
95
96 offset -= range->src_offset;
97
98 /* Adjust for where we stored the TGSI register base. */
99 indirect_offset = qir_ADD(c, indirect_offset,
100 qir_uniform_ui(c, (range->dst_offset +
101 offset)));
102
103 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
104 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
105 indirect_offset = qir_MIN(c, indirect_offset,
106 qir_uniform_ui(c, (range->dst_offset +
107 range->size - 4)));
108
109 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
110 c->num_texture_samples++;
111 return qir_TEX_RESULT(c);
112 }
113
114 nir_ssa_def *
115 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
116 {
117 switch (swiz) {
118 default:
119 case PIPE_SWIZZLE_NONE:
120 fprintf(stderr, "warning: unknown swizzle\n");
121 /* FALLTHROUGH */
122 case PIPE_SWIZZLE_0:
123 return nir_imm_float(b, 0.0);
124 case PIPE_SWIZZLE_1:
125 return nir_imm_float(b, 1.0);
126 case PIPE_SWIZZLE_X:
127 case PIPE_SWIZZLE_Y:
128 case PIPE_SWIZZLE_Z:
129 case PIPE_SWIZZLE_W:
130 return srcs[swiz];
131 }
132 }
133
134 static struct qreg *
135 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
136 {
137 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
138 def->num_components);
139 _mesa_hash_table_insert(c->def_ht, def, qregs);
140 return qregs;
141 }
142
143 static void
144 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
145 struct qreg result)
146 {
147 if (dest->is_ssa) {
148 assert(chan < dest->ssa.num_components);
149
150 struct qreg *qregs;
151 struct hash_entry *entry =
152 _mesa_hash_table_search(c->def_ht, &dest->ssa);
153
154 if (entry)
155 qregs = entry->data;
156 else
157 qregs = ntq_init_ssa_def(c, &dest->ssa);
158
159 qregs[chan] = result;
160 } else {
161 nir_register *reg = dest->reg.reg;
162 assert(dest->reg.base_offset == 0);
163 assert(reg->num_array_elems == 0);
164 struct hash_entry *entry =
165 _mesa_hash_table_search(c->def_ht, reg);
166 struct qreg *qregs = entry->data;
167
168 /* Conditionally move the result to the destination if the
169 * channel is active.
170 */
171 if (c->execute.file != QFILE_NULL) {
172 qir_SF(c, c->execute);
173 qir_MOV_cond(c, QPU_COND_ZS, qregs[chan], result);
174 } else {
175 qir_MOV_dest(c, qregs[chan], result);
176 }
177 }
178 }
179
180 static struct qreg *
181 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
182 {
183 if (dest->is_ssa) {
184 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
185 for (int i = 0; i < dest->ssa.num_components; i++)
186 qregs[i] = c->undef;
187 return qregs;
188 } else {
189 nir_register *reg = dest->reg.reg;
190 assert(dest->reg.base_offset == 0);
191 assert(reg->num_array_elems == 0);
192 struct hash_entry *entry =
193 _mesa_hash_table_search(c->def_ht, reg);
194 return entry->data;
195 }
196 }
197
198 static struct qreg
199 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
200 {
201 struct hash_entry *entry;
202 if (src.is_ssa) {
203 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
204 assert(i < src.ssa->num_components);
205 } else {
206 nir_register *reg = src.reg.reg;
207 entry = _mesa_hash_table_search(c->def_ht, reg);
208 assert(reg->num_array_elems == 0);
209 assert(src.reg.base_offset == 0);
210 assert(i < reg->num_components);
211 }
212
213 struct qreg *qregs = entry->data;
214 return qregs[i];
215 }
216
217 static struct qreg
218 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
219 unsigned src)
220 {
221 assert(util_is_power_of_two(instr->dest.write_mask));
222 unsigned chan = ffs(instr->dest.write_mask) - 1;
223 struct qreg r = ntq_get_src(c, instr->src[src].src,
224 instr->src[src].swizzle[chan]);
225
226 assert(!instr->src[src].abs);
227 assert(!instr->src[src].negate);
228
229 return r;
230 };
231
232 static inline struct qreg
233 qir_SAT(struct vc4_compile *c, struct qreg val)
234 {
235 return qir_FMAX(c,
236 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
237 qir_uniform_f(c, 0.0));
238 }
239
240 static struct qreg
241 ntq_rcp(struct vc4_compile *c, struct qreg x)
242 {
243 struct qreg r = qir_RCP(c, x);
244
245 /* Apply a Newton-Raphson step to improve the accuracy. */
246 r = qir_FMUL(c, r, qir_FSUB(c,
247 qir_uniform_f(c, 2.0),
248 qir_FMUL(c, x, r)));
249
250 return r;
251 }
252
253 static struct qreg
254 ntq_rsq(struct vc4_compile *c, struct qreg x)
255 {
256 struct qreg r = qir_RSQ(c, x);
257
258 /* Apply a Newton-Raphson step to improve the accuracy. */
259 r = qir_FMUL(c, r, qir_FSUB(c,
260 qir_uniform_f(c, 1.5),
261 qir_FMUL(c,
262 qir_uniform_f(c, 0.5),
263 qir_FMUL(c, x,
264 qir_FMUL(c, r, r)))));
265
266 return r;
267 }
268
269 static struct qreg
270 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
271 {
272 struct qreg src0_hi = qir_SHR(c, src0,
273 qir_uniform_ui(c, 24));
274 struct qreg src1_hi = qir_SHR(c, src1,
275 qir_uniform_ui(c, 24));
276
277 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
278 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
279 struct qreg lolo = qir_MUL24(c, src0, src1);
280
281 return qir_ADD(c, lolo, qir_SHL(c,
282 qir_ADD(c, hilo, lohi),
283 qir_uniform_ui(c, 24)));
284 }
285
286 static struct qreg
287 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
288 {
289 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
290 qir_uniform_ui(c, 8)));
291 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
292 }
293
294 /**
295 * Emits a lowered TXF_MS from an MSAA texture.
296 *
297 * The addressing math has been lowered in NIR, and now we just need to read
298 * it like a UBO.
299 */
300 static void
301 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
302 {
303 uint32_t tile_width = 32;
304 uint32_t tile_height = 32;
305 uint32_t tile_size = (tile_height * tile_width *
306 VC4_MAX_SAMPLES * sizeof(uint32_t));
307
308 unsigned unit = instr->texture_index;
309 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
310 uint32_t w_tiles = w / tile_width;
311 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
312 uint32_t h_tiles = h / tile_height;
313 uint32_t size = w_tiles * h_tiles * tile_size;
314
315 struct qreg addr;
316 assert(instr->num_srcs == 1);
317 assert(instr->src[0].src_type == nir_tex_src_coord);
318 addr = ntq_get_src(c, instr->src[0].src, 0);
319
320 /* Perform the clamping required by kernel validation. */
321 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
322 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
323
324 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
325
326 struct qreg tex = qir_TEX_RESULT(c);
327 c->num_texture_samples++;
328
329 struct qreg dest[4];
330 enum pipe_format format = c->key->tex[unit].format;
331 if (util_format_is_depth_or_stencil(format)) {
332 struct qreg scaled = ntq_scale_depth_texture(c, tex);
333 for (int i = 0; i < 4; i++)
334 dest[i] = scaled;
335 } else {
336 for (int i = 0; i < 4; i++)
337 dest[i] = qir_UNPACK_8_F(c, tex, i);
338 }
339
340 for (int i = 0; i < 4; i++)
341 ntq_store_dest(c, &instr->dest, i, dest[i]);
342 }
343
344 static void
345 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
346 {
347 struct qreg s, t, r, lod, compare;
348 bool is_txb = false, is_txl = false;
349 unsigned unit = instr->texture_index;
350
351 if (instr->op == nir_texop_txf) {
352 ntq_emit_txf(c, instr);
353 return;
354 }
355
356 for (unsigned i = 0; i < instr->num_srcs; i++) {
357 switch (instr->src[i].src_type) {
358 case nir_tex_src_coord:
359 s = ntq_get_src(c, instr->src[i].src, 0);
360 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
361 t = qir_uniform_f(c, 0.5);
362 else
363 t = ntq_get_src(c, instr->src[i].src, 1);
364 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
365 r = ntq_get_src(c, instr->src[i].src, 2);
366 break;
367 case nir_tex_src_bias:
368 lod = ntq_get_src(c, instr->src[i].src, 0);
369 is_txb = true;
370 break;
371 case nir_tex_src_lod:
372 lod = ntq_get_src(c, instr->src[i].src, 0);
373 is_txl = true;
374 break;
375 case nir_tex_src_comparitor:
376 compare = ntq_get_src(c, instr->src[i].src, 0);
377 break;
378 default:
379 unreachable("unknown texture source");
380 }
381 }
382
383 if (c->key->tex[unit].force_first_level) {
384 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
385 is_txl = true;
386 is_txb = false;
387 }
388
389 struct qreg texture_u[] = {
390 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
391 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
392 qir_uniform(c, QUNIFORM_CONSTANT, 0),
393 qir_uniform(c, QUNIFORM_CONSTANT, 0),
394 };
395 uint32_t next_texture_u = 0;
396
397 /* There is no native support for GL texture rectangle coordinates, so
398 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
399 * 1]).
400 */
401 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
402 s = qir_FMUL(c, s,
403 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
404 t = qir_FMUL(c, t,
405 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
406 }
407
408 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
409 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
410 unit | (is_txl << 16));
411 }
412
413 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
414 qir_TEX_R(c, r, texture_u[next_texture_u++]);
415 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
416 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
417 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
418 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
419 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
420 texture_u[next_texture_u++]);
421 }
422
423 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
424 s = qir_SAT(c, s);
425 }
426
427 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
428 t = qir_SAT(c, t);
429 }
430
431 qir_TEX_T(c, t, texture_u[next_texture_u++]);
432
433 if (is_txl || is_txb)
434 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
435
436 qir_TEX_S(c, s, texture_u[next_texture_u++]);
437
438 c->num_texture_samples++;
439 struct qreg tex = qir_TEX_RESULT(c);
440
441 enum pipe_format format = c->key->tex[unit].format;
442
443 struct qreg *dest = ntq_get_dest(c, &instr->dest);
444 if (util_format_is_depth_or_stencil(format)) {
445 struct qreg normalized = ntq_scale_depth_texture(c, tex);
446 struct qreg depth_output;
447
448 struct qreg u0 = qir_uniform_f(c, 0.0f);
449 struct qreg u1 = qir_uniform_f(c, 1.0f);
450 if (c->key->tex[unit].compare_mode) {
451 switch (c->key->tex[unit].compare_func) {
452 case PIPE_FUNC_NEVER:
453 depth_output = qir_uniform_f(c, 0.0f);
454 break;
455 case PIPE_FUNC_ALWAYS:
456 depth_output = u1;
457 break;
458 case PIPE_FUNC_EQUAL:
459 qir_SF(c, qir_FSUB(c, compare, normalized));
460 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
461 break;
462 case PIPE_FUNC_NOTEQUAL:
463 qir_SF(c, qir_FSUB(c, compare, normalized));
464 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
465 break;
466 case PIPE_FUNC_GREATER:
467 qir_SF(c, qir_FSUB(c, compare, normalized));
468 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
469 break;
470 case PIPE_FUNC_GEQUAL:
471 qir_SF(c, qir_FSUB(c, normalized, compare));
472 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
473 break;
474 case PIPE_FUNC_LESS:
475 qir_SF(c, qir_FSUB(c, compare, normalized));
476 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
477 break;
478 case PIPE_FUNC_LEQUAL:
479 qir_SF(c, qir_FSUB(c, normalized, compare));
480 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
481 break;
482 }
483 } else {
484 depth_output = normalized;
485 }
486
487 for (int i = 0; i < 4; i++)
488 dest[i] = depth_output;
489 } else {
490 for (int i = 0; i < 4; i++)
491 dest[i] = qir_UNPACK_8_F(c, tex, i);
492 }
493 }
494
495 /**
496 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
497 * to zero).
498 */
499 static struct qreg
500 ntq_ffract(struct vc4_compile *c, struct qreg src)
501 {
502 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
503 struct qreg diff = qir_FSUB(c, src, trunc);
504 qir_SF(c, diff);
505 return qir_SEL(c, QPU_COND_NS,
506 qir_FADD(c, diff, qir_uniform_f(c, 1.0)), diff);
507 }
508
509 /**
510 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
511 * zero).
512 */
513 static struct qreg
514 ntq_ffloor(struct vc4_compile *c, struct qreg src)
515 {
516 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
517
518 /* This will be < 0 if we truncated and the truncation was of a value
519 * that was < 0 in the first place.
520 */
521 qir_SF(c, qir_FSUB(c, src, trunc));
522
523 return qir_SEL(c, QPU_COND_NS,
524 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)), trunc);
525 }
526
527 /**
528 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
529 * zero).
530 */
531 static struct qreg
532 ntq_fceil(struct vc4_compile *c, struct qreg src)
533 {
534 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
535
536 /* This will be < 0 if we truncated and the truncation was of a value
537 * that was > 0 in the first place.
538 */
539 qir_SF(c, qir_FSUB(c, trunc, src));
540
541 return qir_SEL(c, QPU_COND_NS,
542 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)), trunc);
543 }
544
545 static struct qreg
546 ntq_fsin(struct vc4_compile *c, struct qreg src)
547 {
548 float coeff[] = {
549 -2.0 * M_PI,
550 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
551 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
552 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
553 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
554 };
555
556 struct qreg scaled_x =
557 qir_FMUL(c,
558 src,
559 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
560
561 struct qreg x = qir_FADD(c,
562 ntq_ffract(c, scaled_x),
563 qir_uniform_f(c, -0.5));
564 struct qreg x2 = qir_FMUL(c, x, x);
565 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
566 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
567 x = qir_FMUL(c, x, x2);
568 sum = qir_FADD(c,
569 sum,
570 qir_FMUL(c,
571 x,
572 qir_uniform_f(c, coeff[i])));
573 }
574 return sum;
575 }
576
577 static struct qreg
578 ntq_fcos(struct vc4_compile *c, struct qreg src)
579 {
580 float coeff[] = {
581 -1.0f,
582 pow(2.0 * M_PI, 2) / (2 * 1),
583 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
584 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
585 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
586 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
587 };
588
589 struct qreg scaled_x =
590 qir_FMUL(c, src,
591 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
592 struct qreg x_frac = qir_FADD(c,
593 ntq_ffract(c, scaled_x),
594 qir_uniform_f(c, -0.5));
595
596 struct qreg sum = qir_uniform_f(c, coeff[0]);
597 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
598 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
599 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
600 if (i != 1)
601 x = qir_FMUL(c, x, x2);
602
603 struct qreg mul = qir_FMUL(c,
604 x,
605 qir_uniform_f(c, coeff[i]));
606 if (i == 0)
607 sum = mul;
608 else
609 sum = qir_FADD(c, sum, mul);
610 }
611 return sum;
612 }
613
614 static struct qreg
615 ntq_fsign(struct vc4_compile *c, struct qreg src)
616 {
617 struct qreg t = qir_get_temp(c);
618
619 qir_SF(c, src);
620 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
621 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
622 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
623 return t;
624 }
625
626 static void
627 emit_vertex_input(struct vc4_compile *c, int attr)
628 {
629 enum pipe_format format = c->vs_key->attr_formats[attr];
630 uint32_t attr_size = util_format_get_blocksize(format);
631
632 c->vattr_sizes[attr] = align(attr_size, 4);
633 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
634 c->inputs[attr * 4 + i] =
635 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
636 c->num_inputs++;
637 }
638 }
639
640 static void
641 emit_fragcoord_input(struct vc4_compile *c, int attr)
642 {
643 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
644 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
645 c->inputs[attr * 4 + 2] =
646 qir_FMUL(c,
647 qir_ITOF(c, qir_FRAG_Z(c)),
648 qir_uniform_f(c, 1.0 / 0xffffff));
649 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
650 }
651
652 static struct qreg
653 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
654 uint8_t swizzle)
655 {
656 uint32_t i = c->num_input_slots++;
657 struct qreg vary = {
658 QFILE_VARY,
659 i
660 };
661
662 if (c->num_input_slots >= c->input_slots_array_size) {
663 c->input_slots_array_size =
664 MAX2(4, c->input_slots_array_size * 2);
665
666 c->input_slots = reralloc(c, c->input_slots,
667 struct vc4_varying_slot,
668 c->input_slots_array_size);
669 }
670
671 c->input_slots[i].slot = slot;
672 c->input_slots[i].swizzle = swizzle;
673
674 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
675 }
676
677 static void
678 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
679 {
680 for (int i = 0; i < 4; i++) {
681 c->inputs[attr * 4 + i] =
682 emit_fragment_varying(c, slot, i);
683 c->num_inputs++;
684 }
685 }
686
687 static void
688 add_output(struct vc4_compile *c,
689 uint32_t decl_offset,
690 uint8_t slot,
691 uint8_t swizzle)
692 {
693 uint32_t old_array_size = c->outputs_array_size;
694 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
695 decl_offset + 1);
696
697 if (old_array_size != c->outputs_array_size) {
698 c->output_slots = reralloc(c,
699 c->output_slots,
700 struct vc4_varying_slot,
701 c->outputs_array_size);
702 }
703
704 c->output_slots[decl_offset].slot = slot;
705 c->output_slots[decl_offset].swizzle = swizzle;
706 }
707
708 static void
709 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
710 {
711 unsigned array_id = c->num_uniform_ranges++;
712 if (array_id >= c->ubo_ranges_array_size) {
713 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
714 array_id + 1);
715 c->ubo_ranges = reralloc(c, c->ubo_ranges,
716 struct vc4_compiler_ubo_range,
717 c->ubo_ranges_array_size);
718 }
719
720 c->ubo_ranges[array_id].dst_offset = 0;
721 c->ubo_ranges[array_id].src_offset = start;
722 c->ubo_ranges[array_id].size = size;
723 c->ubo_ranges[array_id].used = false;
724 }
725
726 static bool
727 ntq_src_is_only_ssa_def_user(nir_src *src)
728 {
729 if (!src->is_ssa)
730 return false;
731
732 if (!list_empty(&src->ssa->if_uses))
733 return false;
734
735 return (src->ssa->uses.next == &src->use_link &&
736 src->ssa->uses.next->next == &src->ssa->uses);
737 }
738
739 /**
740 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
741 * bit set.
742 *
743 * However, as an optimization, it tries to find the instructions generating
744 * the sources to be packed and just emit the pack flag there, if possible.
745 */
746 static void
747 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
748 {
749 struct qreg result = qir_get_temp(c);
750 struct nir_alu_instr *vec4 = NULL;
751
752 /* If packing from a vec4 op (as expected), identify it so that we can
753 * peek back at what generated its sources.
754 */
755 if (instr->src[0].src.is_ssa &&
756 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
757 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
758 nir_op_vec4) {
759 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
760 }
761
762 /* If the pack is replicating the same channel 4 times, use the 8888
763 * pack flag. This is common for blending using the alpha
764 * channel.
765 */
766 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
767 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
768 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
769 struct qreg rep = ntq_get_src(c,
770 instr->src[0].src,
771 instr->src[0].swizzle[0]);
772 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
773 return;
774 }
775
776 for (int i = 0; i < 4; i++) {
777 int swiz = instr->src[0].swizzle[i];
778 struct qreg src;
779 if (vec4) {
780 src = ntq_get_src(c, vec4->src[swiz].src,
781 vec4->src[swiz].swizzle[0]);
782 } else {
783 src = ntq_get_src(c, instr->src[0].src, swiz);
784 }
785
786 if (vec4 &&
787 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
788 src.file == QFILE_TEMP &&
789 c->defs[src.index] &&
790 qir_is_mul(c->defs[src.index]) &&
791 !c->defs[src.index]->dst.pack) {
792 struct qinst *rewrite = c->defs[src.index];
793 c->defs[src.index] = NULL;
794 rewrite->dst = result;
795 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
796 continue;
797 }
798
799 qir_PACK_8_F(c, result, src, i);
800 }
801
802 ntq_store_dest(c, &instr->dest.dest, 0, result);
803 }
804
805 /** Handles sign-extended bitfield extracts for 16 bits. */
806 static struct qreg
807 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
808 struct qreg bits)
809 {
810 assert(bits.file == QFILE_UNIF &&
811 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
812 c->uniform_data[bits.index] == 16);
813
814 assert(offset.file == QFILE_UNIF &&
815 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
816 int offset_bit = c->uniform_data[offset.index];
817 assert(offset_bit % 16 == 0);
818
819 return qir_UNPACK_16_I(c, base, offset_bit / 16);
820 }
821
822 /** Handles unsigned bitfield extracts for 8 bits. */
823 static struct qreg
824 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
825 struct qreg bits)
826 {
827 assert(bits.file == QFILE_UNIF &&
828 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
829 c->uniform_data[bits.index] == 8);
830
831 assert(offset.file == QFILE_UNIF &&
832 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
833 int offset_bit = c->uniform_data[offset.index];
834 assert(offset_bit % 8 == 0);
835
836 return qir_UNPACK_8_I(c, base, offset_bit / 8);
837 }
838
839 /**
840 * If compare_instr is a valid comparison instruction, emits the
841 * compare_instr's comparison and returns the sel_instr's return value based
842 * on the compare_instr's result.
843 */
844 static bool
845 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
846 nir_alu_instr *compare_instr,
847 nir_alu_instr *sel_instr)
848 {
849 enum qpu_cond cond;
850
851 switch (compare_instr->op) {
852 case nir_op_feq:
853 case nir_op_ieq:
854 case nir_op_seq:
855 cond = QPU_COND_ZS;
856 break;
857 case nir_op_fne:
858 case nir_op_ine:
859 case nir_op_sne:
860 cond = QPU_COND_ZC;
861 break;
862 case nir_op_fge:
863 case nir_op_ige:
864 case nir_op_uge:
865 case nir_op_sge:
866 cond = QPU_COND_NC;
867 break;
868 case nir_op_flt:
869 case nir_op_ilt:
870 case nir_op_slt:
871 cond = QPU_COND_NS;
872 break;
873 default:
874 return false;
875 }
876
877 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
878 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
879
880 unsigned unsized_type =
881 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
882 if (unsized_type == nir_type_float)
883 qir_SF(c, qir_FSUB(c, src0, src1));
884 else
885 qir_SF(c, qir_SUB(c, src0, src1));
886
887 switch (sel_instr->op) {
888 case nir_op_seq:
889 case nir_op_sne:
890 case nir_op_sge:
891 case nir_op_slt:
892 *dest = qir_SEL(c, cond,
893 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
894 break;
895
896 case nir_op_bcsel:
897 *dest = qir_SEL(c, cond,
898 ntq_get_alu_src(c, sel_instr, 1),
899 ntq_get_alu_src(c, sel_instr, 2));
900 break;
901
902 default:
903 *dest = qir_SEL(c, cond,
904 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
905 break;
906 }
907
908 return true;
909 }
910
911 /**
912 * Attempts to fold a comparison generating a boolean result into the
913 * condition code for selecting between two values, instead of comparing the
914 * boolean result against 0 to generate the condition code.
915 */
916 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
917 struct qreg *src)
918 {
919 if (!instr->src[0].src.is_ssa)
920 goto out;
921 nir_alu_instr *compare =
922 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
923 if (!compare)
924 goto out;
925
926 struct qreg dest;
927 if (ntq_emit_comparison(c, &dest, compare, instr))
928 return dest;
929
930 out:
931 qir_SF(c, src[0]);
932 return qir_SEL(c, QPU_COND_NS, src[1], src[2]);
933 }
934
935 static void
936 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
937 {
938 /* This should always be lowered to ALU operations for VC4. */
939 assert(!instr->dest.saturate);
940
941 /* Vectors are special in that they have non-scalarized writemasks,
942 * and just take the first swizzle channel for each argument in order
943 * into each writemask channel.
944 */
945 if (instr->op == nir_op_vec2 ||
946 instr->op == nir_op_vec3 ||
947 instr->op == nir_op_vec4) {
948 struct qreg srcs[4];
949 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
950 srcs[i] = ntq_get_src(c, instr->src[i].src,
951 instr->src[i].swizzle[0]);
952 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
953 ntq_store_dest(c, &instr->dest.dest, i, srcs[i]);
954 return;
955 }
956
957 if (instr->op == nir_op_pack_unorm_4x8) {
958 ntq_emit_pack_unorm_4x8(c, instr);
959 return;
960 }
961
962 if (instr->op == nir_op_unpack_unorm_4x8) {
963 struct qreg src = ntq_get_src(c, instr->src[0].src,
964 instr->src[0].swizzle[0]);
965 for (int i = 0; i < 4; i++) {
966 if (instr->dest.write_mask & (1 << i))
967 ntq_store_dest(c, &instr->dest.dest, i,
968 qir_UNPACK_8_F(c, src, i));
969 }
970 return;
971 }
972
973 /* General case: We can just grab the one used channel per src. */
974 struct qreg src[nir_op_infos[instr->op].num_inputs];
975 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
976 src[i] = ntq_get_alu_src(c, instr, i);
977 }
978
979 struct qreg result;
980
981 switch (instr->op) {
982 case nir_op_fmov:
983 case nir_op_imov:
984 result = qir_MOV(c, src[0]);
985 break;
986 case nir_op_fmul:
987 result = qir_FMUL(c, src[0], src[1]);
988 break;
989 case nir_op_fadd:
990 result = qir_FADD(c, src[0], src[1]);
991 break;
992 case nir_op_fsub:
993 result = qir_FSUB(c, src[0], src[1]);
994 break;
995 case nir_op_fmin:
996 result = qir_FMIN(c, src[0], src[1]);
997 break;
998 case nir_op_fmax:
999 result = qir_FMAX(c, src[0], src[1]);
1000 break;
1001
1002 case nir_op_f2i:
1003 case nir_op_f2u:
1004 result = qir_FTOI(c, src[0]);
1005 break;
1006 case nir_op_i2f:
1007 case nir_op_u2f:
1008 result = qir_ITOF(c, src[0]);
1009 break;
1010 case nir_op_b2f:
1011 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1012 break;
1013 case nir_op_b2i:
1014 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1015 break;
1016 case nir_op_i2b:
1017 case nir_op_f2b:
1018 qir_SF(c, src[0]);
1019 result = qir_SEL(c, QPU_COND_ZC,
1020 qir_uniform_ui(c, ~0),
1021 qir_uniform_ui(c, 0));
1022 break;
1023
1024 case nir_op_iadd:
1025 result = qir_ADD(c, src[0], src[1]);
1026 break;
1027 case nir_op_ushr:
1028 result = qir_SHR(c, src[0], src[1]);
1029 break;
1030 case nir_op_isub:
1031 result = qir_SUB(c, src[0], src[1]);
1032 break;
1033 case nir_op_ishr:
1034 result = qir_ASR(c, src[0], src[1]);
1035 break;
1036 case nir_op_ishl:
1037 result = qir_SHL(c, src[0], src[1]);
1038 break;
1039 case nir_op_imin:
1040 result = qir_MIN(c, src[0], src[1]);
1041 break;
1042 case nir_op_imax:
1043 result = qir_MAX(c, src[0], src[1]);
1044 break;
1045 case nir_op_iand:
1046 result = qir_AND(c, src[0], src[1]);
1047 break;
1048 case nir_op_ior:
1049 result = qir_OR(c, src[0], src[1]);
1050 break;
1051 case nir_op_ixor:
1052 result = qir_XOR(c, src[0], src[1]);
1053 break;
1054 case nir_op_inot:
1055 result = qir_NOT(c, src[0]);
1056 break;
1057
1058 case nir_op_imul:
1059 result = ntq_umul(c, src[0], src[1]);
1060 break;
1061
1062 case nir_op_seq:
1063 case nir_op_sne:
1064 case nir_op_sge:
1065 case nir_op_slt:
1066 case nir_op_feq:
1067 case nir_op_fne:
1068 case nir_op_fge:
1069 case nir_op_flt:
1070 case nir_op_ieq:
1071 case nir_op_ine:
1072 case nir_op_ige:
1073 case nir_op_uge:
1074 case nir_op_ilt:
1075 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1076 fprintf(stderr, "Bad comparison instruction\n");
1077 }
1078 break;
1079
1080 case nir_op_bcsel:
1081 result = ntq_emit_bcsel(c, instr, src);
1082 break;
1083 case nir_op_fcsel:
1084 qir_SF(c, src[0]);
1085 result = qir_SEL(c, QPU_COND_ZC, src[1], src[2]);
1086 break;
1087
1088 case nir_op_frcp:
1089 result = ntq_rcp(c, src[0]);
1090 break;
1091 case nir_op_frsq:
1092 result = ntq_rsq(c, src[0]);
1093 break;
1094 case nir_op_fexp2:
1095 result = qir_EXP2(c, src[0]);
1096 break;
1097 case nir_op_flog2:
1098 result = qir_LOG2(c, src[0]);
1099 break;
1100
1101 case nir_op_ftrunc:
1102 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1103 break;
1104 case nir_op_fceil:
1105 result = ntq_fceil(c, src[0]);
1106 break;
1107 case nir_op_ffract:
1108 result = ntq_ffract(c, src[0]);
1109 break;
1110 case nir_op_ffloor:
1111 result = ntq_ffloor(c, src[0]);
1112 break;
1113
1114 case nir_op_fsin:
1115 result = ntq_fsin(c, src[0]);
1116 break;
1117 case nir_op_fcos:
1118 result = ntq_fcos(c, src[0]);
1119 break;
1120
1121 case nir_op_fsign:
1122 result = ntq_fsign(c, src[0]);
1123 break;
1124
1125 case nir_op_fabs:
1126 result = qir_FMAXABS(c, src[0], src[0]);
1127 break;
1128 case nir_op_iabs:
1129 result = qir_MAX(c, src[0],
1130 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1131 break;
1132
1133 case nir_op_ibitfield_extract:
1134 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1135 break;
1136
1137 case nir_op_ubitfield_extract:
1138 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1139 break;
1140
1141 case nir_op_usadd_4x8:
1142 result = qir_V8ADDS(c, src[0], src[1]);
1143 break;
1144
1145 case nir_op_ussub_4x8:
1146 result = qir_V8SUBS(c, src[0], src[1]);
1147 break;
1148
1149 case nir_op_umin_4x8:
1150 result = qir_V8MIN(c, src[0], src[1]);
1151 break;
1152
1153 case nir_op_umax_4x8:
1154 result = qir_V8MAX(c, src[0], src[1]);
1155 break;
1156
1157 case nir_op_umul_unorm_4x8:
1158 result = qir_V8MULD(c, src[0], src[1]);
1159 break;
1160
1161 default:
1162 fprintf(stderr, "unknown NIR ALU inst: ");
1163 nir_print_instr(&instr->instr, stderr);
1164 fprintf(stderr, "\n");
1165 abort();
1166 }
1167
1168 /* We have a scalar result, so the instruction should only have a
1169 * single channel written to.
1170 */
1171 assert(util_is_power_of_two(instr->dest.write_mask));
1172 ntq_store_dest(c, &instr->dest.dest,
1173 ffs(instr->dest.write_mask) - 1, result);
1174 }
1175
1176 static void
1177 emit_frag_end(struct vc4_compile *c)
1178 {
1179 struct qreg color;
1180 if (c->output_color_index != -1) {
1181 color = c->outputs[c->output_color_index];
1182 } else {
1183 color = qir_uniform_ui(c, 0);
1184 }
1185
1186 uint32_t discard_cond = QPU_COND_ALWAYS;
1187 if (c->discard.file != QFILE_NULL) {
1188 qir_SF(c, c->discard);
1189 discard_cond = QPU_COND_ZS;
1190 }
1191
1192 if (c->fs_key->stencil_enabled) {
1193 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1194 qir_uniform(c, QUNIFORM_STENCIL, 0));
1195 if (c->fs_key->stencil_twoside) {
1196 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1197 qir_uniform(c, QUNIFORM_STENCIL, 1));
1198 }
1199 if (c->fs_key->stencil_full_writemasks) {
1200 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1201 qir_uniform(c, QUNIFORM_STENCIL, 2));
1202 }
1203 }
1204
1205 if (c->output_sample_mask_index != -1) {
1206 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1207 }
1208
1209 if (c->fs_key->depth_enabled) {
1210 if (c->output_position_index != -1) {
1211 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1212 qir_FMUL(c,
1213 c->outputs[c->output_position_index],
1214 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1215 } else {
1216 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1217 qir_FRAG_Z(c))->cond = discard_cond;
1218 }
1219 }
1220
1221 if (!c->msaa_per_sample_output) {
1222 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1223 color)->cond = discard_cond;
1224 } else {
1225 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1226 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1227 c->sample_colors[i])->cond = discard_cond;
1228 }
1229 }
1230 }
1231
1232 static void
1233 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1234 {
1235 struct qreg packed = qir_get_temp(c);
1236
1237 for (int i = 0; i < 2; i++) {
1238 struct qreg scale =
1239 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1240
1241 struct qreg packed_chan = packed;
1242 packed_chan.pack = QPU_PACK_A_16A + i;
1243
1244 qir_FTOI_dest(c, packed_chan,
1245 qir_FMUL(c,
1246 qir_FMUL(c,
1247 c->outputs[c->output_position_index + i],
1248 scale),
1249 rcp_w));
1250 }
1251
1252 qir_VPM_WRITE(c, packed);
1253 }
1254
1255 static void
1256 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1257 {
1258 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1259 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1260
1261 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1262 c->outputs[c->output_position_index + 2],
1263 zscale),
1264 rcp_w),
1265 zoffset));
1266 }
1267
1268 static void
1269 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1270 {
1271 qir_VPM_WRITE(c, rcp_w);
1272 }
1273
1274 static void
1275 emit_point_size_write(struct vc4_compile *c)
1276 {
1277 struct qreg point_size;
1278
1279 if (c->output_point_size_index != -1)
1280 point_size = c->outputs[c->output_point_size_index];
1281 else
1282 point_size = qir_uniform_f(c, 1.0);
1283
1284 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1285 * BCM21553).
1286 */
1287 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1288
1289 qir_VPM_WRITE(c, point_size);
1290 }
1291
1292 /**
1293 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1294 *
1295 * The simulator insists that there be at least one vertex attribute, so
1296 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1297 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1298 * to consume it here.
1299 */
1300 static void
1301 emit_stub_vpm_read(struct vc4_compile *c)
1302 {
1303 if (c->num_inputs)
1304 return;
1305
1306 c->vattr_sizes[0] = 4;
1307 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1308 c->num_inputs++;
1309 }
1310
1311 static void
1312 emit_vert_end(struct vc4_compile *c,
1313 struct vc4_varying_slot *fs_inputs,
1314 uint32_t num_fs_inputs)
1315 {
1316 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1317
1318 emit_stub_vpm_read(c);
1319
1320 emit_scaled_viewport_write(c, rcp_w);
1321 emit_zs_write(c, rcp_w);
1322 emit_rcp_wc_write(c, rcp_w);
1323 if (c->vs_key->per_vertex_point_size)
1324 emit_point_size_write(c);
1325
1326 for (int i = 0; i < num_fs_inputs; i++) {
1327 struct vc4_varying_slot *input = &fs_inputs[i];
1328 int j;
1329
1330 for (j = 0; j < c->num_outputs; j++) {
1331 struct vc4_varying_slot *output =
1332 &c->output_slots[j];
1333
1334 if (input->slot == output->slot &&
1335 input->swizzle == output->swizzle) {
1336 qir_VPM_WRITE(c, c->outputs[j]);
1337 break;
1338 }
1339 }
1340 /* Emit padding if we didn't find a declared VS output for
1341 * this FS input.
1342 */
1343 if (j == c->num_outputs)
1344 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1345 }
1346 }
1347
1348 static void
1349 emit_coord_end(struct vc4_compile *c)
1350 {
1351 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1352
1353 emit_stub_vpm_read(c);
1354
1355 for (int i = 0; i < 4; i++)
1356 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1357
1358 emit_scaled_viewport_write(c, rcp_w);
1359 emit_zs_write(c, rcp_w);
1360 emit_rcp_wc_write(c, rcp_w);
1361 if (c->vs_key->per_vertex_point_size)
1362 emit_point_size_write(c);
1363 }
1364
1365 static void
1366 vc4_optimize_nir(struct nir_shader *s)
1367 {
1368 bool progress;
1369
1370 do {
1371 progress = false;
1372
1373 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1374 NIR_PASS_V(s, nir_lower_alu_to_scalar);
1375 NIR_PASS_V(s, nir_lower_phis_to_scalar);
1376
1377 NIR_PASS(progress, s, nir_copy_prop);
1378 NIR_PASS(progress, s, nir_opt_remove_phis);
1379 NIR_PASS(progress, s, nir_opt_dce);
1380 NIR_PASS(progress, s, nir_opt_dead_cf);
1381 NIR_PASS(progress, s, nir_opt_cse);
1382 NIR_PASS(progress, s, nir_opt_peephole_select);
1383 NIR_PASS(progress, s, nir_opt_algebraic);
1384 NIR_PASS(progress, s, nir_opt_constant_folding);
1385 NIR_PASS(progress, s, nir_opt_undef);
1386 } while (progress);
1387 }
1388
1389 static int
1390 driver_location_compare(const void *in_a, const void *in_b)
1391 {
1392 const nir_variable *const *a = in_a;
1393 const nir_variable *const *b = in_b;
1394
1395 return (*a)->data.driver_location - (*b)->data.driver_location;
1396 }
1397
1398 static void
1399 ntq_setup_inputs(struct vc4_compile *c)
1400 {
1401 unsigned num_entries = 0;
1402 nir_foreach_variable(var, &c->s->inputs)
1403 num_entries++;
1404
1405 nir_variable *vars[num_entries];
1406
1407 unsigned i = 0;
1408 nir_foreach_variable(var, &c->s->inputs)
1409 vars[i++] = var;
1410
1411 /* Sort the variables so that we emit the input setup in
1412 * driver_location order. This is required for VPM reads, whose data
1413 * is fetched into the VPM in driver_location (TGSI register index)
1414 * order.
1415 */
1416 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1417
1418 for (unsigned i = 0; i < num_entries; i++) {
1419 nir_variable *var = vars[i];
1420 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1421 unsigned loc = var->data.driver_location;
1422
1423 assert(array_len == 1);
1424 (void)array_len;
1425 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1426 (loc + 1) * 4);
1427
1428 if (c->stage == QSTAGE_FRAG) {
1429 if (var->data.location == VARYING_SLOT_POS) {
1430 emit_fragcoord_input(c, loc);
1431 } else if (var->data.location == VARYING_SLOT_PNTC ||
1432 (var->data.location >= VARYING_SLOT_VAR0 &&
1433 (c->fs_key->point_sprite_mask &
1434 (1 << (var->data.location -
1435 VARYING_SLOT_VAR0))))) {
1436 c->inputs[loc * 4 + 0] = c->point_x;
1437 c->inputs[loc * 4 + 1] = c->point_y;
1438 } else {
1439 emit_fragment_input(c, loc, var->data.location);
1440 }
1441 } else {
1442 emit_vertex_input(c, loc);
1443 }
1444 }
1445 }
1446
1447 static void
1448 ntq_setup_outputs(struct vc4_compile *c)
1449 {
1450 nir_foreach_variable(var, &c->s->outputs) {
1451 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1452 unsigned loc = var->data.driver_location * 4;
1453
1454 assert(array_len == 1);
1455 (void)array_len;
1456
1457 for (int i = 0; i < 4; i++)
1458 add_output(c, loc + i, var->data.location, i);
1459
1460 if (c->stage == QSTAGE_FRAG) {
1461 switch (var->data.location) {
1462 case FRAG_RESULT_COLOR:
1463 case FRAG_RESULT_DATA0:
1464 c->output_color_index = loc;
1465 break;
1466 case FRAG_RESULT_DEPTH:
1467 c->output_position_index = loc;
1468 break;
1469 case FRAG_RESULT_SAMPLE_MASK:
1470 c->output_sample_mask_index = loc;
1471 break;
1472 }
1473 } else {
1474 switch (var->data.location) {
1475 case VARYING_SLOT_POS:
1476 c->output_position_index = loc;
1477 break;
1478 case VARYING_SLOT_PSIZ:
1479 c->output_point_size_index = loc;
1480 break;
1481 }
1482 }
1483 }
1484 }
1485
1486 static void
1487 ntq_setup_uniforms(struct vc4_compile *c)
1488 {
1489 nir_foreach_variable(var, &c->s->uniforms) {
1490 uint32_t vec4_count = st_glsl_type_size(var->type);
1491 unsigned vec4_size = 4 * sizeof(float);
1492
1493 declare_uniform_range(c, var->data.driver_location * vec4_size,
1494 vec4_count * vec4_size);
1495
1496 }
1497 }
1498
1499 /**
1500 * Sets up the mapping from nir_register to struct qreg *.
1501 *
1502 * Each nir_register gets a struct qreg per 32-bit component being stored.
1503 */
1504 static void
1505 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1506 {
1507 foreach_list_typed(nir_register, nir_reg, node, list) {
1508 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1509 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1510 array_len *
1511 nir_reg->num_components);
1512
1513 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1514
1515 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1516 qregs[i] = qir_get_temp(c);
1517 }
1518 }
1519
1520 static void
1521 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1522 {
1523 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1524 for (int i = 0; i < instr->def.num_components; i++)
1525 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1526
1527 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1528 }
1529
1530 static void
1531 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1532 {
1533 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1534
1535 /* QIR needs there to be *some* value, so pick 0 (same as for
1536 * ntq_setup_registers().
1537 */
1538 for (int i = 0; i < instr->def.num_components; i++)
1539 qregs[i] = qir_uniform_ui(c, 0);
1540 }
1541
1542 static void
1543 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1544 {
1545 nir_const_value *const_offset;
1546 unsigned offset;
1547
1548 switch (instr->intrinsic) {
1549 case nir_intrinsic_load_uniform:
1550 assert(instr->num_components == 1);
1551 const_offset = nir_src_as_const_value(instr->src[0]);
1552 if (const_offset) {
1553 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1554 assert(offset % 4 == 0);
1555 /* We need dwords */
1556 offset = offset / 4;
1557 ntq_store_dest(c, &instr->dest, 0,
1558 qir_uniform(c, QUNIFORM_UNIFORM,
1559 offset));
1560 } else {
1561 ntq_store_dest(c, &instr->dest, 0,
1562 indirect_uniform_load(c, instr));
1563 }
1564 break;
1565
1566 case nir_intrinsic_load_user_clip_plane:
1567 for (int i = 0; i < instr->num_components; i++) {
1568 ntq_store_dest(c, &instr->dest, i,
1569 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1570 nir_intrinsic_ucp_id(instr) *
1571 4 + i));
1572 }
1573 break;
1574
1575 case nir_intrinsic_load_blend_const_color_r_float:
1576 case nir_intrinsic_load_blend_const_color_g_float:
1577 case nir_intrinsic_load_blend_const_color_b_float:
1578 case nir_intrinsic_load_blend_const_color_a_float:
1579 ntq_store_dest(c, &instr->dest, 0,
1580 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1581 (instr->intrinsic -
1582 nir_intrinsic_load_blend_const_color_r_float),
1583 0));
1584 break;
1585
1586 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1587 ntq_store_dest(c, &instr->dest, 0,
1588 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1589 0));
1590 break;
1591
1592 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1593 ntq_store_dest(c, &instr->dest, 0,
1594 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1595 0));
1596 break;
1597
1598 case nir_intrinsic_load_alpha_ref_float:
1599 ntq_store_dest(c, &instr->dest, 0,
1600 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1601 break;
1602
1603 case nir_intrinsic_load_sample_mask_in:
1604 ntq_store_dest(c, &instr->dest, 0,
1605 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1606 break;
1607
1608 case nir_intrinsic_load_front_face:
1609 /* The register contains 0 (front) or 1 (back), and we need to
1610 * turn it into a NIR bool where true means front.
1611 */
1612 ntq_store_dest(c, &instr->dest, 0,
1613 qir_ADD(c,
1614 qir_uniform_ui(c, -1),
1615 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1616 break;
1617
1618 case nir_intrinsic_load_input:
1619 assert(instr->num_components == 1);
1620 const_offset = nir_src_as_const_value(instr->src[0]);
1621 assert(const_offset && "vc4 doesn't support indirect inputs");
1622 if (c->stage == QSTAGE_FRAG &&
1623 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1624 assert(const_offset->u32[0] == 0);
1625 /* Reads of the per-sample color need to be done in
1626 * order.
1627 */
1628 int sample_index = (nir_intrinsic_base(instr) -
1629 VC4_NIR_TLB_COLOR_READ_INPUT);
1630 for (int i = 0; i <= sample_index; i++) {
1631 if (c->color_reads[i].file == QFILE_NULL) {
1632 c->color_reads[i] =
1633 qir_TLB_COLOR_READ(c);
1634 }
1635 }
1636 ntq_store_dest(c, &instr->dest, 0,
1637 c->color_reads[sample_index]);
1638 } else {
1639 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1640 int comp = nir_intrinsic_component(instr);
1641 ntq_store_dest(c, &instr->dest, 0,
1642 c->inputs[offset * 4 + comp]);
1643 }
1644 break;
1645
1646 case nir_intrinsic_store_output:
1647 const_offset = nir_src_as_const_value(instr->src[1]);
1648 assert(const_offset && "vc4 doesn't support indirect outputs");
1649 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1650
1651 /* MSAA color outputs are the only case where we have an
1652 * output that's not lowered to being a store of a single 32
1653 * bit value.
1654 */
1655 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1656 assert(offset == c->output_color_index);
1657 for (int i = 0; i < 4; i++) {
1658 c->sample_colors[i] =
1659 qir_MOV(c, ntq_get_src(c, instr->src[0],
1660 i));
1661 }
1662 } else {
1663 offset = offset * 4 + nir_intrinsic_component(instr);
1664 assert(instr->num_components == 1);
1665 c->outputs[offset] =
1666 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1667 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1668 }
1669 break;
1670
1671 case nir_intrinsic_discard:
1672 c->discard = qir_uniform_ui(c, ~0);
1673 break;
1674
1675 case nir_intrinsic_discard_if:
1676 if (c->discard.file == QFILE_NULL)
1677 c->discard = qir_uniform_ui(c, 0);
1678 c->discard = qir_OR(c, c->discard,
1679 ntq_get_src(c, instr->src[0], 0));
1680 break;
1681
1682 default:
1683 fprintf(stderr, "Unknown intrinsic: ");
1684 nir_print_instr(&instr->instr, stderr);
1685 fprintf(stderr, "\n");
1686 break;
1687 }
1688 }
1689
1690 /* Clears (activates) the execute flags for any channels whose jump target
1691 * matches this block.
1692 */
1693 static void
1694 ntq_activate_execute_for_block(struct vc4_compile *c)
1695 {
1696 qir_SF(c, qir_SUB(c,
1697 c->execute,
1698 qir_uniform_ui(c, c->cur_block->index)));
1699 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1700 }
1701
1702 static void
1703 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1704 {
1705 if (!c->vc4->screen->has_control_flow) {
1706 fprintf(stderr,
1707 "IF statement support requires updated kernel.\n");
1708 return;
1709 }
1710
1711 nir_cf_node *nir_first_else_node = nir_if_first_else_node(if_stmt);
1712 nir_cf_node *nir_last_else_node = nir_if_last_else_node(if_stmt);
1713 nir_block *nir_else_block = nir_cf_node_as_block(nir_first_else_node);
1714 bool empty_else_block =
1715 (nir_first_else_node == nir_last_else_node &&
1716 exec_list_is_empty(&nir_else_block->instr_list));
1717
1718 struct qblock *then_block = qir_new_block(c);
1719 struct qblock *after_block = qir_new_block(c);
1720 struct qblock *else_block;
1721 if (empty_else_block)
1722 else_block = after_block;
1723 else
1724 else_block = qir_new_block(c);
1725
1726 bool was_top_level = false;
1727 if (c->execute.file == QFILE_NULL) {
1728 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1729 was_top_level = true;
1730 }
1731
1732 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1733 * 0) channels, and then update execute flags for those to point to
1734 * the ELSE block.
1735 */
1736 qir_SF(c, qir_OR(c,
1737 c->execute,
1738 ntq_get_src(c, if_stmt->condition, 0)));
1739 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1740 qir_uniform_ui(c, else_block->index));
1741
1742 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1743 * through.
1744 */
1745 qir_SF(c, c->execute);
1746 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1747 qir_link_blocks(c->cur_block, else_block);
1748 qir_link_blocks(c->cur_block, then_block);
1749
1750 /* Process the THEN block. */
1751 qir_set_emit_block(c, then_block);
1752 ntq_emit_cf_list(c, &if_stmt->then_list);
1753
1754 if (!empty_else_block) {
1755 /* Handle the end of the THEN block. First, all currently
1756 * active channels update their execute flags to point to
1757 * ENDIF
1758 */
1759 qir_SF(c, c->execute);
1760 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1761 qir_uniform_ui(c, after_block->index));
1762
1763 /* If everything points at ENDIF, then jump there immediately. */
1764 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1765 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1766 qir_link_blocks(c->cur_block, after_block);
1767 qir_link_blocks(c->cur_block, else_block);
1768
1769 qir_set_emit_block(c, else_block);
1770 ntq_activate_execute_for_block(c);
1771 ntq_emit_cf_list(c, &if_stmt->else_list);
1772 }
1773
1774 qir_link_blocks(c->cur_block, after_block);
1775
1776 qir_set_emit_block(c, after_block);
1777 if (was_top_level)
1778 c->execute = c->undef;
1779 else
1780 ntq_activate_execute_for_block(c);
1781
1782 }
1783
1784 static void
1785 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1786 {
1787 switch (jump->type) {
1788 case nir_jump_break:
1789 qir_SF(c, c->execute);
1790 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1791 qir_uniform_ui(c, c->loop_break_block->index));
1792 break;
1793
1794 case nir_jump_continue:
1795 qir_SF(c, c->execute);
1796 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1797 qir_uniform_ui(c, c->loop_cont_block->index));
1798 break;
1799
1800 case nir_jump_return:
1801 unreachable("All returns shouold be lowered\n");
1802 }
1803 }
1804
1805 static void
1806 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1807 {
1808 switch (instr->type) {
1809 case nir_instr_type_alu:
1810 ntq_emit_alu(c, nir_instr_as_alu(instr));
1811 break;
1812
1813 case nir_instr_type_intrinsic:
1814 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1815 break;
1816
1817 case nir_instr_type_load_const:
1818 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1819 break;
1820
1821 case nir_instr_type_ssa_undef:
1822 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1823 break;
1824
1825 case nir_instr_type_tex:
1826 ntq_emit_tex(c, nir_instr_as_tex(instr));
1827 break;
1828
1829 case nir_instr_type_jump:
1830 ntq_emit_jump(c, nir_instr_as_jump(instr));
1831 break;
1832
1833 default:
1834 fprintf(stderr, "Unknown NIR instr type: ");
1835 nir_print_instr(instr, stderr);
1836 fprintf(stderr, "\n");
1837 abort();
1838 }
1839 }
1840
1841 static void
1842 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1843 {
1844 nir_foreach_instr(instr, block) {
1845 ntq_emit_instr(c, instr);
1846 }
1847 }
1848
1849 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
1850
1851 static void
1852 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
1853 {
1854 if (!c->vc4->screen->has_control_flow) {
1855 fprintf(stderr,
1856 "loop support requires updated kernel.\n");
1857 ntq_emit_cf_list(c, &loop->body);
1858 return;
1859 }
1860
1861 bool was_top_level = false;
1862 if (c->execute.file == QFILE_NULL) {
1863 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1864 was_top_level = true;
1865 }
1866
1867 struct qblock *save_loop_cont_block = c->loop_cont_block;
1868 struct qblock *save_loop_break_block = c->loop_break_block;
1869
1870 c->loop_cont_block = qir_new_block(c);
1871 c->loop_break_block = qir_new_block(c);
1872
1873 qir_link_blocks(c->cur_block, c->loop_cont_block);
1874 qir_set_emit_block(c, c->loop_cont_block);
1875 ntq_activate_execute_for_block(c);
1876
1877 ntq_emit_cf_list(c, &loop->body);
1878
1879 /* If anything had explicitly continued, or is here at the end of the
1880 * loop, then we need to loop again. SF updates are masked by the
1881 * instruction's condition, so we can do the OR of the two conditions
1882 * within SF.
1883 */
1884 qir_SF(c, c->execute);
1885 struct qinst *cont_check =
1886 qir_SUB_dest(c,
1887 c->undef,
1888 c->execute,
1889 qir_uniform_ui(c, c->loop_cont_block->index));
1890 cont_check->cond = QPU_COND_ZC;
1891 cont_check->sf = true;
1892
1893 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
1894 qir_link_blocks(c->cur_block, c->loop_cont_block);
1895 qir_link_blocks(c->cur_block, c->loop_break_block);
1896
1897 qir_set_emit_block(c, c->loop_break_block);
1898 if (was_top_level)
1899 c->execute = c->undef;
1900 else
1901 ntq_activate_execute_for_block(c);
1902
1903 c->loop_break_block = save_loop_break_block;
1904 c->loop_cont_block = save_loop_cont_block;
1905 }
1906
1907 static void
1908 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
1909 {
1910 fprintf(stderr, "FUNCTIONS not handled.\n");
1911 abort();
1912 }
1913
1914 static void
1915 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1916 {
1917 foreach_list_typed(nir_cf_node, node, node, list) {
1918 switch (node->type) {
1919 case nir_cf_node_block:
1920 ntq_emit_block(c, nir_cf_node_as_block(node));
1921 break;
1922
1923 case nir_cf_node_if:
1924 ntq_emit_if(c, nir_cf_node_as_if(node));
1925 break;
1926
1927 case nir_cf_node_loop:
1928 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1929 break;
1930
1931 case nir_cf_node_function:
1932 ntq_emit_function(c, nir_cf_node_as_function(node));
1933 break;
1934
1935 default:
1936 fprintf(stderr, "Unknown NIR node type\n");
1937 abort();
1938 }
1939 }
1940 }
1941
1942 static void
1943 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1944 {
1945 ntq_setup_registers(c, &impl->registers);
1946 ntq_emit_cf_list(c, &impl->body);
1947 }
1948
1949 static void
1950 nir_to_qir(struct vc4_compile *c)
1951 {
1952 ntq_setup_inputs(c);
1953 ntq_setup_outputs(c);
1954 ntq_setup_uniforms(c);
1955 ntq_setup_registers(c, &c->s->registers);
1956
1957 /* Find the main function and emit the body. */
1958 nir_foreach_function(function, c->s) {
1959 assert(strcmp(function->name, "main") == 0);
1960 assert(function->impl);
1961 ntq_emit_impl(c, function->impl);
1962 }
1963 }
1964
1965 static const nir_shader_compiler_options nir_options = {
1966 .lower_extract_byte = true,
1967 .lower_extract_word = true,
1968 .lower_ffma = true,
1969 .lower_flrp32 = true,
1970 .lower_fpow = true,
1971 .lower_fsat = true,
1972 .lower_fsqrt = true,
1973 .lower_negate = true,
1974 };
1975
1976 static int
1977 count_nir_instrs(nir_shader *nir)
1978 {
1979 int count = 0;
1980 nir_foreach_function(function, nir) {
1981 if (!function->impl)
1982 continue;
1983 nir_foreach_block(block, function->impl) {
1984 nir_foreach_instr(instr, block)
1985 count++;
1986 }
1987 }
1988 return count;
1989 }
1990
1991 static struct vc4_compile *
1992 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1993 struct vc4_key *key)
1994 {
1995 struct vc4_compile *c = qir_compile_init();
1996
1997 c->vc4 = vc4;
1998 c->stage = stage;
1999 c->shader_state = &key->shader_state->base;
2000 c->program_id = key->shader_state->program_id;
2001 c->variant_id =
2002 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2003
2004 c->key = key;
2005 switch (stage) {
2006 case QSTAGE_FRAG:
2007 c->fs_key = (struct vc4_fs_key *)key;
2008 if (c->fs_key->is_points) {
2009 c->point_x = emit_fragment_varying(c, ~0, 0);
2010 c->point_y = emit_fragment_varying(c, ~0, 0);
2011 } else if (c->fs_key->is_lines) {
2012 c->line_x = emit_fragment_varying(c, ~0, 0);
2013 }
2014 break;
2015 case QSTAGE_VERT:
2016 c->vs_key = (struct vc4_vs_key *)key;
2017 break;
2018 case QSTAGE_COORD:
2019 c->vs_key = (struct vc4_vs_key *)key;
2020 break;
2021 }
2022
2023 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2024
2025 if (stage == QSTAGE_FRAG)
2026 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2027
2028 struct nir_lower_tex_options tex_options = {
2029 /* We would need to implement txs, but we don't want the
2030 * int/float conversions
2031 */
2032 .lower_rect = false,
2033
2034 .lower_txp = ~0,
2035
2036 /* Apply swizzles to all samplers. */
2037 .swizzle_result = ~0,
2038 };
2039
2040 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2041 * The format swizzling applies before sRGB decode, and
2042 * ARB_texture_swizzle is the last thing before returning the sample.
2043 */
2044 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2045 enum pipe_format format = c->key->tex[i].format;
2046
2047 if (!format)
2048 continue;
2049
2050 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2051
2052 for (int j = 0; j < 4; j++) {
2053 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2054
2055 if (arb_swiz <= 3) {
2056 tex_options.swizzles[i][j] =
2057 format_swizzle[arb_swiz];
2058 } else {
2059 tex_options.swizzles[i][j] = arb_swiz;
2060 }
2061 }
2062
2063 if (util_format_is_srgb(format))
2064 tex_options.lower_srgb |= (1 << i);
2065 }
2066
2067 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2068
2069 if (c->fs_key && c->fs_key->light_twoside)
2070 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2071
2072 if (c->vs_key && c->vs_key->clamp_color)
2073 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2074
2075 if (c->key->ucp_enables) {
2076 if (stage == QSTAGE_FRAG) {
2077 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2078 } else {
2079 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
2080 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2081 nir_var_shader_out);
2082 }
2083 }
2084
2085 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2086 * which only handles a vec4 at a time. Similarly, VS output
2087 * scalarizing must happen after nir_lower_clip_vs.
2088 */
2089 if (c->stage == QSTAGE_FRAG)
2090 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2091 else
2092 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2093
2094 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2095 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2096 NIR_PASS_V(c->s, nir_lower_idiv);
2097
2098 vc4_optimize_nir(c->s);
2099
2100 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2101
2102 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2103 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2104 qir_get_stage_name(c->stage),
2105 c->program_id, c->variant_id,
2106 count_nir_instrs(c->s));
2107 }
2108
2109 if (vc4_debug & VC4_DEBUG_NIR) {
2110 fprintf(stderr, "%s prog %d/%d NIR:\n",
2111 qir_get_stage_name(c->stage),
2112 c->program_id, c->variant_id);
2113 nir_print_shader(c->s, stderr);
2114 }
2115
2116 nir_to_qir(c);
2117
2118 switch (stage) {
2119 case QSTAGE_FRAG:
2120 emit_frag_end(c);
2121 break;
2122 case QSTAGE_VERT:
2123 emit_vert_end(c,
2124 c->vs_key->fs_inputs->input_slots,
2125 c->vs_key->fs_inputs->num_inputs);
2126 break;
2127 case QSTAGE_COORD:
2128 emit_coord_end(c);
2129 break;
2130 }
2131
2132 if (vc4_debug & VC4_DEBUG_QIR) {
2133 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2134 qir_get_stage_name(c->stage),
2135 c->program_id, c->variant_id);
2136 qir_dump(c);
2137 fprintf(stderr, "\n");
2138 }
2139
2140 qir_optimize(c);
2141 qir_lower_uniforms(c);
2142
2143 qir_schedule_instructions(c);
2144 qir_emit_uniform_stream_resets(c);
2145
2146 if (vc4_debug & VC4_DEBUG_QIR) {
2147 fprintf(stderr, "%s prog %d/%d QIR:\n",
2148 qir_get_stage_name(c->stage),
2149 c->program_id, c->variant_id);
2150 qir_dump(c);
2151 fprintf(stderr, "\n");
2152 }
2153
2154 qir_reorder_uniforms(c);
2155 vc4_generate_code(vc4, c);
2156
2157 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2158 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2159 qir_get_stage_name(c->stage),
2160 c->program_id, c->variant_id,
2161 c->qpu_inst_count);
2162 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2163 qir_get_stage_name(c->stage),
2164 c->program_id, c->variant_id,
2165 c->num_uniforms);
2166 }
2167
2168 ralloc_free(c->s);
2169
2170 return c;
2171 }
2172
2173 static void *
2174 vc4_shader_state_create(struct pipe_context *pctx,
2175 const struct pipe_shader_state *cso)
2176 {
2177 struct vc4_context *vc4 = vc4_context(pctx);
2178 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2179 if (!so)
2180 return NULL;
2181
2182 so->program_id = vc4->next_uncompiled_program_id++;
2183
2184 if (vc4_debug & VC4_DEBUG_TGSI) {
2185 fprintf(stderr, "prog %d TGSI:\n",
2186 so->program_id);
2187 tgsi_dump(cso->tokens, 0);
2188 fprintf(stderr, "\n");
2189 }
2190
2191 nir_shader *s = tgsi_to_nir(cso->tokens, &nir_options);
2192
2193 NIR_PASS_V(s, nir_opt_global_to_local);
2194 NIR_PASS_V(s, nir_convert_to_ssa);
2195 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2196
2197 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2198
2199 vc4_optimize_nir(s);
2200
2201 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_local);
2202
2203 /* Garbage collect dead instructions */
2204 nir_sweep(s);
2205
2206 so->base.type = PIPE_SHADER_IR_NIR;
2207 so->base.ir.nir = s;
2208
2209 if (vc4_debug & VC4_DEBUG_NIR) {
2210 fprintf(stderr, "%s prog %d NIR:\n",
2211 gl_shader_stage_name(s->stage),
2212 so->program_id);
2213 nir_print_shader(s, stderr);
2214 fprintf(stderr, "\n");
2215 }
2216
2217 return so;
2218 }
2219
2220 static void
2221 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2222 struct vc4_compile *c)
2223 {
2224 int count = c->num_uniforms;
2225 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2226
2227 uinfo->count = count;
2228 uinfo->data = ralloc_array(shader, uint32_t, count);
2229 memcpy(uinfo->data, c->uniform_data,
2230 count * sizeof(*uinfo->data));
2231 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2232 memcpy(uinfo->contents, c->uniform_contents,
2233 count * sizeof(*uinfo->contents));
2234 uinfo->num_texture_samples = c->num_texture_samples;
2235
2236 vc4_set_shader_uniform_dirty_flags(shader);
2237 }
2238
2239 static void
2240 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2241 struct vc4_compiled_shader *shader)
2242 {
2243 struct vc4_fs_inputs inputs;
2244
2245 memset(&inputs, 0, sizeof(inputs));
2246 inputs.input_slots = ralloc_array(shader,
2247 struct vc4_varying_slot,
2248 c->num_input_slots);
2249
2250 bool input_live[c->num_input_slots];
2251
2252 memset(input_live, 0, sizeof(input_live));
2253 qir_for_each_inst_inorder(inst, c) {
2254 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2255 if (inst->src[i].file == QFILE_VARY)
2256 input_live[inst->src[i].index] = true;
2257 }
2258 }
2259
2260 for (int i = 0; i < c->num_input_slots; i++) {
2261 struct vc4_varying_slot *slot = &c->input_slots[i];
2262
2263 if (!input_live[i])
2264 continue;
2265
2266 /* Skip non-VS-output inputs. */
2267 if (slot->slot == (uint8_t)~0)
2268 continue;
2269
2270 if (slot->slot == VARYING_SLOT_COL0 ||
2271 slot->slot == VARYING_SLOT_COL1 ||
2272 slot->slot == VARYING_SLOT_BFC0 ||
2273 slot->slot == VARYING_SLOT_BFC1) {
2274 shader->color_inputs |= (1 << inputs.num_inputs);
2275 }
2276
2277 inputs.input_slots[inputs.num_inputs] = *slot;
2278 inputs.num_inputs++;
2279 }
2280 shader->num_inputs = inputs.num_inputs;
2281
2282 /* Add our set of inputs to the set of all inputs seen. This way, we
2283 * can have a single pointer that identifies an FS inputs set,
2284 * allowing VS to avoid recompiling when the FS is recompiled (or a
2285 * new one is bound using separate shader objects) but the inputs
2286 * don't change.
2287 */
2288 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2289 if (entry) {
2290 shader->fs_inputs = entry->key;
2291 ralloc_free(inputs.input_slots);
2292 } else {
2293 struct vc4_fs_inputs *alloc_inputs;
2294
2295 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2296 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2297 ralloc_steal(alloc_inputs, inputs.input_slots);
2298 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2299
2300 shader->fs_inputs = alloc_inputs;
2301 }
2302 }
2303
2304 static struct vc4_compiled_shader *
2305 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2306 struct vc4_key *key)
2307 {
2308 struct hash_table *ht;
2309 uint32_t key_size;
2310 if (stage == QSTAGE_FRAG) {
2311 ht = vc4->fs_cache;
2312 key_size = sizeof(struct vc4_fs_key);
2313 } else {
2314 ht = vc4->vs_cache;
2315 key_size = sizeof(struct vc4_vs_key);
2316 }
2317
2318 struct vc4_compiled_shader *shader;
2319 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2320 if (entry)
2321 return entry->data;
2322
2323 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2324 shader = rzalloc(NULL, struct vc4_compiled_shader);
2325
2326 shader->program_id = vc4->next_compiled_program_id++;
2327 if (stage == QSTAGE_FRAG) {
2328 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2329
2330 /* Note: the temporary clone in c->s has been freed. */
2331 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2332 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2333 shader->disable_early_z = true;
2334 } else {
2335 shader->num_inputs = c->num_inputs;
2336
2337 shader->vattr_offsets[0] = 0;
2338 for (int i = 0; i < 8; i++) {
2339 shader->vattr_offsets[i + 1] =
2340 shader->vattr_offsets[i] + c->vattr_sizes[i];
2341
2342 if (c->vattr_sizes[i])
2343 shader->vattrs_live |= (1 << i);
2344 }
2345 }
2346
2347 copy_uniform_state_to_shader(shader, c);
2348 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2349 c->qpu_inst_count * sizeof(uint64_t));
2350
2351 /* Copy the compiler UBO range state to the compiled shader, dropping
2352 * out arrays that were never referenced by an indirect load.
2353 *
2354 * (Note that QIR dead code elimination of an array access still
2355 * leaves that array alive, though)
2356 */
2357 if (c->num_ubo_ranges) {
2358 shader->num_ubo_ranges = c->num_ubo_ranges;
2359 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2360 c->num_ubo_ranges);
2361 uint32_t j = 0;
2362 for (int i = 0; i < c->num_uniform_ranges; i++) {
2363 struct vc4_compiler_ubo_range *range =
2364 &c->ubo_ranges[i];
2365 if (!range->used)
2366 continue;
2367
2368 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2369 shader->ubo_ranges[j].src_offset = range->src_offset;
2370 shader->ubo_ranges[j].size = range->size;
2371 shader->ubo_size += c->ubo_ranges[i].size;
2372 j++;
2373 }
2374 }
2375 if (shader->ubo_size) {
2376 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2377 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2378 qir_get_stage_name(c->stage),
2379 c->program_id, c->variant_id,
2380 shader->ubo_size / 4);
2381 }
2382 }
2383
2384 qir_compile_destroy(c);
2385
2386 struct vc4_key *dup_key;
2387 dup_key = ralloc_size(shader, key_size);
2388 memcpy(dup_key, key, key_size);
2389 _mesa_hash_table_insert(ht, dup_key, shader);
2390
2391 return shader;
2392 }
2393
2394 static void
2395 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2396 struct vc4_texture_stateobj *texstate)
2397 {
2398 for (int i = 0; i < texstate->num_textures; i++) {
2399 struct pipe_sampler_view *sampler = texstate->textures[i];
2400 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2401 struct pipe_sampler_state *sampler_state =
2402 texstate->samplers[i];
2403
2404 if (!sampler)
2405 continue;
2406
2407 key->tex[i].format = sampler->format;
2408 key->tex[i].swizzle[0] = sampler->swizzle_r;
2409 key->tex[i].swizzle[1] = sampler->swizzle_g;
2410 key->tex[i].swizzle[2] = sampler->swizzle_b;
2411 key->tex[i].swizzle[3] = sampler->swizzle_a;
2412
2413 if (sampler->texture->nr_samples > 1) {
2414 key->tex[i].msaa_width = sampler->texture->width0;
2415 key->tex[i].msaa_height = sampler->texture->height0;
2416 } else if (sampler){
2417 key->tex[i].compare_mode = sampler_state->compare_mode;
2418 key->tex[i].compare_func = sampler_state->compare_func;
2419 key->tex[i].wrap_s = sampler_state->wrap_s;
2420 key->tex[i].wrap_t = sampler_state->wrap_t;
2421 key->tex[i].force_first_level =
2422 vc4_sampler->force_first_level;
2423 }
2424 }
2425
2426 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2427 }
2428
2429 static void
2430 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2431 {
2432 struct vc4_fs_key local_key;
2433 struct vc4_fs_key *key = &local_key;
2434
2435 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2436 VC4_DIRTY_BLEND |
2437 VC4_DIRTY_FRAMEBUFFER |
2438 VC4_DIRTY_ZSA |
2439 VC4_DIRTY_RASTERIZER |
2440 VC4_DIRTY_SAMPLE_MASK |
2441 VC4_DIRTY_FRAGTEX |
2442 VC4_DIRTY_UNCOMPILED_FS))) {
2443 return;
2444 }
2445
2446 memset(key, 0, sizeof(*key));
2447 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2448 key->base.shader_state = vc4->prog.bind_fs;
2449 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2450 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2451 prim_mode <= PIPE_PRIM_LINE_STRIP);
2452 key->blend = vc4->blend->rt[0];
2453 if (vc4->blend->logicop_enable) {
2454 key->logicop_func = vc4->blend->logicop_func;
2455 } else {
2456 key->logicop_func = PIPE_LOGICOP_COPY;
2457 }
2458 if (vc4->msaa) {
2459 key->msaa = vc4->rasterizer->base.multisample;
2460 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2461 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2462 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2463 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2464 }
2465
2466 if (vc4->framebuffer.cbufs[0])
2467 key->color_format = vc4->framebuffer.cbufs[0]->format;
2468
2469 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2470 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2471 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2472 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2473 key->stencil_enabled);
2474 if (vc4->zsa->base.alpha.enabled) {
2475 key->alpha_test = true;
2476 key->alpha_test_func = vc4->zsa->base.alpha.func;
2477 }
2478
2479 if (key->is_points) {
2480 key->point_sprite_mask =
2481 vc4->rasterizer->base.sprite_coord_enable;
2482 key->point_coord_upper_left =
2483 (vc4->rasterizer->base.sprite_coord_mode ==
2484 PIPE_SPRITE_COORD_UPPER_LEFT);
2485 }
2486
2487 key->light_twoside = vc4->rasterizer->base.light_twoside;
2488
2489 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2490 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2491 if (vc4->prog.fs == old_fs)
2492 return;
2493
2494 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2495
2496 if (vc4->rasterizer->base.flatshade &&
2497 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2498 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2499 }
2500
2501 if (old_fs && vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2502 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2503 }
2504
2505 static void
2506 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2507 {
2508 struct vc4_vs_key local_key;
2509 struct vc4_vs_key *key = &local_key;
2510
2511 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2512 VC4_DIRTY_RASTERIZER |
2513 VC4_DIRTY_VERTTEX |
2514 VC4_DIRTY_VTXSTATE |
2515 VC4_DIRTY_UNCOMPILED_VS |
2516 VC4_DIRTY_FS_INPUTS))) {
2517 return;
2518 }
2519
2520 memset(key, 0, sizeof(*key));
2521 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2522 key->base.shader_state = vc4->prog.bind_vs;
2523 key->fs_inputs = vc4->prog.fs->fs_inputs;
2524 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2525
2526 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2527 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2528
2529 key->per_vertex_point_size =
2530 (prim_mode == PIPE_PRIM_POINTS &&
2531 vc4->rasterizer->base.point_size_per_vertex);
2532
2533 struct vc4_compiled_shader *vs =
2534 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2535 if (vs != vc4->prog.vs) {
2536 vc4->prog.vs = vs;
2537 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2538 }
2539
2540 key->is_coord = true;
2541 /* Coord shaders don't care what the FS inputs are. */
2542 key->fs_inputs = NULL;
2543 struct vc4_compiled_shader *cs =
2544 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2545 if (cs != vc4->prog.cs) {
2546 vc4->prog.cs = cs;
2547 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2548 }
2549 }
2550
2551 void
2552 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2553 {
2554 vc4_update_compiled_fs(vc4, prim_mode);
2555 vc4_update_compiled_vs(vc4, prim_mode);
2556 }
2557
2558 static uint32_t
2559 fs_cache_hash(const void *key)
2560 {
2561 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2562 }
2563
2564 static uint32_t
2565 vs_cache_hash(const void *key)
2566 {
2567 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2568 }
2569
2570 static bool
2571 fs_cache_compare(const void *key1, const void *key2)
2572 {
2573 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2574 }
2575
2576 static bool
2577 vs_cache_compare(const void *key1, const void *key2)
2578 {
2579 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2580 }
2581
2582 static uint32_t
2583 fs_inputs_hash(const void *key)
2584 {
2585 const struct vc4_fs_inputs *inputs = key;
2586
2587 return _mesa_hash_data(inputs->input_slots,
2588 sizeof(*inputs->input_slots) *
2589 inputs->num_inputs);
2590 }
2591
2592 static bool
2593 fs_inputs_compare(const void *key1, const void *key2)
2594 {
2595 const struct vc4_fs_inputs *inputs1 = key1;
2596 const struct vc4_fs_inputs *inputs2 = key2;
2597
2598 return (inputs1->num_inputs == inputs2->num_inputs &&
2599 memcmp(inputs1->input_slots,
2600 inputs2->input_slots,
2601 sizeof(*inputs1->input_slots) *
2602 inputs1->num_inputs) == 0);
2603 }
2604
2605 static void
2606 delete_from_cache_if_matches(struct hash_table *ht,
2607 struct hash_entry *entry,
2608 struct vc4_uncompiled_shader *so)
2609 {
2610 const struct vc4_key *key = entry->key;
2611
2612 if (key->shader_state == so) {
2613 struct vc4_compiled_shader *shader = entry->data;
2614 _mesa_hash_table_remove(ht, entry);
2615 vc4_bo_unreference(&shader->bo);
2616 ralloc_free(shader);
2617 }
2618 }
2619
2620 static void
2621 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2622 {
2623 struct vc4_context *vc4 = vc4_context(pctx);
2624 struct vc4_uncompiled_shader *so = hwcso;
2625
2626 struct hash_entry *entry;
2627 hash_table_foreach(vc4->fs_cache, entry)
2628 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2629 hash_table_foreach(vc4->vs_cache, entry)
2630 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2631
2632 ralloc_free(so->base.ir.nir);
2633 free(so);
2634 }
2635
2636 static void
2637 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2638 {
2639 struct vc4_context *vc4 = vc4_context(pctx);
2640 vc4->prog.bind_fs = hwcso;
2641 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2642 }
2643
2644 static void
2645 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2646 {
2647 struct vc4_context *vc4 = vc4_context(pctx);
2648 vc4->prog.bind_vs = hwcso;
2649 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2650 }
2651
2652 void
2653 vc4_program_init(struct pipe_context *pctx)
2654 {
2655 struct vc4_context *vc4 = vc4_context(pctx);
2656
2657 pctx->create_vs_state = vc4_shader_state_create;
2658 pctx->delete_vs_state = vc4_shader_state_delete;
2659
2660 pctx->create_fs_state = vc4_shader_state_create;
2661 pctx->delete_fs_state = vc4_shader_state_delete;
2662
2663 pctx->bind_fs_state = vc4_fp_state_bind;
2664 pctx->bind_vs_state = vc4_vp_state_bind;
2665
2666 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2667 fs_cache_compare);
2668 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2669 vs_cache_compare);
2670 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
2671 fs_inputs_compare);
2672 }
2673
2674 void
2675 vc4_program_fini(struct pipe_context *pctx)
2676 {
2677 struct vc4_context *vc4 = vc4_context(pctx);
2678
2679 struct hash_entry *entry;
2680 hash_table_foreach(vc4->fs_cache, entry) {
2681 struct vc4_compiled_shader *shader = entry->data;
2682 vc4_bo_unreference(&shader->bo);
2683 ralloc_free(shader);
2684 _mesa_hash_table_remove(vc4->fs_cache, entry);
2685 }
2686
2687 hash_table_foreach(vc4->vs_cache, entry) {
2688 struct vc4_compiled_shader *shader = entry->data;
2689 vc4_bo_unreference(&shader->bo);
2690 ralloc_free(shader);
2691 _mesa_hash_table_remove(vc4->vs_cache, entry);
2692 }
2693 }