2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2015 Broadcom
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26 * @file vc4_qir_schedule.c
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies from the bottom up, and make a list of the DAG
30 * heads. Heuristically pick a DAG head and schedule (remove) it, then put
31 * all the parents that are now DAG heads into the list of things to
34 * The goal of scheduling here, before register allocation and conversion to
35 * QPU instructions, is to reduce register pressure by reordering instructions
36 * to consume values when possible.
43 struct schedule_node
{
44 struct list_head link
;
47 struct schedule_node
**children
;
49 uint32_t child_array_size
;
50 uint32_t parent_count
;
52 /* Length of the longest (latency) chain from a DAG head to the this
57 /* Longest time + latency_between(parent, this) of any parent of this
60 uint32_t unblocked_time
;
63 struct schedule_state
{
64 /* List of struct schedule_node *. This starts out with all
65 * instructions, and after dependency updates it's trimmed to be just
68 struct list_head worklist
;
72 uint32_t *temp_writes
;
74 BITSET_WORD
*temp_live
;
77 /* When walking the instructions in reverse, we need to swap before/after in
80 enum direction
{ F
, R
};
83 * Marks a dependency between two intructions, that \p after must appear after
86 * Our dependencies are tracked as a DAG. Since we're scheduling bottom-up,
87 * the latest instructions with nothing left to schedule are the DAG heads,
88 * and their inputs are their children.
91 add_dep(enum direction dir
,
92 struct schedule_node
*before
,
93 struct schedule_node
*after
)
95 if (!before
|| !after
)
98 assert(before
!= after
);
101 struct schedule_node
*t
= before
;
106 for (int i
= 0; i
< after
->child_count
; i
++) {
107 if (after
->children
[i
] == after
)
111 if (after
->child_array_size
<= after
->child_count
) {
112 after
->child_array_size
= MAX2(after
->child_array_size
* 2, 16);
113 after
->children
= reralloc(after
, after
->children
,
114 struct schedule_node
*,
115 after
->child_array_size
);
118 after
->children
[after
->child_count
] = before
;
119 after
->child_count
++;
120 before
->parent_count
++;
124 add_write_dep(enum direction dir
,
125 struct schedule_node
**before
,
126 struct schedule_node
*after
)
128 add_dep(dir
, *before
, after
);
132 struct schedule_setup_state
{
133 struct schedule_node
**last_temp_write
;
134 struct schedule_node
*last_sf
;
135 struct schedule_node
*last_vary_read
;
136 struct schedule_node
*last_vpm_read
;
137 struct schedule_node
*last_vpm_write
;
138 struct schedule_node
*last_tex_coord
;
139 struct schedule_node
*last_tex_result
;
140 struct schedule_node
*last_tlb
;
144 * Texture FIFO tracking. This is done top-to-bottom, and is used to
145 * track the QOP_TEX_RESULTs and add dependencies on previous ones
146 * when trying to submit texture coords with TFREQ full or new texture
147 * fetches with TXRCV full.
150 struct schedule_node
*node
;
153 int tfreq_count
; /**< Number of texture coords outstanding. */
154 int tfrcv_count
; /**< Number of texture results outstanding. */
159 block_until_tex_result(struct schedule_setup_state
*state
, struct schedule_node
*n
)
161 add_dep(state
->dir
, state
->tex_fifo
[0].node
, n
);
163 state
->tfreq_count
-= state
->tex_fifo
[0].coords
;
164 state
->tfrcv_count
--;
166 memmove(&state
->tex_fifo
[0],
168 state
->tex_fifo_pos
* sizeof(state
->tex_fifo
[0]));
169 state
->tex_fifo_pos
--;
173 * Common code for dependencies that need to be tracked both forward and
176 * This is for things like "all VPM reads have to happen in order."
179 calculate_deps(struct schedule_setup_state
*state
, struct schedule_node
*n
)
181 struct qinst
*inst
= n
->inst
;
182 enum direction dir
= state
->dir
;
185 /* Add deps for temp registers and varyings accesses. Note that we
186 * ignore uniforms accesses, because qir_reorder_uniforms() happens
189 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
190 switch (inst
->src
[i
].file
) {
193 state
->last_temp_write
[inst
->src
[i
].index
], n
);
197 add_write_dep(dir
, &state
->last_vary_read
, n
);
201 add_write_dep(dir
, &state
->last_vpm_read
, n
);
211 add_dep(dir
, state
->last_vary_read
, n
);
219 /* Texturing setup gets scheduled in order, because
220 * the uniforms referenced by them have to land in a
223 add_write_dep(dir
, &state
->last_tex_coord
, n
);
227 /* Results have to be fetched in order. */
228 add_write_dep(dir
, &state
->last_tex_result
, n
);
231 case QOP_TLB_COLOR_READ
:
233 add_write_dep(dir
, &state
->last_tlb
, n
);
240 switch (inst
->dst
.file
) {
242 add_write_dep(dir
, &state
->last_vpm_write
, n
);
246 add_write_dep(dir
, &state
->last_temp_write
[inst
->dst
.index
], n
);
249 case QFILE_TLB_COLOR_WRITE
:
250 case QFILE_TLB_COLOR_WRITE_MS
:
251 case QFILE_TLB_Z_WRITE
:
252 case QFILE_TLB_STENCIL_SETUP
:
253 add_write_dep(dir
, &state
->last_tlb
, n
);
260 if (qir_depends_on_flags(inst
))
261 add_dep(dir
, state
->last_sf
, n
);
264 add_write_dep(dir
, &state
->last_sf
, n
);
268 calculate_forward_deps(struct vc4_compile
*c
, void *mem_ctx
,
269 struct list_head
*schedule_list
)
271 struct schedule_setup_state state
;
273 memset(&state
, 0, sizeof(state
));
274 state
.last_temp_write
= rzalloc_array(mem_ctx
, struct schedule_node
*,
278 list_for_each_entry(struct schedule_node
, n
, schedule_list
, link
) {
279 struct qinst
*inst
= n
->inst
;
281 calculate_deps(&state
, n
);
289 /* If the texture coordinate fifo is full,
290 * block this on the last QOP_TEX_RESULT.
292 if (state
.tfreq_count
== 8) {
293 block_until_tex_result(&state
, n
);
296 /* If the texture result fifo is full, block
297 * adding any more to it until the last
300 if (inst
->op
== QOP_TEX_S
||
301 inst
->op
== QOP_TEX_DIRECT
) {
302 if (state
.tfrcv_count
== 4)
303 block_until_tex_result(&state
, n
);
307 state
.tex_fifo
[state
.tex_fifo_pos
].coords
++;
312 /* Results have to be fetched after the
313 * coordinate setup. Note that we're assuming
314 * here that our input shader has the texture
315 * coord setup and result fetch in order,
316 * which is true initially but not of our
317 * instruction stream after this pass.
319 add_dep(state
.dir
, state
.last_tex_coord
, n
);
321 state
.tex_fifo
[state
.tex_fifo_pos
].node
= n
;
323 state
.tex_fifo_pos
++;
324 memset(&state
.tex_fifo
[state
.tex_fifo_pos
], 0,
325 sizeof(state
.tex_fifo
[0]));
328 assert(!qir_is_tex(inst
));
335 calculate_reverse_deps(struct vc4_compile
*c
, void *mem_ctx
,
336 struct list_head
*schedule_list
)
338 struct schedule_setup_state state
;
340 memset(&state
, 0, sizeof(state
));
342 state
.last_temp_write
= rzalloc_array(mem_ctx
, struct schedule_node
*,
345 list_for_each_entry_rev(struct schedule_node
, n
, schedule_list
, link
) {
346 calculate_deps(&state
, n
);
351 get_register_pressure_cost(struct schedule_state
*state
, struct qinst
*inst
)
355 if (inst
->dst
.file
== QFILE_TEMP
&&
356 state
->temp_writes
[inst
->dst
.index
] == 1)
359 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
360 if (inst
->src
[i
].file
== QFILE_TEMP
&&
361 !BITSET_TEST(state
->temp_live
, inst
->src
[i
].index
)) {
370 locks_scoreboard(struct qinst
*inst
)
372 if (inst
->op
== QOP_TLB_COLOR_READ
)
375 switch (inst
->dst
.file
) {
376 case QFILE_TLB_Z_WRITE
:
377 case QFILE_TLB_COLOR_WRITE
:
378 case QFILE_TLB_COLOR_WRITE_MS
:
385 static struct schedule_node
*
386 choose_instruction(struct schedule_state
*state
)
388 struct schedule_node
*chosen
= NULL
;
390 list_for_each_entry(struct schedule_node
, n
, &state
->worklist
, link
) {
396 /* Prefer scheduling things that lock the scoreboard, so that
397 * they appear late in the program and we get more parallelism
398 * between shaders on multiple QPUs hitting the same fragment.
400 if (locks_scoreboard(n
->inst
) &&
401 !locks_scoreboard(chosen
->inst
)) {
404 } else if (!locks_scoreboard(n
->inst
) &&
405 locks_scoreboard(chosen
->inst
)) {
409 /* If we would block on the previously chosen node, but would
410 * block less on this one, then then prefer it.
412 if (chosen
->unblocked_time
> state
->time
&&
413 n
->unblocked_time
< chosen
->unblocked_time
) {
416 } else if (n
->unblocked_time
> state
->time
&&
417 n
->unblocked_time
> chosen
->unblocked_time
) {
421 /* If we can definitely reduce register pressure, do so
424 int register_pressure_cost
=
425 get_register_pressure_cost(state
, n
->inst
);
426 int chosen_register_pressure_cost
=
427 get_register_pressure_cost(state
, chosen
->inst
);
429 if (register_pressure_cost
< chosen_register_pressure_cost
) {
432 } else if (register_pressure_cost
>
433 chosen_register_pressure_cost
) {
437 /* Otherwise, prefer instructions with the deepest chain to
438 * the end of the program. This avoids the problem of
439 * "everything generates a temp, nothing finishes freeing one,
440 * guess I'll just keep emitting varying mul/adds".
442 if (n
->delay
> chosen
->delay
) {
445 } else if (n
->delay
< chosen
->delay
) {
454 dump_state(struct vc4_compile
*c
, struct schedule_state
*state
)
457 list_for_each_entry(struct schedule_node
, n
, &state
->worklist
, link
) {
458 fprintf(stderr
, "%3d: ", i
++);
459 qir_dump_inst(c
, n
->inst
);
460 fprintf(stderr
, " (%d cost)\n",
461 get_register_pressure_cost(state
, n
->inst
));
463 for (int i
= 0; i
< n
->child_count
; i
++) {
464 struct schedule_node
*child
= n
->children
[i
];
465 fprintf(stderr
, " - ");
466 qir_dump_inst(c
, child
->inst
);
467 fprintf(stderr
, " (%d parents)\n", child
->parent_count
);
472 /* Estimate of how many instructions we should schedule between operations.
474 * These aren't in real cycle counts, because we're just estimating cycle
475 * times anyway. QIR instructions will get paired up when turned into QPU
476 * instructions, or extra NOP delays will have to be added due to register
477 * allocation choices.
480 latency_between(struct schedule_node
*before
, struct schedule_node
*after
)
482 if ((before
->inst
->op
== QOP_TEX_S
||
483 before
->inst
->op
== QOP_TEX_DIRECT
) &&
484 after
->inst
->op
== QOP_TEX_RESULT
)
490 /** Recursive computation of the delay member of a node. */
492 compute_delay(struct schedule_node
*n
)
494 if (!n
->child_count
) {
495 /* The color read needs to be scheduled late, to avoid locking
496 * the scoreboard early. This is our best tool for
497 * encouraging that. The other scoreboard locking ops will
498 * have this happen by default, since they are generally the
499 * DAG heads or close to them.
501 if (n
->inst
->op
== QOP_TLB_COLOR_READ
)
506 for (int i
= 0; i
< n
->child_count
; i
++) {
507 if (!n
->children
[i
]->delay
)
508 compute_delay(n
->children
[i
]);
509 n
->delay
= MAX2(n
->delay
,
510 n
->children
[i
]->delay
+
511 latency_between(n
, n
->children
[i
]));
517 schedule_instructions(struct vc4_compile
*c
, struct schedule_state
*state
)
520 fprintf(stderr
, "initial deps:\n");
521 dump_state(c
, state
);
524 /* Remove non-DAG heads from the list. */
525 list_for_each_entry_safe(struct schedule_node
, n
,
526 &state
->worklist
, link
) {
527 if (n
->parent_count
!= 0)
532 while (!list_empty(&state
->worklist
)) {
533 struct schedule_node
*chosen
= choose_instruction(state
);
534 struct qinst
*inst
= chosen
->inst
;
537 fprintf(stderr
, "current list:\n");
538 dump_state(c
, state
);
539 fprintf(stderr
, "chose: ");
540 qir_dump_inst(c
, inst
);
541 fprintf(stderr
, " (%d cost)\n",
542 get_register_pressure_cost(state
, inst
));
545 state
->time
= MAX2(state
->time
, chosen
->unblocked_time
);
547 /* Schedule this instruction back onto the QIR list. */
548 list_del(&chosen
->link
);
549 list_add(&inst
->link
, &c
->instructions
);
551 /* Now that we've scheduled a new instruction, some of its
552 * children can be promoted to the list of instructions ready to
553 * be scheduled. Update the children's unblocked time for this
554 * DAG edge as we do so.
556 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
557 struct schedule_node
*child
= chosen
->children
[i
];
559 child
->unblocked_time
= MAX2(child
->unblocked_time
,
561 latency_between(chosen
,
563 child
->parent_count
--;
564 if (child
->parent_count
== 0)
565 list_add(&child
->link
, &state
->worklist
);
568 /* Update our tracking of register pressure. */
569 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
570 if (inst
->src
[i
].file
== QFILE_TEMP
)
571 BITSET_SET(state
->temp_live
, inst
->src
[i
].index
);
573 if (inst
->dst
.file
== QFILE_TEMP
) {
574 state
->temp_writes
[inst
->dst
.index
]--;
575 if (state
->temp_writes
[inst
->dst
.index
] == 0)
576 BITSET_CLEAR(state
->temp_live
, inst
->dst
.index
);
584 qir_schedule_instructions(struct vc4_compile
*c
)
586 void *mem_ctx
= ralloc_context(NULL
);
587 struct schedule_state state
= { { 0 } };
590 fprintf(stderr
, "Pre-schedule instructions\n");
594 state
.temp_writes
= rzalloc_array(mem_ctx
, uint32_t, c
->num_temps
);
595 state
.temp_live
= rzalloc_array(mem_ctx
, BITSET_WORD
,
596 BITSET_WORDS(c
->num_temps
));
597 list_inithead(&state
.worklist
);
599 /* Wrap each instruction in a scheduler structure. */
600 list_for_each_entry_safe(struct qinst
, inst
, &c
->instructions
, link
) {
601 struct schedule_node
*n
= rzalloc(mem_ctx
, struct schedule_node
);
604 list_del(&inst
->link
);
605 list_addtail(&n
->link
, &state
.worklist
);
607 if (inst
->dst
.file
== QFILE_TEMP
)
608 state
.temp_writes
[inst
->dst
.index
]++;
611 /* Dependencies tracked top-to-bottom. */
612 calculate_forward_deps(c
, mem_ctx
, &state
.worklist
);
613 /* Dependencies tracked bottom-to-top. */
614 calculate_reverse_deps(c
, mem_ctx
, &state
.worklist
);
616 list_for_each_entry(struct schedule_node
, n
, &state
.worklist
, link
)
619 schedule_instructions(c
, &state
);
622 fprintf(stderr
, "Post-schedule instructions\n");
626 ralloc_free(mem_ctx
);