src/gallium/drivers/vc4/vc4_qpu_defines.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef VC4_QPU_DEFINES_H
  25 #define VC4_QPU_DEFINES_H
  26
  27 #include <assert.h>
  28 #include <util/macros.h>
  29
  30 enum qpu_op_add {
  31         QPU_A_NOP,
  32         QPU_A_FADD,
  33         QPU_A_FSUB,
  34         QPU_A_FMIN,
  35         QPU_A_FMAX,
  36         QPU_A_FMINABS,
  37         QPU_A_FMAXABS,
  38         QPU_A_FTOI,
  39         QPU_A_ITOF,
  40         QPU_A_ADD = 12,
  41         QPU_A_SUB,
  42         QPU_A_SHR,
  43         QPU_A_ASR,
  44         QPU_A_ROR,
  45         QPU_A_SHL,
  46         QPU_A_MIN,
  47         QPU_A_MAX,
  48         QPU_A_AND,
  49         QPU_A_OR,
  50         QPU_A_XOR,
  51         QPU_A_NOT,
  52         QPU_A_CLZ,
  53         QPU_A_V8ADDS = 30,
  54         QPU_A_V8SUBS = 31,
  55 };
  56
  57 enum qpu_op_mul {
  58         QPU_M_NOP,
  59         QPU_M_FMUL,
  60         QPU_M_MUL24,
  61         QPU_M_V8MULD,
  62         QPU_M_V8MIN,
  63         QPU_M_V8MAX,
  64         QPU_M_V8ADDS,
  65         QPU_M_V8SUBS,
  66 };
  67
  68 enum qpu_raddr {
  69         QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */
  70         /* 0-31 are the plain regfile a or b fields */
  71         QPU_R_UNIF = 32,
  72         QPU_R_VARY = 35,
  73         QPU_R_ELEM_QPU = 38,
  74         QPU_R_NOP,
  75         QPU_R_XY_PIXEL_COORD = 41,
  76         QPU_R_MS_REV_FLAGS = 42,
  77         QPU_R_VPM = 48,
  78         QPU_R_VPM_LD_BUSY,
  79         QPU_R_VPM_LD_WAIT,
  80         QPU_R_MUTEX_ACQUIRE,
  81 };
  82
  83 enum qpu_waddr {
  84         /* 0-31 are the plain regfile a or b fields */
  85         QPU_W_ACC0 = 32, /* aka r0 */
  86         QPU_W_ACC1,
  87         QPU_W_ACC2,
  88         QPU_W_ACC3,
  89         QPU_W_TMU_NOSWAP,
  90         QPU_W_ACC5,
  91         QPU_W_HOST_INT,
  92         QPU_W_NOP,
  93         QPU_W_UNIFORMS_ADDRESS,
  94         QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */
  95         QPU_W_MS_FLAGS = 42,
  96         QPU_W_REV_FLAG = 42,
  97         QPU_W_TLB_STENCIL_SETUP = 43,
  98         QPU_W_TLB_Z,
  99         QPU_W_TLB_COLOR_MS,
 100         QPU_W_TLB_COLOR_ALL,
 101         QPU_W_TLB_ALPHA_MASK,
 102         QPU_W_VPM,
 103         QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */
 104         QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */
 105         QPU_W_MUTEX_RELEASE,
 106         QPU_W_SFU_RECIP,
 107         QPU_W_SFU_RECIPSQRT,
 108         QPU_W_SFU_EXP,
 109         QPU_W_SFU_LOG,
 110         QPU_W_TMU0_S,
 111         QPU_W_TMU0_T,
 112         QPU_W_TMU0_R,
 113         QPU_W_TMU0_B,
 114         QPU_W_TMU1_S,
 115         QPU_W_TMU1_T,
 116         QPU_W_TMU1_R,
 117         QPU_W_TMU1_B,
 118 };
 119
 120 enum qpu_sig_bits {
 121         QPU_SIG_SW_BREAKPOINT,
 122         QPU_SIG_NONE,
 123         QPU_SIG_THREAD_SWITCH,
 124         QPU_SIG_PROG_END,
 125         QPU_SIG_WAIT_FOR_SCOREBOARD,
 126         QPU_SIG_SCOREBOARD_UNLOCK,
 127         QPU_SIG_LAST_THREAD_SWITCH,
 128         QPU_SIG_COVERAGE_LOAD,
 129         QPU_SIG_COLOR_LOAD,
 130         QPU_SIG_COLOR_LOAD_END,
 131         QPU_SIG_LOAD_TMU0,
 132         QPU_SIG_LOAD_TMU1,
 133         QPU_SIG_ALPHA_MASK_LOAD,
 134         QPU_SIG_SMALL_IMM,
 135         QPU_SIG_LOAD_IMM,
 136         QPU_SIG_BRANCH
 137 };
 138
 139 enum qpu_mux {
 140         /* hardware mux values */
 141         QPU_MUX_R0,
 142         QPU_MUX_R1,
 143         QPU_MUX_R2,
 144         QPU_MUX_R3,
 145         QPU_MUX_R4,
 146         QPU_MUX_R5,
 147         QPU_MUX_A,
 148         QPU_MUX_B,
 149
 150         /**
 151          * Non-hardware mux value, stores a small immediate field to be
 152          * programmed into raddr_b in the qpu_reg.index.
 153          */
 154         QPU_MUX_SMALL_IMM,
 155 };
 156
 157 enum qpu_cond {
 158         QPU_COND_NEVER,
 159         QPU_COND_ALWAYS,
 160         QPU_COND_ZS,
 161         QPU_COND_ZC,
 162         QPU_COND_NS,
 163         QPU_COND_NC,
 164         QPU_COND_CS,
 165         QPU_COND_CC,
 166 };
 167
 168 enum qpu_branch_cond {
 169         QPU_COND_BRANCH_ALL_ZS,
 170         QPU_COND_BRANCH_ALL_ZC,
 171         QPU_COND_BRANCH_ANY_ZS,
 172         QPU_COND_BRANCH_ANY_ZC,
 173         QPU_COND_BRANCH_ALL_NS,
 174         QPU_COND_BRANCH_ALL_NC,
 175         QPU_COND_BRANCH_ANY_NS,
 176         QPU_COND_BRANCH_ANY_NC,
 177         QPU_COND_BRANCH_ALL_CS,
 178         QPU_COND_BRANCH_ALL_CC,
 179         QPU_COND_BRANCH_ANY_CS,
 180         QPU_COND_BRANCH_ANY_CC,
 181
 182         QPU_COND_BRANCH_ALWAYS = 15
 183 };
 184
 185 enum qpu_pack_mul {
 186         QPU_PACK_MUL_NOP,
 187         QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */
 188         QPU_PACK_MUL_8A,
 189         QPU_PACK_MUL_8B,
 190         QPU_PACK_MUL_8C,
 191         QPU_PACK_MUL_8D,
 192 };
 193
 194 enum qpu_pack_a {
 195         QPU_PACK_A_NOP,
 196         /* convert to 16 bit float if float input, or to int16. */
 197         QPU_PACK_A_16A,
 198         QPU_PACK_A_16B,
 199         /* replicated to each 8 bits of the 32-bit dst. */
 200         QPU_PACK_A_8888,
 201         /* Convert to 8-bit unsigned int. */
 202         QPU_PACK_A_8A,
 203         QPU_PACK_A_8B,
 204         QPU_PACK_A_8C,
 205         QPU_PACK_A_8D,
 206
 207         /* Saturating variants of the previous instructions. */
 208         QPU_PACK_A_32_SAT, /* int-only */
 209         QPU_PACK_A_16A_SAT, /* int or float */
 210         QPU_PACK_A_16B_SAT,
 211         QPU_PACK_A_8888_SAT,
 212         QPU_PACK_A_8A_SAT,
 213         QPU_PACK_A_8B_SAT,
 214         QPU_PACK_A_8C_SAT,
 215         QPU_PACK_A_8D_SAT,
 216 };
 217
 218 enum qpu_unpack {
 219         QPU_UNPACK_NOP,
 220         QPU_UNPACK_16A,
 221         QPU_UNPACK_16B,
 222         QPU_UNPACK_8D_REP,
 223         QPU_UNPACK_8A,
 224         QPU_UNPACK_8B,
 225         QPU_UNPACK_8C,
 226         QPU_UNPACK_8D,
 227 };
 228
 229 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
 230 /* Using the GNU statement expression extension */
 231 #define QPU_SET_FIELD(value, field)                                       \
 232         ({                                                                \
 233                 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
 234                 assert((fieldval & ~ field ## _MASK) == 0);               \
 235                 fieldval & field ## _MASK;                                \
 236          })
 237
 238 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word)  & field ## _MASK) >> field ## _SHIFT))
 239
 240 #define QPU_UPDATE_FIELD(inst, value, field)                              \
 241         (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
 242
 243 #define QPU_SIG_SHIFT                   60
 244 #define QPU_SIG_MASK                    QPU_MASK(63, 60)
 245
 246 #define QPU_UNPACK_SHIFT                57
 247 #define QPU_UNPACK_MASK                 QPU_MASK(59, 57)
 248
 249 #define QPU_LOAD_IMM_MODE_SHIFT         57
 250 #define QPU_LOAD_IMM_MODE_MASK          QPU_MASK(59, 57)
 251 # define QPU_LOAD_IMM_MODE_U32          0
 252 # define QPU_LOAD_IMM_MODE_I2           1
 253 # define QPU_LOAD_IMM_MODE_U2           3
 254
 255 /**
 256  * If set, the pack field means PACK_MUL or R4 packing, instead of normal
 257  * regfile a packing.
 258  */
 259 #define QPU_PM                          ((uint64_t)1 << 56)
 260
 261 #define QPU_PACK_SHIFT                  52
 262 #define QPU_PACK_MASK                   QPU_MASK(55, 52)
 263
 264 #define QPU_COND_ADD_SHIFT              49
 265 #define QPU_COND_ADD_MASK               QPU_MASK(51, 49)
 266 #define QPU_COND_MUL_SHIFT              46
 267 #define QPU_COND_MUL_MASK               QPU_MASK(48, 46)
 268
 269
 270 #define QPU_BRANCH_COND_SHIFT           52
 271 #define QPU_BRANCH_COND_MASK            QPU_MASK(55, 52)
 272
 273 #define QPU_BRANCH_REL                  ((uint64_t)1 << 51)
 274 #define QPU_BRANCH_REG                  ((uint64_t)1 << 50)
 275
 276 #define QPU_BRANCH_RADDR_A_SHIFT        45
 277 #define QPU_BRANCH_RADDR_A_MASK         QPU_MASK(49, 45)
 278
 279 #define QPU_SF                          ((uint64_t)1 << 45)
 280
 281 #define QPU_WADDR_ADD_SHIFT             38
 282 #define QPU_WADDR_ADD_MASK              QPU_MASK(43, 38)
 283 #define QPU_WADDR_MUL_SHIFT             32
 284 #define QPU_WADDR_MUL_MASK              QPU_MASK(37, 32)
 285
 286 #define QPU_OP_MUL_SHIFT                29
 287 #define QPU_OP_MUL_MASK                 QPU_MASK(31, 29)
 288
 289 #define QPU_RADDR_A_SHIFT               18
 290 #define QPU_RADDR_A_MASK                QPU_MASK(23, 18)
 291 #define QPU_RADDR_B_SHIFT               12
 292 #define QPU_RADDR_B_MASK                QPU_MASK(17, 12)
 293 #define QPU_SMALL_IMM_SHIFT             12
 294 #define QPU_SMALL_IMM_MASK              QPU_MASK(17, 12)
 295 /* Small immediate value for rotate-by-r5, and 49-63 are "rotate by n
 296  * channels"
 297  */
 298 #define QPU_SMALL_IMM_MUL_ROT           48
 299
 300 #define QPU_ADD_A_SHIFT                 9
 301 #define QPU_ADD_A_MASK                  QPU_MASK(11, 9)
 302 #define QPU_ADD_B_SHIFT                 6
 303 #define QPU_ADD_B_MASK                  QPU_MASK(8, 6)
 304 #define QPU_MUL_A_SHIFT                 3
 305 #define QPU_MUL_A_MASK                  QPU_MASK(5, 3)
 306 #define QPU_MUL_B_SHIFT                 0
 307 #define QPU_MUL_B_MASK                  QPU_MASK(2, 0)
 308
 309 #define QPU_WS                          ((uint64_t)1 << 44)
 310
 311 #define QPU_OP_ADD_SHIFT                24
 312 #define QPU_OP_ADD_MASK                 QPU_MASK(28, 24)
 313
 314 #define QPU_LOAD_IMM_SHIFT              0
 315 #define QPU_LOAD_IMM_MASK               QPU_MASK(31, 0)
 316
 317 #define QPU_BRANCH_TARGET_SHIFT         0
 318 #define QPU_BRANCH_TARGET_MASK          QPU_MASK(31, 0)
 319
 320 #endif /* VC4_QPU_DEFINES_H */