src/gallium/drivers/vc4/vc4_register_allocate.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/ralloc.h"
  25 #include "util/register_allocate.h"
  26 #include "vc4_context.h"
  27 #include "vc4_qir.h"
  28 #include "vc4_qpu.h"
  29
  30 #define QPU_R(file, index) { QPU_MUX_##file, index }
  31
  32 static const struct qpu_reg vc4_regs[] = {
  33         { QPU_MUX_R0, 0},
  34         { QPU_MUX_R1, 0},
  35         { QPU_MUX_R2, 0},
  36         { QPU_MUX_R3, 0},
  37         { QPU_MUX_R4, 0},
  38         QPU_R(A, 0),
  39         QPU_R(A, 1),
  40         QPU_R(A, 2),
  41         QPU_R(A, 3),
  42         QPU_R(A, 4),
  43         QPU_R(A, 5),
  44         QPU_R(A, 6),
  45         QPU_R(A, 7),
  46         QPU_R(A, 8),
  47         QPU_R(A, 9),
  48         QPU_R(A, 10),
  49         QPU_R(A, 11),
  50         QPU_R(A, 12),
  51         QPU_R(A, 13),
  52         QPU_R(A, 14),
  53         QPU_R(A, 15),
  54         QPU_R(A, 16),
  55         QPU_R(A, 17),
  56         QPU_R(A, 18),
  57         QPU_R(A, 19),
  58         QPU_R(A, 20),
  59         QPU_R(A, 21),
  60         QPU_R(A, 22),
  61         QPU_R(A, 23),
  62         QPU_R(A, 24),
  63         QPU_R(A, 25),
  64         QPU_R(A, 26),
  65         QPU_R(A, 27),
  66         QPU_R(A, 28),
  67         QPU_R(A, 29),
  68         QPU_R(A, 30),
  69         QPU_R(A, 31),
  70         QPU_R(B, 0),
  71         QPU_R(B, 1),
  72         QPU_R(B, 2),
  73         QPU_R(B, 3),
  74         QPU_R(B, 4),
  75         QPU_R(B, 5),
  76         QPU_R(B, 6),
  77         QPU_R(B, 7),
  78         QPU_R(B, 8),
  79         QPU_R(B, 9),
  80         QPU_R(B, 10),
  81         QPU_R(B, 11),
  82         QPU_R(B, 12),
  83         QPU_R(B, 13),
  84         QPU_R(B, 14),
  85         QPU_R(B, 15),
  86         QPU_R(B, 16),
  87         QPU_R(B, 17),
  88         QPU_R(B, 18),
  89         QPU_R(B, 19),
  90         QPU_R(B, 20),
  91         QPU_R(B, 21),
  92         QPU_R(B, 22),
  93         QPU_R(B, 23),
  94         QPU_R(B, 24),
  95         QPU_R(B, 25),
  96         QPU_R(B, 26),
  97         QPU_R(B, 27),
  98         QPU_R(B, 28),
  99         QPU_R(B, 29),
 100         QPU_R(B, 30),
 101         QPU_R(B, 31),
 102 };
 103 #define ACC_INDEX     0
 104 #define A_INDEX       (ACC_INDEX + 5)
 105 #define B_INDEX       (A_INDEX + 32)
 106
 107 static void
 108 vc4_alloc_reg_set(struct vc4_context *vc4)
 109 {
 110         assert(vc4_regs[A_INDEX].addr == 0);
 111         assert(vc4_regs[B_INDEX].addr == 0);
 112         STATIC_ASSERT(ARRAY_SIZE(vc4_regs) == B_INDEX + 32);
 113
 114         if (vc4->regs)
 115                 return;
 116
 117         vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs));
 118
 119         vc4->reg_class_any = ra_alloc_reg_class(vc4->regs);
 120         for (uint32_t i = 0; i < ARRAY_SIZE(vc4_regs); i++) {
 121                 /* Reserve r3 for now, since we're using it for spilling-like
 122                  * operations in vc4_qpu_emit.c
 123                  */
 124                 if (vc4_regs[i].mux == QPU_MUX_R3)
 125                         continue;
 126
 127                 /* R4 can't be written as a general purpose register. (it's
 128                  * TMU_NOSWAP as a write address).
 129                  */
 130                 if (vc4_regs[i].mux == QPU_MUX_R4)
 131                         continue;
 132
 133                 ra_class_add_reg(vc4->regs, vc4->reg_class_any, i);
 134         }
 135
 136         vc4->reg_class_a = ra_alloc_reg_class(vc4->regs);
 137         for (uint32_t i = A_INDEX; i < A_INDEX + 32; i++)
 138                 ra_class_add_reg(vc4->regs, vc4->reg_class_a, i);
 139
 140         ra_set_finalize(vc4->regs, NULL);
 141 }
 142
 143 /**
 144  * Returns a mapping from QFILE_TEMP indices to struct qpu_regs.
 145  *
 146  * The return value should be freed by the caller.
 147  */
 148 struct qpu_reg *
 149 vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
 150 {
 151         struct simple_node *node;
 152         uint32_t def[c->num_temps];
 153         uint32_t use[c->num_temps];
 154         struct qpu_reg *temp_registers = calloc(c->num_temps,
 155                                                 sizeof(*temp_registers));
 156         memset(def, 0, sizeof(def));
 157         memset(use, 0, sizeof(use));
 158
 159         /* If things aren't ever written (undefined values), just read from
 160          * r0.
 161          */
 162         for (uint32_t i = 0; i < c->num_temps; i++)
 163                 temp_registers[i] = qpu_rn(0);
 164
 165         vc4_alloc_reg_set(vc4);
 166
 167         struct ra_graph *g = ra_alloc_interference_graph(vc4->regs,
 168                                                          c->num_temps);
 169
 170         for (uint32_t i = 0; i < c->num_temps; i++)
 171                 ra_set_node_class(g, i, vc4->reg_class_any);
 172
 173         /* Compute the live ranges so we can figure out interference, and
 174          * figure out our register classes and preallocated registers.
 175          */
 176         uint32_t ip = 0;
 177         foreach(node, &c->instructions) {
 178                 struct qinst *inst = (struct qinst *)node;
 179
 180                 if (inst->dst.file == QFILE_TEMP) {
 181                         def[inst->dst.index] = ip;
 182                         use[inst->dst.index] = ip;
 183                 }
 184
 185                 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
 186                         if (inst->src[i].file == QFILE_TEMP)
 187                                 use[inst->src[i].index] = ip;
 188                 }
 189
 190                 switch (inst->op) {
 191                 case QOP_FRAG_Z:
 192                         def[inst->dst.index] = 0;
 193                         ra_set_node_reg(g, inst->dst.index,
 194                                         B_INDEX + QPU_R_FRAG_PAYLOAD_ZW);
 195                         break;
 196
 197                 case QOP_FRAG_W:
 198                         def[inst->dst.index] = 0;
 199                         ra_set_node_reg(g, inst->dst.index,
 200                                         A_INDEX + QPU_R_FRAG_PAYLOAD_ZW);
 201                         break;
 202
 203                 case QOP_TEX_RESULT:
 204                 case QOP_TLB_COLOR_READ:
 205                         assert(vc4_regs[ACC_INDEX + 4].mux == QPU_MUX_R4);
 206                         ra_set_node_reg(g, inst->dst.index,
 207                                         ACC_INDEX + 4);
 208                         break;
 209
 210                 case QOP_PACK_SCALED:
 211                         /* The pack flags require an A-file dst register. */
 212                         ra_set_node_class(g, inst->dst.index, vc4->reg_class_a);
 213                         break;
 214
 215                 case QOP_UNPACK_8A:
 216                 case QOP_UNPACK_8B:
 217                 case QOP_UNPACK_8C:
 218                 case QOP_UNPACK_8D:
 219                         /* The unpack flags require an A-file src register. */
 220                         ra_set_node_class(g, inst->src[0].index, vc4->reg_class_a);
 221                         break;
 222
 223                 default:
 224                         break;
 225                 }
 226
 227                 ip++;
 228         }
 229
 230         for (uint32_t i = 0; i < c->num_temps; i++) {
 231                 for (uint32_t j = i + 1; j < c->num_temps; j++) {
 232                         if (!(def[i] >= use[j] || def[j] >= use[i]))
 233                                 ra_add_node_interference(g, i, j);
 234                 }
 235         }
 236
 237         bool ok = ra_allocate(g);
 238         assert(ok);
 239
 240         for (uint32_t i = 0; i < c->num_temps; i++) {
 241                 temp_registers[i] = vc4_regs[ra_get_node_reg(g, i)];
 242
 243                 /* If the value's never used, just write to the NOP register
 244                  * for clarity in debug output.
 245                  */
 246                 if (def[i] == use[i])
 247                         temp_registers[i] = qpu_ra(QPU_W_NOP);
 248         }
 249
 250         ralloc_free(g);
 251
 252         return temp_registers;
 253 }