src/gallium/drivers/vc4/vc4_screen.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "os/os_misc.h"
  26 #include "pipe/p_defines.h"
  27 #include "pipe/p_screen.h"
  28 #include "pipe/p_state.h"
  29
  30 #include "util/u_debug.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_format.h"
  33 #include "util/u_hash_table.h"
  34 #include "util/ralloc.h"
  35
  36 #include <xf86drm.h>
  37 #include "vc4_drm.h"
  38 #include "vc4_screen.h"
  39 #include "vc4_context.h"
  40 #include "vc4_resource.h"
  41
  42 static const struct debug_named_value debug_options[] = {
  43         { "cl",       VC4_DEBUG_CL,
  44           "Dump command list during creation" },
  45         { "qpu",      VC4_DEBUG_QPU,
  46           "Dump generated QPU instructions" },
  47         { "qir",      VC4_DEBUG_QIR,
  48           "Dump QPU IR during program compile" },
  49         { "nir",      VC4_DEBUG_NIR,
  50           "Dump NIR during program compile" },
  51         { "tgsi",     VC4_DEBUG_TGSI,
  52           "Dump TGSI during program compile" },
  53         { "shaderdb", VC4_DEBUG_SHADERDB,
  54           "Dump program compile information for shader-db analysis" },
  55         { "perf",     VC4_DEBUG_PERF,
  56           "Print during performance-related events" },
  57         { "norast",   VC4_DEBUG_NORAST,
  58           "Skip actual hardware execution of commands" },
  59         { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
  60           "Flush after each draw call" },
  61         { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
  62           "Wait for finish after each flush" },
  63 #if USE_VC4_SIMULATOR
  64         { "dump", VC4_DEBUG_DUMP,
  65           "Write a GPU command stream trace file" },
  66 #endif
  67         { NULL }
  68 };
  69
  70 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", debug_options, 0)
  71 uint32_t vc4_debug;
  72
  73 static const char *
  74 vc4_screen_get_name(struct pipe_screen *pscreen)
  75 {
  76         struct vc4_screen *screen = vc4_screen(pscreen);
  77
  78         if (!screen->name) {
  79                 screen->name = ralloc_asprintf(screen,
  80                                                "VC4 V3D %d.%d",
  81                                                screen->v3d_ver / 10,
  82                                                screen->v3d_ver % 10);
  83         }
  84
  85         return screen->name;
  86 }
  87
  88 static const char *
  89 vc4_screen_get_vendor(struct pipe_screen *pscreen)
  90 {
  91         return "Broadcom";
  92 }
  93
  94 static void
  95 vc4_screen_destroy(struct pipe_screen *pscreen)
  96 {
  97         struct vc4_screen *screen = vc4_screen(pscreen);
  98
  99         util_hash_table_destroy(screen->bo_handles);
 100         vc4_bufmgr_destroy(pscreen);
 101         slab_destroy_parent(&screen->transfer_pool);
 102
 103 #if USE_VC4_SIMULATOR
 104         vc4_simulator_destroy(screen);
 105 #endif
 106
 107         close(screen->fd);
 108         ralloc_free(pscreen);
 109 }
 110
 111 static int
 112 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 113 {
 114         switch (param) {
 115                 /* Supported features (boolean caps). */
 116         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 117         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 118         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 119         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 120         case PIPE_CAP_NPOT_TEXTURES:
 121         case PIPE_CAP_SHAREABLE_SHADERS:
 122         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 123         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 124         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 125         case PIPE_CAP_TWO_SIDED_STENCIL:
 126         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 127         case PIPE_CAP_TEXTURE_SWIZZLE:
 128         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 129                 return 1;
 130
 131                 /* lying for GL 2.0 */
 132         case PIPE_CAP_OCCLUSION_QUERY:
 133         case PIPE_CAP_POINT_SPRITE:
 134                 return 1;
 135
 136         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 137                 return 256;
 138
 139         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 140                 return 120;
 141
 142         case PIPE_CAP_MAX_VIEWPORTS:
 143                 return 1;
 144
 145         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 146         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 147                 return 1;
 148
 149         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 150         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 151                 return 1;
 152
 153                 /* Unsupported features. */
 154         case PIPE_CAP_ANISOTROPIC_FILTER:
 155         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 156         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 157         case PIPE_CAP_CUBE_MAP_ARRAY:
 158         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 159         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 160         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 161         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 162         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 163         case PIPE_CAP_TGSI_INSTANCEID:
 164         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 165         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 166         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 167         case PIPE_CAP_COMPUTE:
 168         case PIPE_CAP_START_INSTANCE:
 169         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 170         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 171         case PIPE_CAP_TGSI_TEXCOORD:
 172         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 173         case PIPE_CAP_CONDITIONAL_RENDER:
 174         case PIPE_CAP_PRIMITIVE_RESTART:
 175         case PIPE_CAP_TEXTURE_BARRIER:
 176         case PIPE_CAP_SM3:
 177         case PIPE_CAP_INDEP_BLEND_ENABLE:
 178         case PIPE_CAP_INDEP_BLEND_FUNC:
 179         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 180         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 181         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 182         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 183         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 184         case PIPE_CAP_USER_VERTEX_BUFFERS:
 185         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 186         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 187         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 188         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 189         case PIPE_CAP_TEXTURE_GATHER_SM5:
 190         case PIPE_CAP_FAKE_SW_MSAA:
 191         case PIPE_CAP_TEXTURE_QUERY_LOD:
 192         case PIPE_CAP_SAMPLE_SHADING:
 193         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 194         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 195         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 196         case PIPE_CAP_MAX_TEXEL_OFFSET:
 197         case PIPE_CAP_MAX_VERTEX_STREAMS:
 198         case PIPE_CAP_DRAW_INDIRECT:
 199         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 200         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 201         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 202         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 203         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 204         case PIPE_CAP_CLIP_HALFZ:
 205         case PIPE_CAP_VERTEXID_NOBASE:
 206         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 207         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 208         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 209         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 210         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 211         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 212         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 213         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 214         case PIPE_CAP_TGSI_TXQS:
 215         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 216         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 217         case PIPE_CAP_CLEAR_TEXTURE:
 218         case PIPE_CAP_DRAW_PARAMETERS:
 219         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 220         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 221         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 222         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 223         case PIPE_CAP_INVALIDATE_BUFFER:
 224         case PIPE_CAP_GENERATE_MIPMAP:
 225         case PIPE_CAP_STRING_MARKER:
 226         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 227         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 228         case PIPE_CAP_QUERY_MEMORY_INFO:
 229         case PIPE_CAP_PCI_GROUP:
 230         case PIPE_CAP_PCI_BUS:
 231         case PIPE_CAP_PCI_DEVICE:
 232         case PIPE_CAP_PCI_FUNCTION:
 233         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 234         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 235         case PIPE_CAP_CULL_DISTANCE:
 236         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 237         case PIPE_CAP_TGSI_VOTE:
 238         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 239         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 240         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 241         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 242         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 243         case PIPE_CAP_NATIVE_FENCE_FD:
 244         case PIPE_CAP_TGSI_FS_FBFETCH:
 245         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 246         case PIPE_CAP_DOUBLES:
 247         case PIPE_CAP_INT64:
 248         case PIPE_CAP_INT64_DIVMOD:
 249                 return 0;
 250
 251                 /* Stream output. */
 252         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 253         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 254         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 255         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 256         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 257                 return 0;
 258
 259                 /* Geometry shader output, unsupported. */
 260         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 261         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 262                 return 0;
 263
 264                 /* Texturing. */
 265         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 266         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 267                 return VC4_MAX_MIP_LEVELS;
 268         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 269                 /* Note: Not supported in hardware, just faking it. */
 270                 return 5;
 271         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 272                 return 0;
 273
 274                 /* Render targets. */
 275         case PIPE_CAP_MAX_RENDER_TARGETS:
 276                 return 1;
 277
 278                 /* Queries. */
 279         case PIPE_CAP_QUERY_TIME_ELAPSED:
 280         case PIPE_CAP_QUERY_TIMESTAMP:
 281                 return 0;
 282
 283         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 284         case PIPE_CAP_MIN_TEXEL_OFFSET:
 285                 return 0;
 286
 287         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 288                 return 2048;
 289
 290         case PIPE_CAP_ENDIANNESS:
 291                 return PIPE_ENDIAN_LITTLE;
 292
 293         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 294                 return 64;
 295
 296         case PIPE_CAP_VENDOR_ID:
 297                 return 0x14E4;
 298         case PIPE_CAP_DEVICE_ID:
 299                 return 0xFFFFFFFF;
 300         case PIPE_CAP_ACCELERATED:
 301                 return 1;
 302         case PIPE_CAP_VIDEO_MEMORY: {
 303                 uint64_t system_memory;
 304
 305                 if (!os_get_total_physical_memory(&system_memory))
 306                         return 0;
 307
 308                 return (int)(system_memory >> 20);
 309         }
 310         case PIPE_CAP_UMA:
 311                 return 1;
 312
 313         default:
 314                 fprintf(stderr, "unknown param %d\n", param);
 315                 return 0;
 316         }
 317 }
 318
 319 static float
 320 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 321 {
 322         switch (param) {
 323         case PIPE_CAPF_MAX_LINE_WIDTH:
 324         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 325                 return 32;
 326
 327         case PIPE_CAPF_MAX_POINT_WIDTH:
 328         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 329                 return 512.0f;
 330
 331         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 332                 return 0.0f;
 333         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 334                 return 0.0f;
 335         case PIPE_CAPF_GUARD_BAND_LEFT:
 336         case PIPE_CAPF_GUARD_BAND_TOP:
 337         case PIPE_CAPF_GUARD_BAND_RIGHT:
 338         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 339                 return 0.0f;
 340         default:
 341                 fprintf(stderr, "unknown paramf %d\n", param);
 342                 return 0;
 343         }
 344 }
 345
 346 static int
 347 vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 348                            enum pipe_shader_cap param)
 349 {
 350         if (shader != PIPE_SHADER_VERTEX &&
 351             shader != PIPE_SHADER_FRAGMENT) {
 352                 return 0;
 353         }
 354
 355         /* this is probably not totally correct.. but it's a start: */
 356         switch (param) {
 357         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 358         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 359         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 360         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 361                 return 16384;
 362
 363         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 364                 return vc4_screen(pscreen)->has_control_flow;
 365
 366         case PIPE_SHADER_CAP_MAX_INPUTS:
 367                 return 8;
 368         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 369                 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
 370         case PIPE_SHADER_CAP_MAX_TEMPS:
 371                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 372         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 373                 return 16 * 1024 * sizeof(float);
 374         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 375                 return 1;
 376         case PIPE_SHADER_CAP_MAX_PREDS:
 377                 return 0; /* nothing uses this */
 378         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 379                 return 0;
 380         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 381         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 382         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 383                 return 0;
 384         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 385                 return 1;
 386         case PIPE_SHADER_CAP_SUBROUTINES:
 387                 return 0;
 388         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 389                 return 0;
 390         case PIPE_SHADER_CAP_INTEGERS:
 391                 return 1;
 392         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 393         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 394         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 395         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 396                 return 0;
 397         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 398         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 399                 return VC4_MAX_TEXTURE_SAMPLERS;
 400         case PIPE_SHADER_CAP_PREFERRED_IR:
 401                 return PIPE_SHADER_IR_NIR;
 402         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 403                 return 0;
 404         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 405                 return 32;
 406         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 407         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 408         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 409                 return 0;
 410         default:
 411                 fprintf(stderr, "unknown shader param %d\n", param);
 412                 return 0;
 413         }
 414         return 0;
 415 }
 416
 417 static boolean
 418 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
 419                                enum pipe_format format,
 420                                enum pipe_texture_target target,
 421                                unsigned sample_count,
 422                                unsigned usage)
 423 {
 424         struct vc4_screen *screen = vc4_screen(pscreen);
 425         unsigned retval = 0;
 426
 427         if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
 428                 return FALSE;
 429
 430         if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
 431             !util_format_is_supported(format, usage)) {
 432                 return FALSE;
 433         }
 434
 435         if (usage & PIPE_BIND_VERTEX_BUFFER) {
 436                 switch (format) {
 437                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 438                 case PIPE_FORMAT_R32G32B32_FLOAT:
 439                 case PIPE_FORMAT_R32G32_FLOAT:
 440                 case PIPE_FORMAT_R32_FLOAT:
 441                 case PIPE_FORMAT_R32G32B32A32_SNORM:
 442                 case PIPE_FORMAT_R32G32B32_SNORM:
 443                 case PIPE_FORMAT_R32G32_SNORM:
 444                 case PIPE_FORMAT_R32_SNORM:
 445                 case PIPE_FORMAT_R32G32B32A32_SSCALED:
 446                 case PIPE_FORMAT_R32G32B32_SSCALED:
 447                 case PIPE_FORMAT_R32G32_SSCALED:
 448                 case PIPE_FORMAT_R32_SSCALED:
 449                 case PIPE_FORMAT_R16G16B16A16_UNORM:
 450                 case PIPE_FORMAT_R16G16B16_UNORM:
 451                 case PIPE_FORMAT_R16G16_UNORM:
 452                 case PIPE_FORMAT_R16_UNORM:
 453                 case PIPE_FORMAT_R16G16B16A16_SNORM:
 454                 case PIPE_FORMAT_R16G16B16_SNORM:
 455                 case PIPE_FORMAT_R16G16_SNORM:
 456                 case PIPE_FORMAT_R16_SNORM:
 457                 case PIPE_FORMAT_R16G16B16A16_USCALED:
 458                 case PIPE_FORMAT_R16G16B16_USCALED:
 459                 case PIPE_FORMAT_R16G16_USCALED:
 460                 case PIPE_FORMAT_R16_USCALED:
 461                 case PIPE_FORMAT_R16G16B16A16_SSCALED:
 462                 case PIPE_FORMAT_R16G16B16_SSCALED:
 463                 case PIPE_FORMAT_R16G16_SSCALED:
 464                 case PIPE_FORMAT_R16_SSCALED:
 465                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 466                 case PIPE_FORMAT_R8G8B8_UNORM:
 467                 case PIPE_FORMAT_R8G8_UNORM:
 468                 case PIPE_FORMAT_R8_UNORM:
 469                 case PIPE_FORMAT_R8G8B8A8_SNORM:
 470                 case PIPE_FORMAT_R8G8B8_SNORM:
 471                 case PIPE_FORMAT_R8G8_SNORM:
 472                 case PIPE_FORMAT_R8_SNORM:
 473                 case PIPE_FORMAT_R8G8B8A8_USCALED:
 474                 case PIPE_FORMAT_R8G8B8_USCALED:
 475                 case PIPE_FORMAT_R8G8_USCALED:
 476                 case PIPE_FORMAT_R8_USCALED:
 477                 case PIPE_FORMAT_R8G8B8A8_SSCALED:
 478                 case PIPE_FORMAT_R8G8B8_SSCALED:
 479                 case PIPE_FORMAT_R8G8_SSCALED:
 480                 case PIPE_FORMAT_R8_SSCALED:
 481                         retval |= PIPE_BIND_VERTEX_BUFFER;
 482                         break;
 483                 default:
 484                         break;
 485                 }
 486         }
 487
 488         if ((usage & PIPE_BIND_RENDER_TARGET) &&
 489             vc4_rt_format_supported(format)) {
 490                 retval |= PIPE_BIND_RENDER_TARGET;
 491         }
 492
 493         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 494             vc4_tex_format_supported(format) &&
 495             (format != PIPE_FORMAT_ETC1_RGB8 || screen->has_etc1)) {
 496                 retval |= PIPE_BIND_SAMPLER_VIEW;
 497         }
 498
 499         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 500             (format == PIPE_FORMAT_S8_UINT_Z24_UNORM ||
 501              format == PIPE_FORMAT_X8Z24_UNORM)) {
 502                 retval |= PIPE_BIND_DEPTH_STENCIL;
 503         }
 504
 505         if ((usage & PIPE_BIND_INDEX_BUFFER) &&
 506             (format == PIPE_FORMAT_I8_UINT ||
 507              format == PIPE_FORMAT_I16_UINT)) {
 508                 retval |= PIPE_BIND_INDEX_BUFFER;
 509         }
 510
 511 #if 0
 512         if (retval != usage) {
 513                 fprintf(stderr,
 514                         "not supported: format=%s, target=%d, sample_count=%d, "
 515                         "usage=0x%x, retval=0x%x\n", util_format_name(format),
 516                         target, sample_count, usage, retval);
 517         }
 518 #endif
 519
 520         return retval == usage;
 521 }
 522
 523 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 524
 525 static unsigned handle_hash(void *key)
 526 {
 527     return PTR_TO_UINT(key);
 528 }
 529
 530 static int handle_compare(void *key1, void *key2)
 531 {
 532     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 533 }
 534
 535 static bool
 536 vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
 537 {
 538         struct drm_vc4_get_param p = {
 539                 .param = feature,
 540         };
 541         int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
 542
 543         if (ret != 0)
 544                 return false;
 545
 546         return p.value;
 547 }
 548
 549 static bool
 550 vc4_get_chip_info(struct vc4_screen *screen)
 551 {
 552         struct drm_vc4_get_param ident0 = {
 553                 .param = DRM_VC4_PARAM_V3D_IDENT0,
 554         };
 555         struct drm_vc4_get_param ident1 = {
 556                 .param = DRM_VC4_PARAM_V3D_IDENT1,
 557         };
 558         int ret;
 559
 560         ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
 561         if (ret != 0) {
 562                 if (errno == EINVAL) {
 563                         /* Backwards compatibility with 2835 kernels which
 564                          * only do V3D 2.1.
 565                          */
 566                         screen->v3d_ver = 21;
 567                         return true;
 568                 } else {
 569                         fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
 570                                 strerror(errno));
 571                         return false;
 572                 }
 573         }
 574         ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
 575         if (ret != 0) {
 576                 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
 577                         strerror(errno));
 578                 return false;
 579         }
 580
 581         uint32_t major = (ident0.value >> 24) & 0xff;
 582         uint32_t minor = (ident1.value >> 0) & 0xf;
 583         screen->v3d_ver = major * 10 + minor;
 584
 585         if (screen->v3d_ver != 21) {
 586                 fprintf(stderr,
 587                         "V3D %d.%d not supported by this version of Mesa.\n",
 588                         screen->v3d_ver / 10,
 589                         screen->v3d_ver % 10);
 590                 return false;
 591         }
 592
 593         return true;
 594 }
 595
 596 struct pipe_screen *
 597 vc4_screen_create(int fd)
 598 {
 599         struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
 600         struct pipe_screen *pscreen;
 601
 602         pscreen = &screen->base;
 603
 604         pscreen->destroy = vc4_screen_destroy;
 605         pscreen->get_param = vc4_screen_get_param;
 606         pscreen->get_paramf = vc4_screen_get_paramf;
 607         pscreen->get_shader_param = vc4_screen_get_shader_param;
 608         pscreen->context_create = vc4_context_create;
 609         pscreen->is_format_supported = vc4_screen_is_format_supported;
 610
 611         screen->fd = fd;
 612         list_inithead(&screen->bo_cache.time_list);
 613         pipe_mutex_init(screen->bo_handles_mutex);
 614         screen->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 615
 616         screen->has_control_flow =
 617                 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
 618         screen->has_etc1 =
 619                 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
 620         screen->has_threaded_fs =
 621                 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
 622
 623         if (!vc4_get_chip_info(screen))
 624                 goto fail;
 625
 626         slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
 627
 628         vc4_fence_init(screen);
 629
 630         vc4_debug = debug_get_option_vc4_debug();
 631         if (vc4_debug & VC4_DEBUG_SHADERDB)
 632                 vc4_debug |= VC4_DEBUG_NORAST;
 633
 634 #if USE_VC4_SIMULATOR
 635         vc4_simulator_init(screen);
 636 #endif
 637
 638         vc4_resource_screen_init(pscreen);
 639
 640         pscreen->get_name = vc4_screen_get_name;
 641         pscreen->get_vendor = vc4_screen_get_vendor;
 642         pscreen->get_device_vendor = vc4_screen_get_vendor;
 643         pscreen->get_compiler_options = vc4_screen_get_compiler_options;
 644
 645         return pscreen;
 646
 647 fail:
 648         close(fd);
 649         ralloc_free(pscreen);
 650         return NULL;
 651 }
 652
 653 boolean
 654 vc4_screen_bo_get_handle(struct pipe_screen *pscreen,
 655                          struct vc4_bo *bo,
 656                          unsigned stride,
 657                          struct winsys_handle *whandle)
 658 {
 659         whandle->stride = stride;
 660
 661         /* If we're passing some reference to our BO out to some other part of
 662          * the system, then we can't do any optimizations about only us being
 663          * the ones seeing it (like BO caching or shadow update avoidance).
 664          */
 665         bo->private = false;
 666
 667         switch (whandle->type) {
 668         case DRM_API_HANDLE_TYPE_SHARED:
 669                 return vc4_bo_flink(bo, &whandle->handle);
 670         case DRM_API_HANDLE_TYPE_KMS:
 671                 whandle->handle = bo->handle;
 672                 return TRUE;
 673         case DRM_API_HANDLE_TYPE_FD:
 674                 whandle->handle = vc4_bo_get_dmabuf(bo);
 675                 return whandle->handle != -1;
 676         }
 677
 678         return FALSE;
 679 }
 680
 681 struct vc4_bo *
 682 vc4_screen_bo_from_handle(struct pipe_screen *pscreen,
 683                           struct winsys_handle *whandle)
 684 {
 685         struct vc4_screen *screen = vc4_screen(pscreen);
 686
 687         if (whandle->offset != 0) {
 688                 fprintf(stderr,
 689                         "Attempt to import unsupported winsys offset %u\n",
 690                         whandle->offset);
 691                 return NULL;
 692         }
 693
 694         switch (whandle->type) {
 695         case DRM_API_HANDLE_TYPE_SHARED:
 696                 return vc4_bo_open_name(screen, whandle->handle, whandle->stride);
 697         case DRM_API_HANDLE_TYPE_FD:
 698                 return vc4_bo_open_dmabuf(screen, whandle->handle, whandle->stride);
 699         default:
 700                 fprintf(stderr,
 701                         "Attempt to import unsupported handle type %d\n",
 702                         whandle->type);
 703                 return NULL;
 704         }
 705 }