src/gallium/drivers/vc4/vc4_screen.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "os/os_misc.h"
  26 #include "pipe/p_defines.h"
  27 #include "pipe/p_screen.h"
  28 #include "pipe/p_state.h"
  29
  30 #include "util/u_cpu_detect.h"
  31 #include "util/u_debug.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_format.h"
  34 #include "util/u_hash_table.h"
  35 #include "util/ralloc.h"
  36
  37 #include <xf86drm.h>
  38 #include "drm_fourcc.h"
  39 #include "vc4_drm.h"
  40 #include "vc4_screen.h"
  41 #include "vc4_context.h"
  42 #include "vc4_resource.h"
  43
  44 static const struct debug_named_value debug_options[] = {
  45         { "cl",       VC4_DEBUG_CL,
  46           "Dump command list during creation" },
  47         { "surf",       VC4_DEBUG_SURFACE,
  48           "Dump surface layouts" },
  49         { "qpu",      VC4_DEBUG_QPU,
  50           "Dump generated QPU instructions" },
  51         { "qir",      VC4_DEBUG_QIR,
  52           "Dump QPU IR during program compile" },
  53         { "nir",      VC4_DEBUG_NIR,
  54           "Dump NIR during program compile" },
  55         { "tgsi",     VC4_DEBUG_TGSI,
  56           "Dump TGSI during program compile" },
  57         { "shaderdb", VC4_DEBUG_SHADERDB,
  58           "Dump program compile information for shader-db analysis" },
  59         { "perf",     VC4_DEBUG_PERF,
  60           "Print during performance-related events" },
  61         { "norast",   VC4_DEBUG_NORAST,
  62           "Skip actual hardware execution of commands" },
  63         { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
  64           "Flush after each draw call" },
  65         { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
  66           "Wait for finish after each flush" },
  67 #if USE_VC4_SIMULATOR
  68         { "dump", VC4_DEBUG_DUMP,
  69           "Write a GPU command stream trace file" },
  70 #endif
  71         { NULL }
  72 };
  73
  74 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", debug_options, 0)
  75 uint32_t vc4_debug;
  76
  77 static const char *
  78 vc4_screen_get_name(struct pipe_screen *pscreen)
  79 {
  80         struct vc4_screen *screen = vc4_screen(pscreen);
  81
  82         if (!screen->name) {
  83                 screen->name = ralloc_asprintf(screen,
  84                                                "VC4 V3D %d.%d",
  85                                                screen->v3d_ver / 10,
  86                                                screen->v3d_ver % 10);
  87         }
  88
  89         return screen->name;
  90 }
  91
  92 static const char *
  93 vc4_screen_get_vendor(struct pipe_screen *pscreen)
  94 {
  95         return "Broadcom";
  96 }
  97
  98 static void
  99 vc4_screen_destroy(struct pipe_screen *pscreen)
 100 {
 101         struct vc4_screen *screen = vc4_screen(pscreen);
 102
 103         util_hash_table_destroy(screen->bo_handles);
 104         vc4_bufmgr_destroy(pscreen);
 105         slab_destroy_parent(&screen->transfer_pool);
 106         free(screen->ro);
 107
 108 #if USE_VC4_SIMULATOR
 109         vc4_simulator_destroy(screen);
 110 #endif
 111
 112         close(screen->fd);
 113         ralloc_free(pscreen);
 114 }
 115
 116 static int
 117 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 118 {
 119         switch (param) {
 120                 /* Supported features (boolean caps). */
 121         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 122         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 123         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 124         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 125         case PIPE_CAP_NPOT_TEXTURES:
 126         case PIPE_CAP_SHAREABLE_SHADERS:
 127         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 128         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 129         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 130         case PIPE_CAP_TWO_SIDED_STENCIL:
 131         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 132         case PIPE_CAP_TEXTURE_SWIZZLE:
 133         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 134         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 135         case PIPE_CAP_TEXTURE_BARRIER:
 136                 return 1;
 137
 138                 /* lying for GL 2.0 */
 139         case PIPE_CAP_OCCLUSION_QUERY:
 140         case PIPE_CAP_POINT_SPRITE:
 141                 return 1;
 142
 143         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 144                 return 256;
 145
 146         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 147                 return 120;
 148
 149         case PIPE_CAP_MAX_VIEWPORTS:
 150                 return 1;
 151
 152         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 153         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 154                 return 1;
 155
 156         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 157         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 158                 return 1;
 159
 160                 /* Unsupported features. */
 161         case PIPE_CAP_ANISOTROPIC_FILTER:
 162         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 163         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 164         case PIPE_CAP_CUBE_MAP_ARRAY:
 165         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 166         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 167         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 168         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 169         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 170         case PIPE_CAP_TGSI_INSTANCEID:
 171         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 172         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 173         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 174         case PIPE_CAP_COMPUTE:
 175         case PIPE_CAP_START_INSTANCE:
 176         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 177         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 178         case PIPE_CAP_TGSI_TEXCOORD:
 179         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 180         case PIPE_CAP_CONDITIONAL_RENDER:
 181         case PIPE_CAP_PRIMITIVE_RESTART:
 182         case PIPE_CAP_SM3:
 183         case PIPE_CAP_INDEP_BLEND_ENABLE:
 184         case PIPE_CAP_INDEP_BLEND_FUNC:
 185         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 186         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 187         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 188         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 189         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 190         case PIPE_CAP_USER_VERTEX_BUFFERS:
 191         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 192         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 193         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 194         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 195         case PIPE_CAP_TEXTURE_GATHER_SM5:
 196         case PIPE_CAP_FAKE_SW_MSAA:
 197         case PIPE_CAP_TEXTURE_QUERY_LOD:
 198         case PIPE_CAP_SAMPLE_SHADING:
 199         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 200         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 201         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 202         case PIPE_CAP_MAX_TEXEL_OFFSET:
 203         case PIPE_CAP_MAX_VERTEX_STREAMS:
 204         case PIPE_CAP_DRAW_INDIRECT:
 205         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 206         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 207         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 208         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 209         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 210         case PIPE_CAP_CLIP_HALFZ:
 211         case PIPE_CAP_VERTEXID_NOBASE:
 212         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 213         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 214         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 215         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 216         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 217         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 218         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 219         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 220         case PIPE_CAP_TGSI_TXQS:
 221         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 222         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 223         case PIPE_CAP_CLEAR_TEXTURE:
 224         case PIPE_CAP_DRAW_PARAMETERS:
 225         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 226         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 227         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 228         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 229         case PIPE_CAP_INVALIDATE_BUFFER:
 230         case PIPE_CAP_GENERATE_MIPMAP:
 231         case PIPE_CAP_STRING_MARKER:
 232         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 233         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 234         case PIPE_CAP_QUERY_MEMORY_INFO:
 235         case PIPE_CAP_PCI_GROUP:
 236         case PIPE_CAP_PCI_BUS:
 237         case PIPE_CAP_PCI_DEVICE:
 238         case PIPE_CAP_PCI_FUNCTION:
 239         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 240         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 241         case PIPE_CAP_CULL_DISTANCE:
 242         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 243         case PIPE_CAP_TGSI_VOTE:
 244         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 245         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 246         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 247         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 248         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 249         case PIPE_CAP_NATIVE_FENCE_FD:
 250         case PIPE_CAP_TGSI_FS_FBFETCH:
 251         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 252         case PIPE_CAP_DOUBLES:
 253         case PIPE_CAP_INT64:
 254         case PIPE_CAP_INT64_DIVMOD:
 255         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 256         case PIPE_CAP_TGSI_CLOCK:
 257         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 258         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 259         case PIPE_CAP_TGSI_BALLOT:
 260         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 261         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 262         case PIPE_CAP_POST_DEPTH_COVERAGE:
 263         case PIPE_CAP_BINDLESS_TEXTURE:
 264         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 265         case PIPE_CAP_QUERY_SO_OVERFLOW:
 266         case PIPE_CAP_MEMOBJ:
 267         case PIPE_CAP_LOAD_CONSTBUF:
 268         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 269                 return 0;
 270
 271                 /* Stream output. */
 272         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 273         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 274         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 275         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 276         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 277                 return 0;
 278
 279                 /* Geometry shader output, unsupported. */
 280         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 281         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 282                 return 0;
 283
 284                 /* Texturing. */
 285         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 286         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 287                 return VC4_MAX_MIP_LEVELS;
 288         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 289                 /* Note: Not supported in hardware, just faking it. */
 290                 return 5;
 291         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 292                 return 0;
 293
 294                 /* Render targets. */
 295         case PIPE_CAP_MAX_RENDER_TARGETS:
 296                 return 1;
 297
 298                 /* Queries. */
 299         case PIPE_CAP_QUERY_TIME_ELAPSED:
 300         case PIPE_CAP_QUERY_TIMESTAMP:
 301                 return 0;
 302
 303         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 304         case PIPE_CAP_MIN_TEXEL_OFFSET:
 305                 return 0;
 306
 307         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 308                 return 2048;
 309
 310         case PIPE_CAP_ENDIANNESS:
 311                 return PIPE_ENDIAN_LITTLE;
 312
 313         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 314                 return 64;
 315
 316         case PIPE_CAP_VENDOR_ID:
 317                 return 0x14E4;
 318         case PIPE_CAP_DEVICE_ID:
 319                 return 0xFFFFFFFF;
 320         case PIPE_CAP_ACCELERATED:
 321                 return 1;
 322         case PIPE_CAP_VIDEO_MEMORY: {
 323                 uint64_t system_memory;
 324
 325                 if (!os_get_total_physical_memory(&system_memory))
 326                         return 0;
 327
 328                 return (int)(system_memory >> 20);
 329         }
 330         case PIPE_CAP_UMA:
 331                 return 1;
 332
 333         default:
 334                 fprintf(stderr, "unknown param %d\n", param);
 335                 return 0;
 336         }
 337 }
 338
 339 static float
 340 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 341 {
 342         switch (param) {
 343         case PIPE_CAPF_MAX_LINE_WIDTH:
 344         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 345                 return 32;
 346
 347         case PIPE_CAPF_MAX_POINT_WIDTH:
 348         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 349                 return 512.0f;
 350
 351         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 352                 return 0.0f;
 353         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 354                 return 0.0f;
 355         case PIPE_CAPF_GUARD_BAND_LEFT:
 356         case PIPE_CAPF_GUARD_BAND_TOP:
 357         case PIPE_CAPF_GUARD_BAND_RIGHT:
 358         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 359                 return 0.0f;
 360         default:
 361                 fprintf(stderr, "unknown paramf %d\n", param);
 362                 return 0;
 363         }
 364 }
 365
 366 static int
 367 vc4_screen_get_shader_param(struct pipe_screen *pscreen,
 368                             enum pipe_shader_type shader,
 369                             enum pipe_shader_cap param)
 370 {
 371         if (shader != PIPE_SHADER_VERTEX &&
 372             shader != PIPE_SHADER_FRAGMENT) {
 373                 return 0;
 374         }
 375
 376         /* this is probably not totally correct.. but it's a start: */
 377         switch (param) {
 378         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 379         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 380         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 381         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 382                 return 16384;
 383
 384         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 385                 return vc4_screen(pscreen)->has_control_flow;
 386
 387         case PIPE_SHADER_CAP_MAX_INPUTS:
 388                 return 8;
 389         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 390                 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
 391         case PIPE_SHADER_CAP_MAX_TEMPS:
 392                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 393         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 394                 return 16 * 1024 * sizeof(float);
 395         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 396                 return 1;
 397         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 398                 return 0;
 399         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 400         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 401         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 402                 return 0;
 403         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 404                 return 1;
 405         case PIPE_SHADER_CAP_SUBROUTINES:
 406                 return 0;
 407         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 408                 return 0;
 409         case PIPE_SHADER_CAP_INTEGERS:
 410                 return 1;
 411         case PIPE_SHADER_CAP_INT64_ATOMICS:
 412         case PIPE_SHADER_CAP_FP16:
 413         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 414         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 415         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 416         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 417         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 418                 return 0;
 419         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 420         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 421                 return VC4_MAX_TEXTURE_SAMPLERS;
 422         case PIPE_SHADER_CAP_PREFERRED_IR:
 423                 return PIPE_SHADER_IR_NIR;
 424         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 425                 return 0;
 426         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 427                 return 32;
 428         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 429         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 430         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 431         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 432                 return 0;
 433         default:
 434                 fprintf(stderr, "unknown shader param %d\n", param);
 435                 return 0;
 436         }
 437         return 0;
 438 }
 439
 440 static boolean
 441 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
 442                                enum pipe_format format,
 443                                enum pipe_texture_target target,
 444                                unsigned sample_count,
 445                                unsigned usage)
 446 {
 447         struct vc4_screen *screen = vc4_screen(pscreen);
 448         unsigned retval = 0;
 449
 450         if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
 451                 return FALSE;
 452
 453         if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
 454             !util_format_is_supported(format, usage)) {
 455                 return FALSE;
 456         }
 457
 458         if (usage & PIPE_BIND_VERTEX_BUFFER) {
 459                 switch (format) {
 460                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 461                 case PIPE_FORMAT_R32G32B32_FLOAT:
 462                 case PIPE_FORMAT_R32G32_FLOAT:
 463                 case PIPE_FORMAT_R32_FLOAT:
 464                 case PIPE_FORMAT_R32G32B32A32_SNORM:
 465                 case PIPE_FORMAT_R32G32B32_SNORM:
 466                 case PIPE_FORMAT_R32G32_SNORM:
 467                 case PIPE_FORMAT_R32_SNORM:
 468                 case PIPE_FORMAT_R32G32B32A32_SSCALED:
 469                 case PIPE_FORMAT_R32G32B32_SSCALED:
 470                 case PIPE_FORMAT_R32G32_SSCALED:
 471                 case PIPE_FORMAT_R32_SSCALED:
 472                 case PIPE_FORMAT_R16G16B16A16_UNORM:
 473                 case PIPE_FORMAT_R16G16B16_UNORM:
 474                 case PIPE_FORMAT_R16G16_UNORM:
 475                 case PIPE_FORMAT_R16_UNORM:
 476                 case PIPE_FORMAT_R16G16B16A16_SNORM:
 477                 case PIPE_FORMAT_R16G16B16_SNORM:
 478                 case PIPE_FORMAT_R16G16_SNORM:
 479                 case PIPE_FORMAT_R16_SNORM:
 480                 case PIPE_FORMAT_R16G16B16A16_USCALED:
 481                 case PIPE_FORMAT_R16G16B16_USCALED:
 482                 case PIPE_FORMAT_R16G16_USCALED:
 483                 case PIPE_FORMAT_R16_USCALED:
 484                 case PIPE_FORMAT_R16G16B16A16_SSCALED:
 485                 case PIPE_FORMAT_R16G16B16_SSCALED:
 486                 case PIPE_FORMAT_R16G16_SSCALED:
 487                 case PIPE_FORMAT_R16_SSCALED:
 488                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 489                 case PIPE_FORMAT_R8G8B8_UNORM:
 490                 case PIPE_FORMAT_R8G8_UNORM:
 491                 case PIPE_FORMAT_R8_UNORM:
 492                 case PIPE_FORMAT_R8G8B8A8_SNORM:
 493                 case PIPE_FORMAT_R8G8B8_SNORM:
 494                 case PIPE_FORMAT_R8G8_SNORM:
 495                 case PIPE_FORMAT_R8_SNORM:
 496                 case PIPE_FORMAT_R8G8B8A8_USCALED:
 497                 case PIPE_FORMAT_R8G8B8_USCALED:
 498                 case PIPE_FORMAT_R8G8_USCALED:
 499                 case PIPE_FORMAT_R8_USCALED:
 500                 case PIPE_FORMAT_R8G8B8A8_SSCALED:
 501                 case PIPE_FORMAT_R8G8B8_SSCALED:
 502                 case PIPE_FORMAT_R8G8_SSCALED:
 503                 case PIPE_FORMAT_R8_SSCALED:
 504                         retval |= PIPE_BIND_VERTEX_BUFFER;
 505                         break;
 506                 default:
 507                         break;
 508                 }
 509         }
 510
 511         if ((usage & PIPE_BIND_RENDER_TARGET) &&
 512             vc4_rt_format_supported(format)) {
 513                 retval |= PIPE_BIND_RENDER_TARGET;
 514         }
 515
 516         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 517             vc4_tex_format_supported(format) &&
 518             (format != PIPE_FORMAT_ETC1_RGB8 || screen->has_etc1)) {
 519                 retval |= PIPE_BIND_SAMPLER_VIEW;
 520         }
 521
 522         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 523             (format == PIPE_FORMAT_S8_UINT_Z24_UNORM ||
 524              format == PIPE_FORMAT_X8Z24_UNORM)) {
 525                 retval |= PIPE_BIND_DEPTH_STENCIL;
 526         }
 527
 528         if ((usage & PIPE_BIND_INDEX_BUFFER) &&
 529             (format == PIPE_FORMAT_I8_UINT ||
 530              format == PIPE_FORMAT_I16_UINT)) {
 531                 retval |= PIPE_BIND_INDEX_BUFFER;
 532         }
 533
 534 #if 0
 535         if (retval != usage) {
 536                 fprintf(stderr,
 537                         "not supported: format=%s, target=%d, sample_count=%d, "
 538                         "usage=0x%x, retval=0x%x\n", util_format_name(format),
 539                         target, sample_count, usage, retval);
 540         }
 541 #endif
 542
 543         return retval == usage;
 544 }
 545
 546 static void
 547 vc4_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 548                                   enum pipe_format format, int max,
 549                                   uint64_t *modifiers,
 550                                   unsigned int *external_only,
 551                                   int *count)
 552 {
 553         int m, i;
 554         uint64_t available_modifiers[] = {
 555                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
 556                 DRM_FORMAT_MOD_LINEAR,
 557         };
 558         struct vc4_screen *screen = vc4_screen(pscreen);
 559         int num_modifiers = screen->has_tiling_ioctl ? 2 : 1;
 560
 561         if (!modifiers) {
 562                 *count = num_modifiers;
 563                 return;
 564         }
 565
 566         *count = MIN2(max, num_modifiers);
 567         m = screen->has_tiling_ioctl ? 0 : 1;
 568         /* We support both modifiers (tiled and linear) for all sampler
 569          * formats, but if we don't have the DRM_VC4_GET_TILING ioctl
 570          * we shouldn't advertise the tiled formats.
 571          */
 572         for (i = 0; i < *count; i++) {
 573                 modifiers[i] = available_modifiers[m++];
 574                 if (external_only)
 575                         external_only[i] = false;
 576        }
 577 }
 578
 579 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 580
 581 static unsigned handle_hash(void *key)
 582 {
 583     return PTR_TO_UINT(key);
 584 }
 585
 586 static int handle_compare(void *key1, void *key2)
 587 {
 588     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 589 }
 590
 591 static bool
 592 vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
 593 {
 594         struct drm_vc4_get_param p = {
 595                 .param = feature,
 596         };
 597         int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
 598
 599         if (ret != 0)
 600                 return false;
 601
 602         return p.value;
 603 }
 604
 605 static bool
 606 vc4_get_chip_info(struct vc4_screen *screen)
 607 {
 608         struct drm_vc4_get_param ident0 = {
 609                 .param = DRM_VC4_PARAM_V3D_IDENT0,
 610         };
 611         struct drm_vc4_get_param ident1 = {
 612                 .param = DRM_VC4_PARAM_V3D_IDENT1,
 613         };
 614         int ret;
 615
 616         ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
 617         if (ret != 0) {
 618                 if (errno == EINVAL) {
 619                         /* Backwards compatibility with 2835 kernels which
 620                          * only do V3D 2.1.
 621                          */
 622                         screen->v3d_ver = 21;
 623                         return true;
 624                 } else {
 625                         fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
 626                                 strerror(errno));
 627                         return false;
 628                 }
 629         }
 630         ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
 631         if (ret != 0) {
 632                 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
 633                         strerror(errno));
 634                 return false;
 635         }
 636
 637         uint32_t major = (ident0.value >> 24) & 0xff;
 638         uint32_t minor = (ident1.value >> 0) & 0xf;
 639         screen->v3d_ver = major * 10 + minor;
 640
 641         if (screen->v3d_ver != 21 && screen->v3d_ver != 26) {
 642                 fprintf(stderr,
 643                         "V3D %d.%d not supported by this version of Mesa.\n",
 644                         screen->v3d_ver / 10,
 645                         screen->v3d_ver % 10);
 646                 return false;
 647         }
 648
 649         return true;
 650 }
 651
 652 struct pipe_screen *
 653 vc4_screen_create(int fd, struct renderonly *ro)
 654 {
 655         struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
 656         struct pipe_screen *pscreen;
 657
 658         pscreen = &screen->base;
 659
 660         pscreen->destroy = vc4_screen_destroy;
 661         pscreen->get_param = vc4_screen_get_param;
 662         pscreen->get_paramf = vc4_screen_get_paramf;
 663         pscreen->get_shader_param = vc4_screen_get_shader_param;
 664         pscreen->context_create = vc4_context_create;
 665         pscreen->is_format_supported = vc4_screen_is_format_supported;
 666
 667         screen->fd = fd;
 668         if (ro) {
 669                 screen->ro = renderonly_dup(ro);
 670                 if (!screen->ro) {
 671                         fprintf(stderr, "Failed to dup renderonly object\n");
 672                         ralloc_free(screen);
 673                         return NULL;
 674                 }
 675         }
 676
 677         list_inithead(&screen->bo_cache.time_list);
 678         (void) mtx_init(&screen->bo_handles_mutex, mtx_plain);
 679         screen->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 680
 681         screen->has_control_flow =
 682                 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
 683         screen->has_etc1 =
 684                 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
 685         screen->has_threaded_fs =
 686                 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
 687
 688         if (!vc4_get_chip_info(screen))
 689                 goto fail;
 690
 691         util_cpu_detect();
 692
 693         slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
 694
 695         vc4_fence_init(screen);
 696
 697         vc4_debug = debug_get_option_vc4_debug();
 698         if (vc4_debug & VC4_DEBUG_SHADERDB)
 699                 vc4_debug |= VC4_DEBUG_NORAST;
 700
 701 #if USE_VC4_SIMULATOR
 702         vc4_simulator_init(screen);
 703 #endif
 704
 705         vc4_resource_screen_init(pscreen);
 706
 707         pscreen->get_name = vc4_screen_get_name;
 708         pscreen->get_vendor = vc4_screen_get_vendor;
 709         pscreen->get_device_vendor = vc4_screen_get_vendor;
 710         pscreen->get_compiler_options = vc4_screen_get_compiler_options;
 711         pscreen->query_dmabuf_modifiers = vc4_screen_query_dmabuf_modifiers;
 712
 713         return pscreen;
 714
 715 fail:
 716         close(fd);
 717         ralloc_free(pscreen);
 718         return NULL;
 719 }