2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "os/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
30 #include "util/u_cpu_detect.h"
31 #include "util/u_debug.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_hash_table.h"
35 #include "util/u_screen.h"
36 #include "util/ralloc.h"
39 #include "drm_fourcc.h"
41 #include "vc4_screen.h"
42 #include "vc4_context.h"
43 #include "vc4_resource.h"
45 static const struct debug_named_value debug_options
[] = {
47 "Dump command list during creation" },
48 { "surf", VC4_DEBUG_SURFACE
,
49 "Dump surface layouts" },
50 { "qpu", VC4_DEBUG_QPU
,
51 "Dump generated QPU instructions" },
52 { "qir", VC4_DEBUG_QIR
,
53 "Dump QPU IR during program compile" },
54 { "nir", VC4_DEBUG_NIR
,
55 "Dump NIR during program compile" },
56 { "tgsi", VC4_DEBUG_TGSI
,
57 "Dump TGSI during program compile" },
58 { "shaderdb", VC4_DEBUG_SHADERDB
,
59 "Dump program compile information for shader-db analysis" },
60 { "perf", VC4_DEBUG_PERF
,
61 "Print during performance-related events" },
62 { "norast", VC4_DEBUG_NORAST
,
63 "Skip actual hardware execution of commands" },
64 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH
,
65 "Flush after each draw call" },
66 { "always_sync", VC4_DEBUG_ALWAYS_SYNC
,
67 "Wait for finish after each flush" },
68 #ifdef USE_VC4_SIMULATOR
69 { "dump", VC4_DEBUG_DUMP
,
70 "Write a GPU command stream trace file" },
75 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug
, "VC4_DEBUG", debug_options
, 0)
79 vc4_screen_get_name(struct pipe_screen
*pscreen
)
81 struct vc4_screen
*screen
= vc4_screen(pscreen
);
84 screen
->name
= ralloc_asprintf(screen
,
87 screen
->v3d_ver
% 10);
94 vc4_screen_get_vendor(struct pipe_screen
*pscreen
)
100 vc4_screen_destroy(struct pipe_screen
*pscreen
)
102 struct vc4_screen
*screen
= vc4_screen(pscreen
);
104 util_hash_table_destroy(screen
->bo_handles
);
105 vc4_bufmgr_destroy(pscreen
);
106 slab_destroy_parent(&screen
->transfer_pool
);
109 #ifdef USE_VC4_SIMULATOR
110 vc4_simulator_destroy(screen
);
114 ralloc_free(pscreen
);
118 vc4_has_feature(struct vc4_screen
*screen
, uint32_t feature
)
120 struct drm_vc4_get_param p
= {
123 int ret
= vc4_ioctl(screen
->fd
, DRM_IOCTL_VC4_GET_PARAM
, &p
);
132 vc4_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
134 struct vc4_screen
*screen
= vc4_screen(pscreen
);
137 /* Supported features (boolean caps). */
138 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
139 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
140 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
141 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
142 case PIPE_CAP_NPOT_TEXTURES
:
143 case PIPE_CAP_SHAREABLE_SHADERS
:
144 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
145 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
146 case PIPE_CAP_TEXTURE_SWIZZLE
:
147 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
148 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
149 case PIPE_CAP_TEXTURE_BARRIER
:
152 case PIPE_CAP_NATIVE_FENCE_FD
:
153 return screen
->has_syncobj
;
155 case PIPE_CAP_TILE_RASTER_ORDER
:
156 return vc4_has_feature(screen
,
157 DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER
);
159 /* lying for GL 2.0 */
160 case PIPE_CAP_OCCLUSION_QUERY
:
161 case PIPE_CAP_POINT_SPRITE
:
164 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
167 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
168 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
171 case PIPE_CAP_MAX_VIEWPORTS
:
174 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
175 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
178 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
179 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
182 /* Unsupported features. */
183 case PIPE_CAP_ANISOTROPIC_FILTER
:
184 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
185 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
186 case PIPE_CAP_CUBE_MAP_ARRAY
:
187 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
188 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
189 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
190 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
191 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
192 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
193 case PIPE_CAP_TGSI_INSTANCEID
:
194 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
195 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
196 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
197 case PIPE_CAP_COMPUTE
:
198 case PIPE_CAP_START_INSTANCE
:
199 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
200 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
201 case PIPE_CAP_TGSI_TEXCOORD
:
202 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
203 case PIPE_CAP_CONDITIONAL_RENDER
:
204 case PIPE_CAP_PRIMITIVE_RESTART
:
206 case PIPE_CAP_INDEP_BLEND_ENABLE
:
207 case PIPE_CAP_INDEP_BLEND_FUNC
:
208 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
209 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
210 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
211 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
212 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
213 case PIPE_CAP_USER_VERTEX_BUFFERS
:
214 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
215 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
216 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
217 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
218 case PIPE_CAP_TEXTURE_GATHER_SM5
:
219 case PIPE_CAP_FAKE_SW_MSAA
:
220 case PIPE_CAP_TEXTURE_QUERY_LOD
:
221 case PIPE_CAP_SAMPLE_SHADING
:
222 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
223 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
224 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
225 case PIPE_CAP_MAX_TEXEL_OFFSET
:
226 case PIPE_CAP_MAX_VERTEX_STREAMS
:
227 case PIPE_CAP_DRAW_INDIRECT
:
228 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
229 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
230 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
231 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
232 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
233 case PIPE_CAP_CLIP_HALFZ
:
234 case PIPE_CAP_VERTEXID_NOBASE
:
235 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
236 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
237 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
238 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
239 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
240 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
241 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
242 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
243 case PIPE_CAP_TGSI_TXQS
:
244 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
245 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
246 case PIPE_CAP_CLEAR_TEXTURE
:
247 case PIPE_CAP_DRAW_PARAMETERS
:
248 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
249 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
250 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
251 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
252 case PIPE_CAP_INVALIDATE_BUFFER
:
253 case PIPE_CAP_GENERATE_MIPMAP
:
254 case PIPE_CAP_STRING_MARKER
:
255 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
256 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
257 case PIPE_CAP_QUERY_MEMORY_INFO
:
258 case PIPE_CAP_PCI_GROUP
:
259 case PIPE_CAP_PCI_BUS
:
260 case PIPE_CAP_PCI_DEVICE
:
261 case PIPE_CAP_PCI_FUNCTION
:
262 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
263 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
264 case PIPE_CAP_CULL_DISTANCE
:
265 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
266 case PIPE_CAP_TGSI_VOTE
:
267 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
268 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
269 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
270 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
271 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
272 case PIPE_CAP_TGSI_FS_FBFETCH
:
273 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
274 case PIPE_CAP_DOUBLES
:
276 case PIPE_CAP_INT64_DIVMOD
:
277 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
278 case PIPE_CAP_TGSI_CLOCK
:
279 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
280 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
281 case PIPE_CAP_TGSI_BALLOT
:
282 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
283 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
284 case PIPE_CAP_POST_DEPTH_COVERAGE
:
285 case PIPE_CAP_BINDLESS_TEXTURE
:
286 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
287 case PIPE_CAP_QUERY_SO_OVERFLOW
:
288 case PIPE_CAP_MEMOBJ
:
289 case PIPE_CAP_LOAD_CONSTBUF
:
290 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
291 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
292 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
293 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
294 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
295 case PIPE_CAP_FENCE_SIGNAL
:
296 case PIPE_CAP_CONSTBUF0_FLAGS
:
297 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
298 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
299 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
300 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
301 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
302 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
303 case PIPE_CAP_PACKED_UNIFORMS
:
304 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
308 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
309 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
310 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
311 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
312 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
315 /* Geometry shader output, unsupported. */
316 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
317 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
318 case PIPE_CAP_MAX_GS_INVOCATIONS
:
320 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
324 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
325 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
326 return VC4_MAX_MIP_LEVELS
;
327 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
328 /* Note: Not supported in hardware, just faking it. */
330 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
333 /* Render targets. */
334 case PIPE_CAP_MAX_RENDER_TARGETS
:
338 case PIPE_CAP_QUERY_TIME_ELAPSED
:
339 case PIPE_CAP_QUERY_TIMESTAMP
:
342 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
343 case PIPE_CAP_MIN_TEXEL_OFFSET
:
346 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
349 case PIPE_CAP_ENDIANNESS
:
350 return PIPE_ENDIAN_LITTLE
;
352 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
355 case PIPE_CAP_VENDOR_ID
:
357 case PIPE_CAP_DEVICE_ID
:
359 case PIPE_CAP_ACCELERATED
:
361 case PIPE_CAP_VIDEO_MEMORY
: {
362 uint64_t system_memory
;
364 if (!os_get_total_physical_memory(&system_memory
))
367 return (int)(system_memory
>> 20);
373 return u_pipe_screen_get_param_defaults(pscreen
, param
);
378 vc4_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
381 case PIPE_CAPF_MAX_LINE_WIDTH
:
382 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
385 case PIPE_CAPF_MAX_POINT_WIDTH
:
386 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
389 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
391 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
394 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
395 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
396 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
399 fprintf(stderr
, "unknown paramf %d\n", param
);
405 vc4_screen_get_shader_param(struct pipe_screen
*pscreen
,
406 enum pipe_shader_type shader
,
407 enum pipe_shader_cap param
)
409 if (shader
!= PIPE_SHADER_VERTEX
&&
410 shader
!= PIPE_SHADER_FRAGMENT
) {
414 /* this is probably not totally correct.. but it's a start: */
416 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
417 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
418 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
419 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
422 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
423 return vc4_screen(pscreen
)->has_control_flow
;
425 case PIPE_SHADER_CAP_MAX_INPUTS
:
427 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
428 return shader
== PIPE_SHADER_FRAGMENT
? 1 : 8;
429 case PIPE_SHADER_CAP_MAX_TEMPS
:
430 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
431 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
432 return 16 * 1024 * sizeof(float);
433 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
435 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
437 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
438 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
439 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
441 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
443 case PIPE_SHADER_CAP_SUBROUTINES
:
445 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
447 case PIPE_SHADER_CAP_INTEGERS
:
449 case PIPE_SHADER_CAP_INT64_ATOMICS
:
450 case PIPE_SHADER_CAP_FP16
:
451 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
452 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
453 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
454 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
455 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
457 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
458 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
459 return VC4_MAX_TEXTURE_SAMPLERS
;
460 case PIPE_SHADER_CAP_PREFERRED_IR
:
461 return PIPE_SHADER_IR_NIR
;
462 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
464 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
466 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
467 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
468 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
469 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
470 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
471 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
473 case PIPE_SHADER_CAP_SCALAR_ISA
:
476 fprintf(stderr
, "unknown shader param %d\n", param
);
483 vc4_screen_is_format_supported(struct pipe_screen
*pscreen
,
484 enum pipe_format format
,
485 enum pipe_texture_target target
,
486 unsigned sample_count
,
487 unsigned storage_sample_count
,
490 struct vc4_screen
*screen
= vc4_screen(pscreen
);
492 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
495 if (sample_count
> 1 && sample_count
!= VC4_MAX_SAMPLES
)
498 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
502 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
504 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
505 case PIPE_FORMAT_R32G32B32_FLOAT
:
506 case PIPE_FORMAT_R32G32_FLOAT
:
507 case PIPE_FORMAT_R32_FLOAT
:
508 case PIPE_FORMAT_R32G32B32A32_SNORM
:
509 case PIPE_FORMAT_R32G32B32_SNORM
:
510 case PIPE_FORMAT_R32G32_SNORM
:
511 case PIPE_FORMAT_R32_SNORM
:
512 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
513 case PIPE_FORMAT_R32G32B32_SSCALED
:
514 case PIPE_FORMAT_R32G32_SSCALED
:
515 case PIPE_FORMAT_R32_SSCALED
:
516 case PIPE_FORMAT_R16G16B16A16_UNORM
:
517 case PIPE_FORMAT_R16G16B16_UNORM
:
518 case PIPE_FORMAT_R16G16_UNORM
:
519 case PIPE_FORMAT_R16_UNORM
:
520 case PIPE_FORMAT_R16G16B16A16_SNORM
:
521 case PIPE_FORMAT_R16G16B16_SNORM
:
522 case PIPE_FORMAT_R16G16_SNORM
:
523 case PIPE_FORMAT_R16_SNORM
:
524 case PIPE_FORMAT_R16G16B16A16_USCALED
:
525 case PIPE_FORMAT_R16G16B16_USCALED
:
526 case PIPE_FORMAT_R16G16_USCALED
:
527 case PIPE_FORMAT_R16_USCALED
:
528 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
529 case PIPE_FORMAT_R16G16B16_SSCALED
:
530 case PIPE_FORMAT_R16G16_SSCALED
:
531 case PIPE_FORMAT_R16_SSCALED
:
532 case PIPE_FORMAT_R8G8B8A8_UNORM
:
533 case PIPE_FORMAT_R8G8B8_UNORM
:
534 case PIPE_FORMAT_R8G8_UNORM
:
535 case PIPE_FORMAT_R8_UNORM
:
536 case PIPE_FORMAT_R8G8B8A8_SNORM
:
537 case PIPE_FORMAT_R8G8B8_SNORM
:
538 case PIPE_FORMAT_R8G8_SNORM
:
539 case PIPE_FORMAT_R8_SNORM
:
540 case PIPE_FORMAT_R8G8B8A8_USCALED
:
541 case PIPE_FORMAT_R8G8B8_USCALED
:
542 case PIPE_FORMAT_R8G8_USCALED
:
543 case PIPE_FORMAT_R8_USCALED
:
544 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
545 case PIPE_FORMAT_R8G8B8_SSCALED
:
546 case PIPE_FORMAT_R8G8_SSCALED
:
547 case PIPE_FORMAT_R8_SSCALED
:
554 if ((usage
& PIPE_BIND_RENDER_TARGET
) &&
555 !vc4_rt_format_supported(format
)) {
559 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
560 (!vc4_tex_format_supported(format
) ||
561 (format
== PIPE_FORMAT_ETC1_RGB8
&& !screen
->has_etc1
))) {
565 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
566 format
!= PIPE_FORMAT_S8_UINT_Z24_UNORM
&&
567 format
!= PIPE_FORMAT_X8Z24_UNORM
) {
571 if ((usage
& PIPE_BIND_INDEX_BUFFER
) &&
572 format
!= PIPE_FORMAT_I8_UINT
&&
573 format
!= PIPE_FORMAT_I16_UINT
) {
581 vc4_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
582 enum pipe_format format
, int max
,
584 unsigned int *external_only
,
588 uint64_t available_modifiers
[] = {
589 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED
,
590 DRM_FORMAT_MOD_LINEAR
,
592 struct vc4_screen
*screen
= vc4_screen(pscreen
);
593 int num_modifiers
= screen
->has_tiling_ioctl
? 2 : 1;
596 *count
= num_modifiers
;
600 *count
= MIN2(max
, num_modifiers
);
601 m
= screen
->has_tiling_ioctl
? 0 : 1;
602 /* We support both modifiers (tiled and linear) for all sampler
603 * formats, but if we don't have the DRM_VC4_GET_TILING ioctl
604 * we shouldn't advertise the tiled formats.
606 for (i
= 0; i
< *count
; i
++) {
607 modifiers
[i
] = available_modifiers
[m
++];
609 external_only
[i
] = false;
613 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
615 static unsigned handle_hash(void *key
)
617 return PTR_TO_UINT(key
);
620 static int handle_compare(void *key1
, void *key2
)
622 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
626 vc4_get_chip_info(struct vc4_screen
*screen
)
628 struct drm_vc4_get_param ident0
= {
629 .param
= DRM_VC4_PARAM_V3D_IDENT0
,
631 struct drm_vc4_get_param ident1
= {
632 .param
= DRM_VC4_PARAM_V3D_IDENT1
,
636 ret
= vc4_ioctl(screen
->fd
, DRM_IOCTL_VC4_GET_PARAM
, &ident0
);
638 if (errno
== EINVAL
) {
639 /* Backwards compatibility with 2835 kernels which
642 screen
->v3d_ver
= 21;
645 fprintf(stderr
, "Couldn't get V3D IDENT0: %s\n",
650 ret
= vc4_ioctl(screen
->fd
, DRM_IOCTL_VC4_GET_PARAM
, &ident1
);
652 fprintf(stderr
, "Couldn't get V3D IDENT1: %s\n",
657 uint32_t major
= (ident0
.value
>> 24) & 0xff;
658 uint32_t minor
= (ident1
.value
>> 0) & 0xf;
659 screen
->v3d_ver
= major
* 10 + minor
;
661 if (screen
->v3d_ver
!= 21 && screen
->v3d_ver
!= 26) {
663 "V3D %d.%d not supported by this version of Mesa.\n",
664 screen
->v3d_ver
/ 10,
665 screen
->v3d_ver
% 10);
673 vc4_screen_create(int fd
, struct renderonly
*ro
)
675 struct vc4_screen
*screen
= rzalloc(NULL
, struct vc4_screen
);
676 uint64_t syncobj_cap
= 0;
677 struct pipe_screen
*pscreen
;
680 pscreen
= &screen
->base
;
682 pscreen
->destroy
= vc4_screen_destroy
;
683 pscreen
->get_param
= vc4_screen_get_param
;
684 pscreen
->get_paramf
= vc4_screen_get_paramf
;
685 pscreen
->get_shader_param
= vc4_screen_get_shader_param
;
686 pscreen
->context_create
= vc4_context_create
;
687 pscreen
->is_format_supported
= vc4_screen_is_format_supported
;
691 screen
->ro
= renderonly_dup(ro
);
693 fprintf(stderr
, "Failed to dup renderonly object\n");
699 list_inithead(&screen
->bo_cache
.time_list
);
700 (void) mtx_init(&screen
->bo_handles_mutex
, mtx_plain
);
701 screen
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
703 screen
->has_control_flow
=
704 vc4_has_feature(screen
, DRM_VC4_PARAM_SUPPORTS_BRANCHES
);
706 vc4_has_feature(screen
, DRM_VC4_PARAM_SUPPORTS_ETC1
);
707 screen
->has_threaded_fs
=
708 vc4_has_feature(screen
, DRM_VC4_PARAM_SUPPORTS_THREADED_FS
);
709 screen
->has_madvise
=
710 vc4_has_feature(screen
, DRM_VC4_PARAM_SUPPORTS_MADVISE
);
711 screen
->has_perfmon_ioctl
=
712 vc4_has_feature(screen
, DRM_VC4_PARAM_SUPPORTS_PERFMON
);
714 err
= drmGetCap(fd
, DRM_CAP_SYNCOBJ
, &syncobj_cap
);
715 if (err
== 0 && syncobj_cap
)
716 screen
->has_syncobj
= true;
718 if (!vc4_get_chip_info(screen
))
723 slab_create_parent(&screen
->transfer_pool
, sizeof(struct vc4_transfer
), 16);
725 vc4_fence_screen_init(screen
);
727 vc4_debug
= debug_get_option_vc4_debug();
728 if (vc4_debug
& VC4_DEBUG_SHADERDB
)
729 vc4_debug
|= VC4_DEBUG_NORAST
;
731 #ifdef USE_VC4_SIMULATOR
732 vc4_simulator_init(screen
);
735 vc4_resource_screen_init(pscreen
);
737 pscreen
->get_name
= vc4_screen_get_name
;
738 pscreen
->get_vendor
= vc4_screen_get_vendor
;
739 pscreen
->get_device_vendor
= vc4_screen_get_vendor
;
740 pscreen
->get_compiler_options
= vc4_screen_get_compiler_options
;
741 pscreen
->query_dmabuf_modifiers
= vc4_screen_query_dmabuf_modifiers
;
743 if (screen
->has_perfmon_ioctl
) {
744 pscreen
->get_driver_query_group_info
= vc4_get_driver_query_group_info
;
745 pscreen
->get_driver_query_info
= vc4_get_driver_query_info
;
752 ralloc_free(pscreen
);