2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "pipe/p_state.h"
26 #include "util/u_inlines.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29 #include "util/u_helpers.h"
31 #include "vc4_context.h"
34 vc4_generic_cso_state_create(const void *src
, uint32_t size
)
36 void *dst
= calloc(1, size
);
39 memcpy(dst
, src
, size
);
44 vc4_generic_cso_state_delete(struct pipe_context
*pctx
, void *hwcso
)
50 vc4_set_blend_color(struct pipe_context
*pctx
,
51 const struct pipe_blend_color
*blend_color
)
53 struct vc4_context
*vc4
= vc4_context(pctx
);
54 vc4
->blend_color
.f
= *blend_color
;
55 for (int i
= 0; i
< 4; i
++)
56 vc4
->blend_color
.ub
[i
] = float_to_ubyte(blend_color
->color
[i
]);
57 vc4
->dirty
|= VC4_DIRTY_BLEND_COLOR
;
61 vc4_set_stencil_ref(struct pipe_context
*pctx
,
62 const struct pipe_stencil_ref
*stencil_ref
)
64 struct vc4_context
*vc4
= vc4_context(pctx
);
65 vc4
->stencil_ref
=* stencil_ref
;
66 vc4
->dirty
|= VC4_DIRTY_STENCIL_REF
;
70 vc4_set_clip_state(struct pipe_context
*pctx
,
71 const struct pipe_clip_state
*clip
)
73 struct vc4_context
*vc4
= vc4_context(pctx
);
75 vc4
->dirty
|= VC4_DIRTY_CLIP
;
79 vc4_set_sample_mask(struct pipe_context
*pctx
, unsigned sample_mask
)
81 struct vc4_context
*vc4
= vc4_context(pctx
);
82 vc4
->sample_mask
= sample_mask
& ((1 << VC4_MAX_SAMPLES
) - 1);
83 vc4
->dirty
|= VC4_DIRTY_SAMPLE_MASK
;
87 float_to_187_half(float f
)
93 vc4_create_rasterizer_state(struct pipe_context
*pctx
,
94 const struct pipe_rasterizer_state
*cso
)
96 struct vc4_rasterizer_state
*so
;
98 so
= CALLOC_STRUCT(vc4_rasterizer_state
);
104 if (!(cso
->cull_face
& PIPE_FACE_FRONT
))
105 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT
;
106 if (!(cso
->cull_face
& PIPE_FACE_BACK
))
107 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK
;
109 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
112 so
->point_size
= MAX2(cso
->point_size
, .125f
);
115 so
->config_bits
[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES
;
117 if (cso
->offset_tri
) {
118 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET
;
120 so
->offset_units
= float_to_187_half(cso
->offset_units
);
121 so
->offset_factor
= float_to_187_half(cso
->offset_scale
);
124 if (cso
->multisample
)
125 so
->config_bits
[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X
;
130 /* Blend state is baked into shaders. */
132 vc4_create_blend_state(struct pipe_context
*pctx
,
133 const struct pipe_blend_state
*cso
)
135 return vc4_generic_cso_state_create(cso
, sizeof(*cso
));
139 * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
140 * values, so you don't have to do a separate writemask setup.
143 tlb_stencil_setup_writemask(uint8_t mask
)
150 default: return 0xff;
155 tlb_stencil_setup_bits(const struct pipe_stencil_state
*state
,
156 uint8_t writemask_bits
)
158 static const uint8_t op_map
[] = {
159 [PIPE_STENCIL_OP_ZERO
] = 0,
160 [PIPE_STENCIL_OP_KEEP
] = 1,
161 [PIPE_STENCIL_OP_REPLACE
] = 2,
162 [PIPE_STENCIL_OP_INCR
] = 3,
163 [PIPE_STENCIL_OP_DECR
] = 4,
164 [PIPE_STENCIL_OP_INVERT
] = 5,
165 [PIPE_STENCIL_OP_INCR_WRAP
] = 6,
166 [PIPE_STENCIL_OP_DECR_WRAP
] = 7,
170 if (writemask_bits
!= 0xff)
171 bits
|= writemask_bits
<< 28;
172 bits
|= op_map
[state
->zfail_op
] << 25;
173 bits
|= op_map
[state
->zpass_op
] << 22;
174 bits
|= op_map
[state
->fail_op
] << 19;
175 bits
|= state
->func
<< 16;
176 /* Ref is filled in at uniform upload time */
177 bits
|= state
->valuemask
<< 0;
183 vc4_create_depth_stencil_alpha_state(struct pipe_context
*pctx
,
184 const struct pipe_depth_stencil_alpha_state
*cso
)
186 struct vc4_depth_stencil_alpha_state
*so
;
188 so
= CALLOC_STRUCT(vc4_depth_stencil_alpha_state
);
194 /* We always keep the early Z state correct, since a later state using
195 * early Z may want it.
197 so
->config_bits
[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE
;
199 if (cso
->depth
.enabled
) {
200 if (cso
->depth
.writemask
) {
201 so
->config_bits
[1] |= VC4_CONFIG_BITS_Z_UPDATE
;
203 so
->config_bits
[1] |= (cso
->depth
.func
<<
204 VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT
);
206 /* We only handle early Z in the < direction because otherwise
207 * we'd have to runtime guess which direction to set in the
210 if ((cso
->depth
.func
== PIPE_FUNC_LESS
||
211 cso
->depth
.func
== PIPE_FUNC_LEQUAL
) &&
212 (!cso
->stencil
[0].enabled
||
213 (cso
->stencil
[0].zfail_op
== PIPE_STENCIL_OP_KEEP
&&
214 (!cso
->stencil
[1].enabled
||
215 cso
->stencil
[1].zfail_op
== PIPE_STENCIL_OP_KEEP
)))) {
216 so
->config_bits
[2] |= VC4_CONFIG_BITS_EARLY_Z
;
219 so
->config_bits
[1] |= (PIPE_FUNC_ALWAYS
<<
220 VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT
);
223 if (cso
->stencil
[0].enabled
) {
224 const struct pipe_stencil_state
*front
= &cso
->stencil
[0];
225 const struct pipe_stencil_state
*back
= &cso
->stencil
[1];
227 uint8_t front_writemask_bits
=
228 tlb_stencil_setup_writemask(front
->writemask
);
229 uint8_t back_writemask
= front
->writemask
;
230 uint8_t back_writemask_bits
= front_writemask_bits
;
232 so
->stencil_uniforms
[0] =
233 tlb_stencil_setup_bits(front
, front_writemask_bits
);
235 back_writemask
= back
->writemask
;
236 back_writemask_bits
=
237 tlb_stencil_setup_writemask(back
->writemask
);
239 so
->stencil_uniforms
[0] |= (1 << 30);
240 so
->stencil_uniforms
[1] =
241 tlb_stencil_setup_bits(back
, back_writemask_bits
);
242 so
->stencil_uniforms
[1] |= (2 << 30);
244 so
->stencil_uniforms
[0] |= (3 << 30);
247 if (front_writemask_bits
== 0xff ||
248 back_writemask_bits
== 0xff) {
249 so
->stencil_uniforms
[2] = (front
->writemask
|
250 (back_writemask
<< 8));
258 vc4_set_polygon_stipple(struct pipe_context
*pctx
,
259 const struct pipe_poly_stipple
*stipple
)
261 struct vc4_context
*vc4
= vc4_context(pctx
);
262 vc4
->stipple
= *stipple
;
263 vc4
->dirty
|= VC4_DIRTY_STIPPLE
;
267 vc4_set_scissor_states(struct pipe_context
*pctx
,
269 unsigned num_scissors
,
270 const struct pipe_scissor_state
*scissor
)
272 struct vc4_context
*vc4
= vc4_context(pctx
);
274 vc4
->scissor
= *scissor
;
275 vc4
->dirty
|= VC4_DIRTY_SCISSOR
;
279 vc4_set_viewport_states(struct pipe_context
*pctx
,
281 unsigned num_viewports
,
282 const struct pipe_viewport_state
*viewport
)
284 struct vc4_context
*vc4
= vc4_context(pctx
);
285 vc4
->viewport
= *viewport
;
286 vc4
->dirty
|= VC4_DIRTY_VIEWPORT
;
290 vc4_set_vertex_buffers(struct pipe_context
*pctx
,
291 unsigned start_slot
, unsigned count
,
292 const struct pipe_vertex_buffer
*vb
)
294 struct vc4_context
*vc4
= vc4_context(pctx
);
295 struct vc4_vertexbuf_stateobj
*so
= &vc4
->vertexbuf
;
297 util_set_vertex_buffers_mask(so
->vb
, &so
->enabled_mask
, vb
,
299 so
->count
= util_last_bit(so
->enabled_mask
);
301 vc4
->dirty
|= VC4_DIRTY_VTXBUF
;
305 vc4_blend_state_bind(struct pipe_context
*pctx
, void *hwcso
)
307 struct vc4_context
*vc4
= vc4_context(pctx
);
309 vc4
->dirty
|= VC4_DIRTY_BLEND
;
313 vc4_rasterizer_state_bind(struct pipe_context
*pctx
, void *hwcso
)
315 struct vc4_context
*vc4
= vc4_context(pctx
);
316 struct vc4_rasterizer_state
*rast
= hwcso
;
318 if (vc4
->rasterizer
&& rast
&&
319 vc4
->rasterizer
->base
.flatshade
!= rast
->base
.flatshade
) {
320 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
323 vc4
->rasterizer
= hwcso
;
324 vc4
->dirty
|= VC4_DIRTY_RASTERIZER
;
328 vc4_zsa_state_bind(struct pipe_context
*pctx
, void *hwcso
)
330 struct vc4_context
*vc4
= vc4_context(pctx
);
332 vc4
->dirty
|= VC4_DIRTY_ZSA
;
336 vc4_vertex_state_create(struct pipe_context
*pctx
, unsigned num_elements
,
337 const struct pipe_vertex_element
*elements
)
339 struct vc4_vertex_stateobj
*so
= CALLOC_STRUCT(vc4_vertex_stateobj
);
344 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
345 so
->num_elements
= num_elements
;
351 vc4_vertex_state_bind(struct pipe_context
*pctx
, void *hwcso
)
353 struct vc4_context
*vc4
= vc4_context(pctx
);
355 vc4
->dirty
|= VC4_DIRTY_VTXSTATE
;
359 vc4_set_constant_buffer(struct pipe_context
*pctx
,
360 enum pipe_shader_type shader
, uint index
,
361 const struct pipe_constant_buffer
*cb
)
363 struct vc4_context
*vc4
= vc4_context(pctx
);
364 struct vc4_constbuf_stateobj
*so
= &vc4
->constbuf
[shader
];
368 /* Note that the state tracker can unbind constant buffers by
372 so
->enabled_mask
&= ~(1 << index
);
373 so
->dirty_mask
&= ~(1 << index
);
378 so
->cb
[index
].buffer_offset
= cb
->buffer_offset
;
379 so
->cb
[index
].buffer_size
= cb
->buffer_size
;
380 so
->cb
[index
].user_buffer
= cb
->user_buffer
;
382 so
->enabled_mask
|= 1 << index
;
383 so
->dirty_mask
|= 1 << index
;
384 vc4
->dirty
|= VC4_DIRTY_CONSTBUF
;
388 vc4_set_framebuffer_state(struct pipe_context
*pctx
,
389 const struct pipe_framebuffer_state
*framebuffer
)
391 struct vc4_context
*vc4
= vc4_context(pctx
);
392 struct pipe_framebuffer_state
*cso
= &vc4
->framebuffer
;
397 for (i
= 0; i
< framebuffer
->nr_cbufs
; i
++)
398 pipe_surface_reference(&cso
->cbufs
[i
], framebuffer
->cbufs
[i
]);
399 for (; i
< vc4
->framebuffer
.nr_cbufs
; i
++)
400 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
402 cso
->nr_cbufs
= framebuffer
->nr_cbufs
;
404 pipe_surface_reference(&cso
->zsbuf
, framebuffer
->zsbuf
);
406 cso
->width
= framebuffer
->width
;
407 cso
->height
= framebuffer
->height
;
409 /* Nonzero texture mipmap levels are laid out as if they were in
410 * power-of-two-sized spaces. The renderbuffer config infers its
411 * stride from the width parameter, so we need to configure our
412 * framebuffer. Note that if the z/color buffers were mismatched
413 * sizes, we wouldn't be able to do this.
415 if (cso
->cbufs
[0] && cso
->cbufs
[0]->u
.tex
.level
) {
416 struct vc4_resource
*rsc
=
417 vc4_resource(cso
->cbufs
[0]->texture
);
419 (rsc
->slices
[cso
->cbufs
[0]->u
.tex
.level
].stride
/
421 } else if (cso
->zsbuf
&& cso
->zsbuf
->u
.tex
.level
){
422 struct vc4_resource
*rsc
=
423 vc4_resource(cso
->zsbuf
->texture
);
425 (rsc
->slices
[cso
->zsbuf
->u
.tex
.level
].stride
/
429 vc4
->dirty
|= VC4_DIRTY_FRAMEBUFFER
;
432 static struct vc4_texture_stateobj
*
433 vc4_get_stage_tex(struct vc4_context
*vc4
, enum pipe_shader_type shader
)
436 case PIPE_SHADER_FRAGMENT
:
437 vc4
->dirty
|= VC4_DIRTY_FRAGTEX
;
438 return &vc4
->fragtex
;
440 case PIPE_SHADER_VERTEX
:
441 vc4
->dirty
|= VC4_DIRTY_VERTTEX
;
442 return &vc4
->verttex
;
445 fprintf(stderr
, "Unknown shader target %d\n", shader
);
450 static uint32_t translate_wrap(uint32_t p_wrap
, bool using_nearest
)
453 case PIPE_TEX_WRAP_REPEAT
:
455 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
457 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
459 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
461 case PIPE_TEX_WRAP_CLAMP
:
462 return (using_nearest
? 1 : 3);
464 fprintf(stderr
, "Unknown wrap mode %d\n", p_wrap
);
465 assert(!"not reached");
471 vc4_create_sampler_state(struct pipe_context
*pctx
,
472 const struct pipe_sampler_state
*cso
)
474 static const uint8_t minfilter_map
[6] = {
475 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR
,
476 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR
,
477 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN
,
478 VC4_TEX_P1_MINFILT_LIN_MIP_LIN
,
479 VC4_TEX_P1_MINFILT_NEAREST
,
480 VC4_TEX_P1_MINFILT_LINEAR
,
482 static const uint32_t magfilter_map
[] = {
483 [PIPE_TEX_FILTER_NEAREST
] = VC4_TEX_P1_MAGFILT_NEAREST
,
484 [PIPE_TEX_FILTER_LINEAR
] = VC4_TEX_P1_MAGFILT_LINEAR
,
486 bool either_nearest
=
487 (cso
->mag_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
||
488 cso
->min_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
);
489 struct vc4_sampler_state
*so
= CALLOC_STRUCT(vc4_sampler_state
);
494 memcpy(so
, cso
, sizeof(*cso
));
497 (VC4_SET_FIELD(magfilter_map
[cso
->mag_img_filter
],
498 VC4_TEX_P1_MAGFILT
) |
499 VC4_SET_FIELD(minfilter_map
[cso
->min_mip_filter
* 2 +
500 cso
->min_img_filter
],
501 VC4_TEX_P1_MINFILT
) |
502 VC4_SET_FIELD(translate_wrap(cso
->wrap_s
, either_nearest
),
504 VC4_SET_FIELD(translate_wrap(cso
->wrap_t
, either_nearest
),
511 vc4_sampler_states_bind(struct pipe_context
*pctx
,
512 enum pipe_shader_type shader
, unsigned start
,
513 unsigned nr
, void **hwcso
)
515 struct vc4_context
*vc4
= vc4_context(pctx
);
516 struct vc4_texture_stateobj
*stage_tex
= vc4_get_stage_tex(vc4
, shader
);
522 for (i
= 0; i
< nr
; i
++) {
525 stage_tex
->samplers
[i
] = hwcso
[i
];
528 for (; i
< stage_tex
->num_samplers
; i
++) {
529 stage_tex
->samplers
[i
] = NULL
;
532 stage_tex
->num_samplers
= new_nr
;
535 static struct pipe_sampler_view
*
536 vc4_create_sampler_view(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
537 const struct pipe_sampler_view
*cso
)
539 struct vc4_sampler_view
*so
= CALLOC_STRUCT(vc4_sampler_view
);
540 struct vc4_resource
*rsc
= vc4_resource(prsc
);
547 pipe_reference(NULL
, &prsc
->reference
);
549 /* There is no hardware level clamping, and the start address of a
550 * texture may be misaligned, so in that case we have to copy to a
553 * Also, Raspberry Pi doesn't support sampling from raster textures,
554 * so we also have to copy to a temporary then.
556 if ((cso
->u
.tex
.first_level
&&
557 (cso
->u
.tex
.first_level
!= cso
->u
.tex
.last_level
)) ||
558 rsc
->vc4_format
== VC4_TEXTURE_TYPE_RGBA32R
) {
559 struct vc4_resource
*shadow_parent
= vc4_resource(prsc
);
560 struct pipe_resource tmpl
= shadow_parent
->base
.b
;
561 struct vc4_resource
*clone
;
563 tmpl
.bind
= PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_RENDER_TARGET
;
564 tmpl
.width0
= u_minify(tmpl
.width0
, cso
->u
.tex
.first_level
);
565 tmpl
.height0
= u_minify(tmpl
.height0
, cso
->u
.tex
.first_level
);
566 tmpl
.last_level
= cso
->u
.tex
.last_level
- cso
->u
.tex
.first_level
;
568 prsc
= vc4_resource_create(pctx
->screen
, &tmpl
);
573 rsc
= vc4_resource(prsc
);
574 clone
= vc4_resource(prsc
);
575 clone
->shadow_parent
= &shadow_parent
->base
.b
;
576 /* Flag it as needing update of the contents from the parent. */
577 clone
->writes
= shadow_parent
->writes
- 1;
579 assert(clone
->vc4_format
!= VC4_TEXTURE_TYPE_RGBA32R
);
580 } else if (cso
->u
.tex
.first_level
) {
581 so
->force_first_level
= true;
583 so
->base
.texture
= prsc
;
584 so
->base
.reference
.count
= 1;
585 so
->base
.context
= pctx
;
588 (VC4_SET_FIELD(rsc
->slices
[0].offset
>> 12, VC4_TEX_P0_OFFSET
) |
589 VC4_SET_FIELD(rsc
->vc4_format
& 15, VC4_TEX_P0_TYPE
) |
590 VC4_SET_FIELD(so
->force_first_level
?
591 cso
->u
.tex
.last_level
:
592 cso
->u
.tex
.last_level
-
593 cso
->u
.tex
.first_level
, VC4_TEX_P0_MIPLVLS
) |
594 VC4_SET_FIELD(cso
->target
== PIPE_TEXTURE_CUBE
,
597 (VC4_SET_FIELD(rsc
->vc4_format
>> 4, VC4_TEX_P1_TYPE4
) |
598 VC4_SET_FIELD(prsc
->height0
& 2047, VC4_TEX_P1_HEIGHT
) |
599 VC4_SET_FIELD(prsc
->width0
& 2047, VC4_TEX_P1_WIDTH
));
601 if (prsc
->format
== PIPE_FORMAT_ETC1_RGB8
)
602 so
->texture_p1
|= VC4_TEX_P1_ETCFLIP_MASK
;
608 vc4_sampler_view_destroy(struct pipe_context
*pctx
,
609 struct pipe_sampler_view
*view
)
611 pipe_resource_reference(&view
->texture
, NULL
);
616 vc4_set_sampler_views(struct pipe_context
*pctx
,
617 enum pipe_shader_type shader
,
618 unsigned start
, unsigned nr
,
619 struct pipe_sampler_view
**views
)
621 struct vc4_context
*vc4
= vc4_context(pctx
);
622 struct vc4_texture_stateobj
*stage_tex
= vc4_get_stage_tex(vc4
, shader
);
628 for (i
= 0; i
< nr
; i
++) {
631 pipe_sampler_view_reference(&stage_tex
->textures
[i
], views
[i
]);
634 for (; i
< stage_tex
->num_textures
; i
++) {
635 pipe_sampler_view_reference(&stage_tex
->textures
[i
], NULL
);
638 stage_tex
->num_textures
= new_nr
;
642 vc4_state_init(struct pipe_context
*pctx
)
644 pctx
->set_blend_color
= vc4_set_blend_color
;
645 pctx
->set_stencil_ref
= vc4_set_stencil_ref
;
646 pctx
->set_clip_state
= vc4_set_clip_state
;
647 pctx
->set_sample_mask
= vc4_set_sample_mask
;
648 pctx
->set_constant_buffer
= vc4_set_constant_buffer
;
649 pctx
->set_framebuffer_state
= vc4_set_framebuffer_state
;
650 pctx
->set_polygon_stipple
= vc4_set_polygon_stipple
;
651 pctx
->set_scissor_states
= vc4_set_scissor_states
;
652 pctx
->set_viewport_states
= vc4_set_viewport_states
;
654 pctx
->set_vertex_buffers
= vc4_set_vertex_buffers
;
656 pctx
->create_blend_state
= vc4_create_blend_state
;
657 pctx
->bind_blend_state
= vc4_blend_state_bind
;
658 pctx
->delete_blend_state
= vc4_generic_cso_state_delete
;
660 pctx
->create_rasterizer_state
= vc4_create_rasterizer_state
;
661 pctx
->bind_rasterizer_state
= vc4_rasterizer_state_bind
;
662 pctx
->delete_rasterizer_state
= vc4_generic_cso_state_delete
;
664 pctx
->create_depth_stencil_alpha_state
= vc4_create_depth_stencil_alpha_state
;
665 pctx
->bind_depth_stencil_alpha_state
= vc4_zsa_state_bind
;
666 pctx
->delete_depth_stencil_alpha_state
= vc4_generic_cso_state_delete
;
668 pctx
->create_vertex_elements_state
= vc4_vertex_state_create
;
669 pctx
->delete_vertex_elements_state
= vc4_generic_cso_state_delete
;
670 pctx
->bind_vertex_elements_state
= vc4_vertex_state_bind
;
672 pctx
->create_sampler_state
= vc4_create_sampler_state
;
673 pctx
->delete_sampler_state
= vc4_generic_cso_state_delete
;
674 pctx
->bind_sampler_states
= vc4_sampler_states_bind
;
676 pctx
->create_sampler_view
= vc4_create_sampler_view
;
677 pctx
->sampler_view_destroy
= vc4_sampler_view_destroy
;
678 pctx
->set_sampler_views
= vc4_set_sampler_views
;