2 * Copyright © 2014-2017 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "broadcom/common/v3d_macros.h"
34 #include "pipe/p_context.h"
35 #include "pipe/p_state.h"
36 #include "util/bitset.h"
37 #include "util/slab.h"
40 #include "vc5_screen.h"
44 void vc5_job_add_bo(struct vc5_job
*job
, struct vc5_bo
*bo
);
46 #include "vc5_bufmgr.h"
47 #include "vc5_resource.h"
50 #ifdef USE_VC5_SIMULATOR
51 #define using_vc5_simulator true
53 #define using_vc5_simulator false
56 #define VC5_DIRTY_BLEND (1 << 0)
57 #define VC5_DIRTY_RASTERIZER (1 << 1)
58 #define VC5_DIRTY_ZSA (1 << 2)
59 #define VC5_DIRTY_FRAGTEX (1 << 3)
60 #define VC5_DIRTY_VERTTEX (1 << 4)
62 #define VC5_DIRTY_BLEND_COLOR (1 << 7)
63 #define VC5_DIRTY_STENCIL_REF (1 << 8)
64 #define VC5_DIRTY_SAMPLE_MASK (1 << 9)
65 #define VC5_DIRTY_FRAMEBUFFER (1 << 10)
66 #define VC5_DIRTY_STIPPLE (1 << 11)
67 #define VC5_DIRTY_VIEWPORT (1 << 12)
68 #define VC5_DIRTY_CONSTBUF (1 << 13)
69 #define VC5_DIRTY_VTXSTATE (1 << 14)
70 #define VC5_DIRTY_VTXBUF (1 << 15)
71 #define VC5_DIRTY_SCISSOR (1 << 17)
72 #define VC5_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
73 #define VC5_DIRTY_PRIM_MODE (1 << 19)
74 #define VC5_DIRTY_CLIP (1 << 20)
75 #define VC5_DIRTY_UNCOMPILED_VS (1 << 21)
76 #define VC5_DIRTY_UNCOMPILED_FS (1 << 22)
77 #define VC5_DIRTY_COMPILED_CS (1 << 23)
78 #define VC5_DIRTY_COMPILED_VS (1 << 24)
79 #define VC5_DIRTY_COMPILED_FS (1 << 25)
80 #define VC5_DIRTY_FS_INPUTS (1 << 26)
81 #define VC5_DIRTY_STREAMOUT (1 << 27)
82 #define VC5_DIRTY_OQ (1 << 28)
83 #define VC5_DIRTY_CENTROID_FLAGS (1 << 29)
85 #define VC5_MAX_FS_INPUTS 64
87 struct vc5_sampler_view
{
88 struct pipe_sampler_view base
;
91 /* Precomputed swizzles to pass in to the shader key. */
94 uint8_t texture_shader_state
[32];
95 /* V3D 4.x: Texture state struct. */
99 struct vc5_sampler_state
{
100 struct pipe_sampler_state base
;
104 /* V3D 3.x: Packed texture state. */
105 uint8_t texture_shader_state
[32];
106 /* V3D 4.x: Sampler state struct. */
110 struct vc5_texture_stateobj
{
111 struct pipe_sampler_view
*textures
[PIPE_MAX_SAMPLERS
];
112 unsigned num_textures
;
113 struct pipe_sampler_state
*samplers
[PIPE_MAX_SAMPLERS
];
114 unsigned num_samplers
;
115 struct vc5_cl_reloc texture_state
[PIPE_MAX_SAMPLERS
];
118 struct vc5_shader_uniform_info
{
119 enum quniform_contents
*contents
;
124 struct vc5_uncompiled_shader
{
125 /** A name for this program, so you can track it in shader-db output. */
127 /** How many variants of this program were compiled, for shader-db. */
128 uint32_t compiled_variant_count
;
129 struct pipe_shader_state base
;
130 uint32_t num_tf_outputs
;
131 struct v3d_varying_slot
*tf_outputs
;
132 uint16_t tf_specs
[16];
133 uint16_t tf_specs_psiz
[16];
134 uint32_t num_tf_specs
;
137 * Flag for if the NIR in this shader originally came from TGSI. If
138 * so, we need to do some fixups at compile time, due to missing
139 * information in TGSI that exists in NIR.
144 struct vc5_compiled_shader
{
148 struct v3d_prog_data
*base
;
149 struct v3d_vs_prog_data
*vs
;
150 struct v3d_fs_prog_data
*fs
;
154 * VC5_DIRTY_* flags that, when set in vc5->dirty, mean that the
155 * uniforms have to be rewritten (and therefore the shader state
158 uint32_t uniform_dirty_bits
;
161 struct vc5_program_stateobj
{
162 struct vc5_uncompiled_shader
*bind_vs
, *bind_fs
;
163 struct vc5_compiled_shader
*cs
, *vs
, *fs
;
165 struct vc5_bo
*spill_bo
;
166 int spill_size_per_thread
;
169 struct vc5_constbuf_stateobj
{
170 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
171 uint32_t enabled_mask
;
175 struct vc5_vertexbuf_stateobj
{
176 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
178 uint32_t enabled_mask
;
182 struct vc5_vertex_stateobj
{
183 struct pipe_vertex_element pipe
[VC5_MAX_ATTRIBUTES
];
184 unsigned num_elements
;
186 uint8_t attrs
[12 * VC5_MAX_ATTRIBUTES
];
187 struct vc5_bo
*default_attribute_values
;
190 struct vc5_streamout_stateobj
{
191 struct pipe_stream_output_target
*targets
[PIPE_MAX_SO_BUFFERS
];
192 unsigned num_targets
;
195 /* Hash table key for vc5->jobs */
197 struct pipe_surface
*cbufs
[4];
198 struct pipe_surface
*zsbuf
;
202 VC5_EZ_UNDECIDED
= 0,
209 * A complete bin/render job.
211 * This is all of the state necessary to submit a bin/render to the kernel.
212 * We want to be able to have multiple in progress at a time, so that we don't
213 * need to flush an existing CL just to switch to rendering to a new render
214 * target (which would mean reading back from the old render target when
215 * starting to render to it again).
218 struct vc5_context
*vc5
;
221 struct vc5_cl indirect
;
222 struct vc5_bo
*tile_alloc
;
223 struct vc5_bo
*tile_state
;
224 uint32_t shader_rec_count
;
226 struct drm_v3d_submit_cl submit
;
229 * Set of all BOs referenced by the job. This will be used for making
230 * the list of BOs that the kernel will need to have paged in to
235 /** Sum of the sizes of the BOs referenced by the job. */
236 uint32_t referenced_size
;
238 struct set
*write_prscs
;
240 /* Size of the submit.bo_handles array. */
241 uint32_t bo_handles_size
;
243 /** @{ Surfaces to submit rendering for. */
244 struct pipe_surface
*cbufs
[4];
245 struct pipe_surface
*zsbuf
;
248 * Bounding box of the scissor across all queued drawing.
250 * Note that the max values are exclusive.
258 * Width/height of the color framebuffer being rendered to,
259 * for VC5_TILE_RENDERING_MODE_CONFIG.
262 uint32_t draw_height
;
264 /** @{ Tile information, depending on MSAA and float color buffer. */
265 uint32_t draw_tiles_x
; /** @< Number of tiles wide for framebuffer. */
266 uint32_t draw_tiles_y
; /** @< Number of tiles high for framebuffer. */
268 uint32_t tile_width
; /** @< Width of a tile. */
269 uint32_t tile_height
; /** @< Height of a tile. */
270 /** maximum internal_bpp of all color render targets. */
271 uint32_t internal_bpp
;
273 /** Whether the current rendering is in a 4X MSAA tile buffer. */
277 /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
281 /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
282 * (either clears or draws).
285 uint32_t clear_color
[4][4];
290 * Set if some drawing (triangles, blits, or just a glClear()) has
291 * been done to the FBO, meaning that we need to
292 * DRM_IOCTL_VC5_SUBMIT_CL.
297 * Set if there is a nonzero address for OCCLUSION_QUERY_COUNTER. If
298 * so, we need to disable it and flush before ending the CL, to keep
299 * the next tile from starting with it enabled.
304 * Set when a packet enabling TF on all further primitives has been
310 * Current EZ state for drawing. Updated at the start of draw after
311 * we've decided on the shader being rendered.
313 enum vc5_ez_state ez_state
;
315 * The first EZ state that was used for drawing with a decided EZ
316 * direction (so either UNDECIDED, GT, or LT).
318 enum vc5_ez_state first_ez_state
;
321 * Number of draw calls (not counting full buffer clears) queued in
324 uint32_t draw_calls_queued
;
326 struct vc5_job_key key
;
330 struct pipe_context base
;
333 struct vc5_screen
*screen
;
335 /** The 3D rendering job for the currently bound FBO. */
338 /* Map from struct vc5_job_key to the job for that FBO.
340 struct hash_table
*jobs
;
343 * Map from vc5_resource to a job writing to that resource.
345 * Primarily for flushing jobs rendering to textures that are now
348 struct hash_table
*write_jobs
;
350 struct slab_child_pool transfer_pool
;
351 struct blitter_context
*blitter
;
353 /** bitfield of VC5_DIRTY_* */
356 struct primconvert_context
*primconvert
;
358 struct hash_table
*fs_cache
, *vs_cache
;
359 uint32_t next_uncompiled_program_id
;
360 uint64_t next_compiled_program_id
;
362 struct vc5_compiler_state
*compiler_state
;
366 /** Maximum index buffer valid for the current shader_rec. */
369 /** Sync object that our RCL will update as its out_sync. */
372 struct u_upload_mgr
*uploader
;
374 /** @{ Current pipeline state objects */
375 struct pipe_scissor_state scissor
;
376 struct pipe_blend_state
*blend
;
377 struct vc5_rasterizer_state
*rasterizer
;
378 struct vc5_depth_stencil_alpha_state
*zsa
;
380 struct vc5_texture_stateobj verttex
, fragtex
;
382 struct vc5_program_stateobj prog
;
384 struct vc5_vertex_stateobj
*vtx
;
387 struct pipe_blend_color f
;
390 struct pipe_stencil_ref stencil_ref
;
391 unsigned sample_mask
;
392 struct pipe_framebuffer_state framebuffer
;
394 /* Per render target, whether we should swap the R and B fields in the
395 * shader's color output and in blending. If render targets disagree
396 * on the R/B swap and use the constant color, then we would need to
397 * fall back to in-shader blending.
399 uint8_t swap_color_rb
;
401 /* Per render target, whether we should treat the dst alpha values as
404 * For RGBX formats, the tile buffer's alpha channel will be
407 uint8_t blend_dst_alpha_one
;
411 uint32_t tf_prims_generated
;
412 uint32_t prims_generated
;
414 struct pipe_poly_stipple stipple
;
415 struct pipe_clip_state clip
;
416 struct pipe_viewport_state viewport
;
417 struct vc5_constbuf_stateobj constbuf
[PIPE_SHADER_TYPES
];
418 struct vc5_vertexbuf_stateobj vertexbuf
;
419 struct vc5_streamout_stateobj streamout
;
420 struct vc5_bo
*current_oq
;
424 struct vc5_rasterizer_state
{
425 struct pipe_rasterizer_state base
;
427 /* VC5_CONFIGURATION_BITS */
428 uint8_t config_bits
[3];
433 * Half-float (1/8/7 bits) value of polygon offset units for
434 * VC5_PACKET_DEPTH_OFFSET
436 uint16_t offset_units
;
438 * Half-float (1/8/7 bits) value of polygon offset scale for
439 * VC5_PACKET_DEPTH_OFFSET
441 uint16_t offset_factor
;
444 struct vc5_depth_stencil_alpha_state
{
445 struct pipe_depth_stencil_alpha_state base
;
447 enum vc5_ez_state ez_state
;
449 /** Uniforms for stencil state.
451 * Index 0 is either the front config, or the front-and-back config.
452 * Index 1 is the back config if doing separate back stencil.
453 * Index 2 is the writemask config if it's not a common mask value.
455 uint32_t stencil_uniforms
[3];
457 uint8_t stencil_front
[6];
458 uint8_t stencil_back
[6];
461 #define perf_debug(...) do { \
462 if (unlikely(V3D_DEBUG & V3D_DEBUG_PERF)) \
463 fprintf(stderr, __VA_ARGS__); \
466 static inline struct vc5_context
*
467 vc5_context(struct pipe_context
*pcontext
)
469 return (struct vc5_context
*)pcontext
;
472 static inline struct vc5_sampler_view
*
473 vc5_sampler_view(struct pipe_sampler_view
*psview
)
475 return (struct vc5_sampler_view
*)psview
;
478 static inline struct vc5_sampler_state
*
479 vc5_sampler_state(struct pipe_sampler_state
*psampler
)
481 return (struct vc5_sampler_state
*)psampler
;
484 struct pipe_context
*vc5_context_create(struct pipe_screen
*pscreen
,
485 void *priv
, unsigned flags
);
486 void vc5_program_init(struct pipe_context
*pctx
);
487 void vc5_program_fini(struct pipe_context
*pctx
);
488 void vc5_query_init(struct pipe_context
*pctx
);
490 void vc5_simulator_init(struct vc5_screen
*screen
);
491 void vc5_simulator_destroy(struct vc5_screen
*screen
);
492 int vc5_simulator_flush(struct vc5_context
*vc5
,
493 struct drm_v3d_submit_cl
*args
,
494 struct vc5_job
*job
);
495 int vc5_simulator_ioctl(int fd
, unsigned long request
, void *arg
);
496 void vc5_simulator_open_from_handle(int fd
, uint32_t winsys_stride
,
497 int handle
, uint32_t size
);
500 vc5_ioctl(int fd
, unsigned long request
, void *arg
)
502 if (using_vc5_simulator
)
503 return vc5_simulator_ioctl(fd
, request
, arg
);
505 return drmIoctl(fd
, request
, arg
);
508 void vc5_set_shader_uniform_dirty_flags(struct vc5_compiled_shader
*shader
);
509 struct vc5_cl_reloc
vc5_write_uniforms(struct vc5_context
*vc5
,
510 struct vc5_compiled_shader
*shader
,
511 struct vc5_constbuf_stateobj
*cb
,
512 struct vc5_texture_stateobj
*texstate
);
514 void vc5_flush(struct pipe_context
*pctx
);
515 void vc5_job_init(struct vc5_context
*vc5
);
516 struct vc5_job
*vc5_get_job(struct vc5_context
*vc5
,
517 struct pipe_surface
**cbufs
,
518 struct pipe_surface
*zsbuf
);
519 struct vc5_job
*vc5_get_job_for_fbo(struct vc5_context
*vc5
);
520 void vc5_job_add_bo(struct vc5_job
*job
, struct vc5_bo
*bo
);
521 void vc5_job_add_write_resource(struct vc5_job
*job
, struct pipe_resource
*prsc
);
522 void vc5_job_submit(struct vc5_context
*vc5
, struct vc5_job
*job
);
523 void vc5_flush_jobs_writing_resource(struct vc5_context
*vc5
,
524 struct pipe_resource
*prsc
);
525 void vc5_flush_jobs_reading_resource(struct vc5_context
*vc5
,
526 struct pipe_resource
*prsc
);
527 void vc5_update_compiled_shaders(struct vc5_context
*vc5
, uint8_t prim_mode
);
529 bool vc5_rt_format_supported(const struct v3d_device_info
*devinfo
,
531 bool vc5_tex_format_supported(const struct v3d_device_info
*devinfo
,
533 uint8_t vc5_get_rt_format(const struct v3d_device_info
*devinfo
, enum pipe_format f
);
534 uint8_t vc5_get_tex_format(const struct v3d_device_info
*devinfo
, enum pipe_format f
);
535 uint8_t vc5_get_tex_return_size(const struct v3d_device_info
*devinfo
,
537 enum pipe_tex_compare compare
);
538 uint8_t vc5_get_tex_return_channels(const struct v3d_device_info
*devinfo
,
540 const uint8_t *vc5_get_format_swizzle(const struct v3d_device_info
*devinfo
,
542 void vc5_get_internal_type_bpp_for_output_format(const struct v3d_device_info
*devinfo
,
547 void vc5_init_query_functions(struct vc5_context
*vc5
);
548 void vc5_blit(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
);
549 void vc5_blitter_save(struct vc5_context
*vc5
);
551 struct vc5_fence
*vc5_fence_create(struct vc5_context
*vc5
);
554 # include "v3dx_context.h"
556 # define v3dX(x) v3d33_##x
557 # include "v3dx_context.h"
560 # define v3dX(x) v3d41_##x
561 # include "v3dx_context.h"
565 #endif /* VC5_CONTEXT_H */