c36495f646bc0186955966429b19492cd328ff26
[mesa.git] / src / gallium / drivers / vc5 / vc5_screen.c
1 /*
2 * Copyright © 2014-2017 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "os/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
29
30 #include "util/u_debug.h"
31 #include "util/u_memory.h"
32 #include "util/u_format.h"
33 #include "util/u_hash_table.h"
34 #include "util/ralloc.h"
35
36 #include <xf86drm.h>
37 #include "vc5_screen.h"
38 #include "vc5_context.h"
39 #include "vc5_resource.h"
40 #include "compiler/v3d_compiler.h"
41
42 static const char *
43 vc5_screen_get_name(struct pipe_screen *pscreen)
44 {
45 struct vc5_screen *screen = vc5_screen(pscreen);
46
47 if (!screen->name) {
48 screen->name = ralloc_asprintf(screen,
49 "VC5 V3D %d.%d",
50 screen->devinfo.ver / 10,
51 screen->devinfo.ver % 10);
52 }
53
54 return screen->name;
55 }
56
57 static const char *
58 vc5_screen_get_vendor(struct pipe_screen *pscreen)
59 {
60 return "Broadcom";
61 }
62
63 static void
64 vc5_screen_destroy(struct pipe_screen *pscreen)
65 {
66 struct vc5_screen *screen = vc5_screen(pscreen);
67
68 util_hash_table_destroy(screen->bo_handles);
69 vc5_bufmgr_destroy(pscreen);
70 slab_destroy_parent(&screen->transfer_pool);
71
72 if (using_vc5_simulator)
73 vc5_simulator_destroy(screen);
74
75 v3d_compiler_free(screen->compiler);
76
77 close(screen->fd);
78 ralloc_free(pscreen);
79 }
80
81 static int
82 vc5_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
83 {
84 struct vc5_screen *screen = vc5_screen(pscreen);
85
86 switch (param) {
87 /* Supported features (boolean caps). */
88 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
89 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
90 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
91 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
92 case PIPE_CAP_NPOT_TEXTURES:
93 case PIPE_CAP_SHAREABLE_SHADERS:
94 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
95 case PIPE_CAP_TEXTURE_MULTISAMPLE:
96 case PIPE_CAP_TEXTURE_SWIZZLE:
97 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
98 case PIPE_CAP_START_INSTANCE:
99 case PIPE_CAP_TGSI_INSTANCEID:
100 case PIPE_CAP_SM3:
101 case PIPE_CAP_TEXTURE_QUERY_LOD:
102 case PIPE_CAP_PRIMITIVE_RESTART:
103 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
104 case PIPE_CAP_OCCLUSION_QUERY:
105 case PIPE_CAP_POINT_SPRITE:
106 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
107 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
108 case PIPE_CAP_COMPUTE:
109 case PIPE_CAP_DRAW_INDIRECT:
110 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
111 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
112 return 1;
113
114 case PIPE_CAP_INDEP_BLEND_ENABLE:
115 return screen->devinfo.ver >= 40;
116
117 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
118 return 256;
119
120 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
121 return 4;
122
123 case PIPE_CAP_GLSL_FEATURE_LEVEL:
124 return 400;
125
126 case PIPE_CAP_MAX_VIEWPORTS:
127 return 1;
128
129 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
130 return 1;
131 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
132 return 0;
133 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
134 if (screen->devinfo.ver >= 40)
135 return 0;
136 else
137 return 1;
138 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
139 if (screen->devinfo.ver >= 40)
140 return 1;
141 else
142 return 0;
143
144 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
145 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
146 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
147 return 1;
148
149
150 /* Stream output. */
151 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
152 return 4;
153 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
154 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
155 return 64;
156
157 case PIPE_CAP_MIN_TEXEL_OFFSET:
158 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
159 return -8;
160 case PIPE_CAP_MAX_TEXEL_OFFSET:
161 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
162 return 7;
163
164 /* Unsupported features. */
165 case PIPE_CAP_ANISOTROPIC_FILTER:
166 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
167 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
168 case PIPE_CAP_CUBE_MAP_ARRAY:
169 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
170 case PIPE_CAP_SEAMLESS_CUBE_MAP:
171 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
172 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
173 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
174 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
175 case PIPE_CAP_SHADER_STENCIL_EXPORT:
176 case PIPE_CAP_TGSI_TEXCOORD:
177 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
178 case PIPE_CAP_CONDITIONAL_RENDER:
179 case PIPE_CAP_TEXTURE_BARRIER:
180 case PIPE_CAP_INDEP_BLEND_FUNC:
181 case PIPE_CAP_DEPTH_CLIP_DISABLE:
182 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
183 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
184 case PIPE_CAP_USER_VERTEX_BUFFERS:
185 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
186 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
187 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
188 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
189 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
190 case PIPE_CAP_TEXTURE_GATHER_SM5:
191 case PIPE_CAP_FAKE_SW_MSAA:
192 case PIPE_CAP_SAMPLE_SHADING:
193 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
194 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
195 case PIPE_CAP_MAX_VERTEX_STREAMS:
196 case PIPE_CAP_MULTI_DRAW_INDIRECT:
197 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
198 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
199 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
200 case PIPE_CAP_SAMPLER_VIEW_TARGET:
201 case PIPE_CAP_CLIP_HALFZ:
202 case PIPE_CAP_VERTEXID_NOBASE:
203 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
204 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
205 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
206 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
207 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
208 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
209 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
210 case PIPE_CAP_DEPTH_BOUNDS_TEST:
211 case PIPE_CAP_TGSI_TXQS:
212 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
213 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
214 case PIPE_CAP_CLEAR_TEXTURE:
215 case PIPE_CAP_DRAW_PARAMETERS:
216 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
217 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
218 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
219 case PIPE_CAP_INVALIDATE_BUFFER:
220 case PIPE_CAP_GENERATE_MIPMAP:
221 case PIPE_CAP_STRING_MARKER:
222 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
223 case PIPE_CAP_QUERY_BUFFER_OBJECT:
224 case PIPE_CAP_QUERY_MEMORY_INFO:
225 case PIPE_CAP_PCI_GROUP:
226 case PIPE_CAP_PCI_BUS:
227 case PIPE_CAP_PCI_DEVICE:
228 case PIPE_CAP_PCI_FUNCTION:
229 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
230 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
231 case PIPE_CAP_CULL_DISTANCE:
232 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
233 case PIPE_CAP_TGSI_VOTE:
234 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
235 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
236 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
237 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
238 case PIPE_CAP_TGSI_FS_FBFETCH:
239 case PIPE_CAP_INT64:
240 case PIPE_CAP_INT64_DIVMOD:
241 case PIPE_CAP_DOUBLES:
242 case PIPE_CAP_BINDLESS_TEXTURE:
243 case PIPE_CAP_POST_DEPTH_COVERAGE:
244 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
245 case PIPE_CAP_TGSI_BALLOT:
246 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
247 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
248 case PIPE_CAP_TGSI_CLOCK:
249 case PIPE_CAP_TGSI_TEX_TXF_LZ:
250 case PIPE_CAP_NATIVE_FENCE_FD:
251 case PIPE_CAP_FENCE_SIGNAL:
252 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
253 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
254 case PIPE_CAP_QUERY_SO_OVERFLOW:
255 case PIPE_CAP_MEMOBJ:
256 case PIPE_CAP_LOAD_CONSTBUF:
257 case PIPE_CAP_TILE_RASTER_ORDER:
258 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
259 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
260 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
261 case PIPE_CAP_CONSTBUF0_FLAGS:
262 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
263 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
264 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
265 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
266 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
267 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
268 case PIPE_CAP_PACKED_UNIFORMS:
269 return 0;
270
271 /* Geometry shader output, unsupported. */
272 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
273 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
274 return 0;
275
276 /* Texturing. */
277 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
278 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
279 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
280 return VC5_MAX_MIP_LEVELS;
281 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
282 return 2048;
283
284 /* Render targets. */
285 case PIPE_CAP_MAX_RENDER_TARGETS:
286 return 4;
287
288 /* Queries. */
289 case PIPE_CAP_QUERY_TIME_ELAPSED:
290 case PIPE_CAP_QUERY_TIMESTAMP:
291 return 0;
292
293 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
294 return 2048;
295
296 case PIPE_CAP_ENDIANNESS:
297 return PIPE_ENDIAN_LITTLE;
298
299 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
300 return 64;
301
302 case PIPE_CAP_VENDOR_ID:
303 return 0x14E4;
304 case PIPE_CAP_DEVICE_ID:
305 return 0xFFFFFFFF;
306 case PIPE_CAP_ACCELERATED:
307 return 1;
308 case PIPE_CAP_VIDEO_MEMORY: {
309 uint64_t system_memory;
310
311 if (!os_get_total_physical_memory(&system_memory))
312 return 0;
313
314 return (int)(system_memory >> 20);
315 }
316 case PIPE_CAP_UMA:
317 return 1;
318
319 default:
320 fprintf(stderr, "unknown param %d\n", param);
321 return 0;
322 }
323 }
324
325 static float
326 vc5_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
327 {
328 switch (param) {
329 case PIPE_CAPF_MAX_LINE_WIDTH:
330 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
331 return 32;
332
333 case PIPE_CAPF_MAX_POINT_WIDTH:
334 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
335 return 512.0f;
336
337 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
338 return 0.0f;
339 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
340 return 16.0f;
341
342 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
343 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
344 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
345 return 0.0f;
346 default:
347 fprintf(stderr, "unknown paramf %d\n", param);
348 return 0;
349 }
350 }
351
352 static int
353 vc5_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
354 enum pipe_shader_cap param)
355 {
356 if (shader != PIPE_SHADER_VERTEX &&
357 shader != PIPE_SHADER_FRAGMENT) {
358 return 0;
359 }
360
361 /* this is probably not totally correct.. but it's a start: */
362 switch (param) {
363 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
364 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
365 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
366 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
367 return 16384;
368
369 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
370 return UINT_MAX;
371
372 case PIPE_SHADER_CAP_MAX_INPUTS:
373 if (shader == PIPE_SHADER_FRAGMENT)
374 return VC5_MAX_FS_INPUTS / 4;
375 else
376 return 16;
377 case PIPE_SHADER_CAP_MAX_OUTPUTS:
378 if (shader == PIPE_SHADER_FRAGMENT)
379 return 4;
380 else
381 return VC5_MAX_FS_INPUTS / 4;
382 case PIPE_SHADER_CAP_MAX_TEMPS:
383 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
384 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
385 return 16 * 1024 * sizeof(float);
386 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
387 return 16;
388 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
389 return 0;
390 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
391 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
392 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
393 return 0;
394 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
395 return 1;
396 case PIPE_SHADER_CAP_SUBROUTINES:
397 return 0;
398 case PIPE_SHADER_CAP_INTEGERS:
399 return 1;
400 case PIPE_SHADER_CAP_FP16:
401 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
402 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
403 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
404 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
405 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
406 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
407 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
408 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
409 return 0;
410 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
411 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
412 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
413 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
414 return VC5_MAX_TEXTURE_SAMPLERS;
415 case PIPE_SHADER_CAP_PREFERRED_IR:
416 return PIPE_SHADER_IR_NIR;
417 case PIPE_SHADER_CAP_SUPPORTED_IRS:
418 return 0;
419 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
420 return 32;
421 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
422 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
423 return 0;
424 default:
425 fprintf(stderr, "unknown shader param %d\n", param);
426 return 0;
427 }
428 return 0;
429 }
430
431 static boolean
432 vc5_screen_is_format_supported(struct pipe_screen *pscreen,
433 enum pipe_format format,
434 enum pipe_texture_target target,
435 unsigned sample_count,
436 unsigned usage)
437 {
438 struct vc5_screen *screen = vc5_screen(pscreen);
439
440 if (sample_count > 1 && sample_count != VC5_MAX_SAMPLES)
441 return FALSE;
442
443 if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
444 !util_format_is_supported(format, usage)) {
445 return FALSE;
446 }
447
448 if (usage & PIPE_BIND_VERTEX_BUFFER) {
449 switch (format) {
450 case PIPE_FORMAT_R32G32B32A32_FLOAT:
451 case PIPE_FORMAT_R32G32B32_FLOAT:
452 case PIPE_FORMAT_R32G32_FLOAT:
453 case PIPE_FORMAT_R32_FLOAT:
454 case PIPE_FORMAT_R32G32B32A32_SNORM:
455 case PIPE_FORMAT_R32G32B32_SNORM:
456 case PIPE_FORMAT_R32G32_SNORM:
457 case PIPE_FORMAT_R32_SNORM:
458 case PIPE_FORMAT_R32G32B32A32_SSCALED:
459 case PIPE_FORMAT_R32G32B32_SSCALED:
460 case PIPE_FORMAT_R32G32_SSCALED:
461 case PIPE_FORMAT_R32_SSCALED:
462 case PIPE_FORMAT_R16G16B16A16_UNORM:
463 case PIPE_FORMAT_R16G16B16_UNORM:
464 case PIPE_FORMAT_R16G16_UNORM:
465 case PIPE_FORMAT_R16_UNORM:
466 case PIPE_FORMAT_R16G16B16A16_SNORM:
467 case PIPE_FORMAT_R16G16B16_SNORM:
468 case PIPE_FORMAT_R16G16_SNORM:
469 case PIPE_FORMAT_R16_SNORM:
470 case PIPE_FORMAT_R16G16B16A16_USCALED:
471 case PIPE_FORMAT_R16G16B16_USCALED:
472 case PIPE_FORMAT_R16G16_USCALED:
473 case PIPE_FORMAT_R16_USCALED:
474 case PIPE_FORMAT_R16G16B16A16_SSCALED:
475 case PIPE_FORMAT_R16G16B16_SSCALED:
476 case PIPE_FORMAT_R16G16_SSCALED:
477 case PIPE_FORMAT_R16_SSCALED:
478 case PIPE_FORMAT_R8G8B8A8_UNORM:
479 case PIPE_FORMAT_R8G8B8_UNORM:
480 case PIPE_FORMAT_R8G8_UNORM:
481 case PIPE_FORMAT_R8_UNORM:
482 case PIPE_FORMAT_R8G8B8A8_SNORM:
483 case PIPE_FORMAT_R8G8B8_SNORM:
484 case PIPE_FORMAT_R8G8_SNORM:
485 case PIPE_FORMAT_R8_SNORM:
486 case PIPE_FORMAT_R8G8B8A8_USCALED:
487 case PIPE_FORMAT_R8G8B8_USCALED:
488 case PIPE_FORMAT_R8G8_USCALED:
489 case PIPE_FORMAT_R8_USCALED:
490 case PIPE_FORMAT_R8G8B8A8_SSCALED:
491 case PIPE_FORMAT_R8G8B8_SSCALED:
492 case PIPE_FORMAT_R8G8_SSCALED:
493 case PIPE_FORMAT_R8_SSCALED:
494 case PIPE_FORMAT_R10G10B10A2_UNORM:
495 case PIPE_FORMAT_B10G10R10A2_UNORM:
496 case PIPE_FORMAT_R10G10B10A2_SNORM:
497 case PIPE_FORMAT_B10G10R10A2_SNORM:
498 case PIPE_FORMAT_R10G10B10A2_USCALED:
499 case PIPE_FORMAT_B10G10R10A2_USCALED:
500 case PIPE_FORMAT_R10G10B10A2_SSCALED:
501 case PIPE_FORMAT_B10G10R10A2_SSCALED:
502 break;
503 default:
504 return FALSE;
505 }
506 }
507
508 if ((usage & PIPE_BIND_RENDER_TARGET) &&
509 !vc5_rt_format_supported(&screen->devinfo, format)) {
510 return FALSE;
511 }
512
513 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
514 !vc5_tex_format_supported(&screen->devinfo, format)) {
515 return FALSE;
516 }
517
518 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
519 !(format == PIPE_FORMAT_S8_UINT_Z24_UNORM ||
520 format == PIPE_FORMAT_X8Z24_UNORM ||
521 format == PIPE_FORMAT_Z16_UNORM ||
522 format == PIPE_FORMAT_Z32_FLOAT ||
523 format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
524 return FALSE;
525 }
526
527 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
528 !(format == PIPE_FORMAT_I8_UINT ||
529 format == PIPE_FORMAT_I16_UINT ||
530 format == PIPE_FORMAT_I32_UINT)) {
531 return FALSE;
532 }
533
534 return TRUE;
535 }
536
537 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
538
539 static unsigned handle_hash(void *key)
540 {
541 return PTR_TO_UINT(key);
542 }
543
544 static int handle_compare(void *key1, void *key2)
545 {
546 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
547 }
548
549 static bool
550 vc5_get_device_info(struct vc5_screen *screen)
551 {
552 struct drm_v3d_get_param ident0 = {
553 .param = DRM_V3D_PARAM_V3D_CORE0_IDENT0,
554 };
555 struct drm_v3d_get_param ident1 = {
556 .param = DRM_V3D_PARAM_V3D_CORE0_IDENT1,
557 };
558 int ret;
559
560 ret = vc5_ioctl(screen->fd, DRM_IOCTL_V3D_GET_PARAM, &ident0);
561 if (ret != 0) {
562 fprintf(stderr, "Couldn't get V3D core IDENT0: %s\n",
563 strerror(errno));
564 return false;
565 }
566 ret = vc5_ioctl(screen->fd, DRM_IOCTL_V3D_GET_PARAM, &ident1);
567 if (ret != 0) {
568 fprintf(stderr, "Couldn't get V3D core IDENT1: %s\n",
569 strerror(errno));
570 return false;
571 }
572
573 uint32_t major = (ident0.value >> 24) & 0xff;
574 uint32_t minor = (ident1.value >> 0) & 0xf;
575 screen->devinfo.ver = major * 10 + minor;
576
577 switch (screen->devinfo.ver) {
578 case 33:
579 case 41:
580 case 42:
581 break;
582 default:
583 fprintf(stderr,
584 "V3D %d.%d not supported by this version of Mesa.\n",
585 screen->devinfo.ver / 10,
586 screen->devinfo.ver % 10);
587 return false;
588 }
589
590 return true;
591 }
592
593 static const void *
594 vc5_screen_get_compiler_options(struct pipe_screen *pscreen,
595 enum pipe_shader_ir ir, unsigned shader)
596 {
597 return &v3d_nir_options;
598 }
599
600 struct pipe_screen *
601 vc5_screen_create(int fd)
602 {
603 struct vc5_screen *screen = rzalloc(NULL, struct vc5_screen);
604 struct pipe_screen *pscreen;
605
606 pscreen = &screen->base;
607
608 pscreen->destroy = vc5_screen_destroy;
609 pscreen->get_param = vc5_screen_get_param;
610 pscreen->get_paramf = vc5_screen_get_paramf;
611 pscreen->get_shader_param = vc5_screen_get_shader_param;
612 pscreen->context_create = vc5_context_create;
613 pscreen->is_format_supported = vc5_screen_is_format_supported;
614
615 screen->fd = fd;
616 list_inithead(&screen->bo_cache.time_list);
617 (void)mtx_init(&screen->bo_handles_mutex, mtx_plain);
618 screen->bo_handles = util_hash_table_create(handle_hash, handle_compare);
619
620 #if defined(USE_VC5_SIMULATOR)
621 vc5_simulator_init(screen);
622 #endif
623
624 if (!vc5_get_device_info(screen))
625 goto fail;
626
627 slab_create_parent(&screen->transfer_pool, sizeof(struct vc5_transfer), 16);
628
629 vc5_fence_init(screen);
630
631 v3d_process_debug_variable();
632
633 vc5_resource_screen_init(pscreen);
634
635 screen->compiler = v3d_compiler_init(&screen->devinfo);
636
637 pscreen->get_name = vc5_screen_get_name;
638 pscreen->get_vendor = vc5_screen_get_vendor;
639 pscreen->get_device_vendor = vc5_screen_get_vendor;
640 pscreen->get_compiler_options = vc5_screen_get_compiler_options;
641
642 return pscreen;
643
644 fail:
645 close(fd);
646 ralloc_free(pscreen);
647 return NULL;
648 }