src/gallium/drivers/virgl/virgl_context.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <libsync.h>
  25 #include "pipe/p_shader_tokens.h"
  26
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_defines.h"
  29 #include "pipe/p_screen.h"
  30 #include "pipe/p_state.h"
  31 #include "util/u_inlines.h"
  32 #include "util/u_memory.h"
  33 #include "util/format/u_format.h"
  34 #include "util/u_prim.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_helpers.h"
  37 #include "util/slab.h"
  38 #include "util/u_upload_mgr.h"
  39 #include "util/u_blitter.h"
  40 #include "tgsi/tgsi_text.h"
  41 #include "indices/u_primconvert.h"
  42
  43 #include "pipebuffer/pb_buffer.h"
  44
  45 #include "virgl_encode.h"
  46 #include "virgl_context.h"
  47 #include "virgl_protocol.h"
  48 #include "virgl_resource.h"
  49 #include "virgl_screen.h"
  50 #include "virgl_staging_mgr.h"
  51
  52 struct virgl_vertex_elements_state {
  53    uint32_t handle;
  54    uint8_t binding_map[PIPE_MAX_ATTRIBS];
  55    uint8_t num_bindings;
  56 };
  57
  58 static uint32_t next_handle;
  59 uint32_t virgl_object_assign_handle(void)
  60 {
  61    return ++next_handle;
  62 }
  63
  64 bool
  65 virgl_can_rebind_resource(struct virgl_context *vctx,
  66                           struct pipe_resource *res)
  67 {
  68    /* We cannot rebind resources that are referenced by host objects, which
  69     * are
  70     *
  71     *  - VIRGL_OBJECT_SURFACE
  72     *  - VIRGL_OBJECT_SAMPLER_VIEW
  73     *  - VIRGL_OBJECT_STREAMOUT_TARGET
  74     *
  75     * Because surfaces cannot be created from buffers, we require the resource
  76     * to be a buffer instead (and avoid tracking VIRGL_OBJECT_SURFACE binds).
  77     */
  78    const unsigned unsupported_bind = (PIPE_BIND_SAMPLER_VIEW |
  79                                       PIPE_BIND_STREAM_OUTPUT);
  80    const unsigned bind_history = virgl_resource(res)->bind_history;
  81    return res->target == PIPE_BUFFER && !(bind_history & unsupported_bind);
  82 }
  83
  84 void
  85 virgl_rebind_resource(struct virgl_context *vctx,
  86                       struct pipe_resource *res)
  87 {
  88    /* Queries use internally created buffers and do not go through transfers.
  89     * Index buffers are not bindable.  They are not tracked.
  90     */
  91    ASSERTED const unsigned tracked_bind = (PIPE_BIND_VERTEX_BUFFER |
  92                                                PIPE_BIND_CONSTANT_BUFFER |
  93                                                PIPE_BIND_SHADER_BUFFER |
  94                                                PIPE_BIND_SHADER_IMAGE);
  95    const unsigned bind_history = virgl_resource(res)->bind_history;
  96    unsigned i;
  97
  98    assert(virgl_can_rebind_resource(vctx, res) &&
  99           (bind_history & tracked_bind) == bind_history);
 100
 101    if (bind_history & PIPE_BIND_VERTEX_BUFFER) {
 102       for (i = 0; i < vctx->num_vertex_buffers; i++) {
 103          if (vctx->vertex_buffer[i].buffer.resource == res) {
 104             vctx->vertex_array_dirty = true;
 105             break;
 106          }
 107       }
 108    }
 109
 110    if (bind_history & PIPE_BIND_SHADER_BUFFER) {
 111       uint32_t remaining_mask = vctx->atomic_buffer_enabled_mask;
 112       while (remaining_mask) {
 113          int i = u_bit_scan(&remaining_mask);
 114          if (vctx->atomic_buffers[i].buffer == res) {
 115             const struct pipe_shader_buffer *abo = &vctx->atomic_buffers[i];
 116             virgl_encode_set_hw_atomic_buffers(vctx, i, 1, abo);
 117          }
 118       }
 119    }
 120
 121    /* check per-stage shader bindings */
 122    if (bind_history & (PIPE_BIND_CONSTANT_BUFFER |
 123                        PIPE_BIND_SHADER_BUFFER |
 124                        PIPE_BIND_SHADER_IMAGE)) {
 125       enum pipe_shader_type shader_type;
 126       for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
 127          const struct virgl_shader_binding_state *binding =
 128             &vctx->shader_bindings[shader_type];
 129
 130          if (bind_history & PIPE_BIND_CONSTANT_BUFFER) {
 131             uint32_t remaining_mask = binding->ubo_enabled_mask;
 132             while (remaining_mask) {
 133                int i = u_bit_scan(&remaining_mask);
 134                if (binding->ubos[i].buffer == res) {
 135                   const struct pipe_constant_buffer *ubo = &binding->ubos[i];
 136                   virgl_encoder_set_uniform_buffer(vctx, shader_type, i,
 137                                                    ubo->buffer_offset,
 138                                                    ubo->buffer_size,
 139                                                    virgl_resource(res));
 140                }
 141             }
 142          }
 143
 144          if (bind_history & PIPE_BIND_SHADER_BUFFER) {
 145             uint32_t remaining_mask = binding->ssbo_enabled_mask;
 146             while (remaining_mask) {
 147                int i = u_bit_scan(&remaining_mask);
 148                if (binding->ssbos[i].buffer == res) {
 149                   const struct pipe_shader_buffer *ssbo = &binding->ssbos[i];
 150                   virgl_encode_set_shader_buffers(vctx, shader_type, i, 1,
 151                                                   ssbo);
 152                }
 153             }
 154          }
 155
 156          if (bind_history & PIPE_BIND_SHADER_IMAGE) {
 157             uint32_t remaining_mask = binding->image_enabled_mask;
 158             while (remaining_mask) {
 159                int i = u_bit_scan(&remaining_mask);
 160                if (binding->images[i].resource == res) {
 161                   const struct pipe_image_view *image = &binding->images[i];
 162                   virgl_encode_set_shader_images(vctx, shader_type, i, 1,
 163                                                  image);
 164                }
 165             }
 166          }
 167       }
 168    }
 169 }
 170
 171 static void virgl_attach_res_framebuffer(struct virgl_context *vctx)
 172 {
 173    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 174    struct pipe_surface *surf;
 175    struct virgl_resource *res;
 176    unsigned i;
 177
 178    surf = vctx->framebuffer.zsbuf;
 179    if (surf) {
 180       res = virgl_resource(surf->texture);
 181       if (res) {
 182          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 183          virgl_resource_dirty(res, surf->u.tex.level);
 184       }
 185    }
 186    for (i = 0; i < vctx->framebuffer.nr_cbufs; i++) {
 187       surf = vctx->framebuffer.cbufs[i];
 188       if (surf) {
 189          res = virgl_resource(surf->texture);
 190          if (res) {
 191             vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 192             virgl_resource_dirty(res, surf->u.tex.level);
 193          }
 194       }
 195    }
 196 }
 197
 198 static void virgl_attach_res_sampler_views(struct virgl_context *vctx,
 199                                            enum pipe_shader_type shader_type)
 200 {
 201    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 202    const struct virgl_shader_binding_state *binding =
 203       &vctx->shader_bindings[shader_type];
 204    uint32_t remaining_mask = binding->view_enabled_mask;
 205    struct virgl_resource *res;
 206
 207    while (remaining_mask) {
 208       int i = u_bit_scan(&remaining_mask);
 209       assert(binding->views[i] && binding->views[i]->texture);
 210       res = virgl_resource(binding->views[i]->texture);
 211       vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 212    }
 213 }
 214
 215 static void virgl_attach_res_vertex_buffers(struct virgl_context *vctx)
 216 {
 217    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 218    struct virgl_resource *res;
 219    unsigned i;
 220
 221    for (i = 0; i < vctx->num_vertex_buffers; i++) {
 222       res = virgl_resource(vctx->vertex_buffer[i].buffer.resource);
 223       if (res)
 224          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 225    }
 226 }
 227
 228 static void virgl_attach_res_index_buffer(struct virgl_context *vctx,
 229                                           struct virgl_indexbuf *ib)
 230 {
 231    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 232    struct virgl_resource *res;
 233
 234    res = virgl_resource(ib->buffer);
 235    if (res)
 236       vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 237 }
 238
 239 static void virgl_attach_res_so_targets(struct virgl_context *vctx)
 240 {
 241    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 242    struct virgl_resource *res;
 243    unsigned i;
 244
 245    for (i = 0; i < vctx->num_so_targets; i++) {
 246       res = virgl_resource(vctx->so_targets[i].base.buffer);
 247       if (res)
 248          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 249    }
 250 }
 251
 252 static void virgl_attach_res_uniform_buffers(struct virgl_context *vctx,
 253                                              enum pipe_shader_type shader_type)
 254 {
 255    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 256    const struct virgl_shader_binding_state *binding =
 257       &vctx->shader_bindings[shader_type];
 258    uint32_t remaining_mask = binding->ubo_enabled_mask;
 259    struct virgl_resource *res;
 260
 261    while (remaining_mask) {
 262       int i = u_bit_scan(&remaining_mask);
 263       res = virgl_resource(binding->ubos[i].buffer);
 264       assert(res);
 265       vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 266    }
 267 }
 268
 269 static void virgl_attach_res_shader_buffers(struct virgl_context *vctx,
 270                                             enum pipe_shader_type shader_type)
 271 {
 272    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 273    const struct virgl_shader_binding_state *binding =
 274       &vctx->shader_bindings[shader_type];
 275    uint32_t remaining_mask = binding->ssbo_enabled_mask;
 276    struct virgl_resource *res;
 277
 278    while (remaining_mask) {
 279       int i = u_bit_scan(&remaining_mask);
 280       res = virgl_resource(binding->ssbos[i].buffer);
 281       assert(res);
 282       vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 283    }
 284 }
 285
 286 static void virgl_attach_res_shader_images(struct virgl_context *vctx,
 287                                            enum pipe_shader_type shader_type)
 288 {
 289    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 290    const struct virgl_shader_binding_state *binding =
 291       &vctx->shader_bindings[shader_type];
 292    uint32_t remaining_mask = binding->image_enabled_mask;
 293    struct virgl_resource *res;
 294
 295    while (remaining_mask) {
 296       int i = u_bit_scan(&remaining_mask);
 297       res = virgl_resource(binding->images[i].resource);
 298       assert(res);
 299       vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 300    }
 301 }
 302
 303 static void virgl_attach_res_atomic_buffers(struct virgl_context *vctx)
 304 {
 305    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 306    uint32_t remaining_mask = vctx->atomic_buffer_enabled_mask;
 307    struct virgl_resource *res;
 308
 309    while (remaining_mask) {
 310       int i = u_bit_scan(&remaining_mask);
 311       res = virgl_resource(vctx->atomic_buffers[i].buffer);
 312       assert(res);
 313       vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 314    }
 315 }
 316
 317 /*
 318  * after flushing, the hw context still has a bunch of
 319  * resources bound, so we need to rebind those here.
 320  */
 321 static void virgl_reemit_draw_resources(struct virgl_context *vctx)
 322 {
 323    enum pipe_shader_type shader_type;
 324
 325    /* reattach any flushed resources */
 326    /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
 327    virgl_attach_res_framebuffer(vctx);
 328
 329    for (shader_type = 0; shader_type < PIPE_SHADER_COMPUTE; shader_type++) {
 330       virgl_attach_res_sampler_views(vctx, shader_type);
 331       virgl_attach_res_uniform_buffers(vctx, shader_type);
 332       virgl_attach_res_shader_buffers(vctx, shader_type);
 333       virgl_attach_res_shader_images(vctx, shader_type);
 334    }
 335    virgl_attach_res_atomic_buffers(vctx);
 336    virgl_attach_res_vertex_buffers(vctx);
 337    virgl_attach_res_so_targets(vctx);
 338 }
 339
 340 static void virgl_reemit_compute_resources(struct virgl_context *vctx)
 341 {
 342    virgl_attach_res_sampler_views(vctx, PIPE_SHADER_COMPUTE);
 343    virgl_attach_res_uniform_buffers(vctx, PIPE_SHADER_COMPUTE);
 344    virgl_attach_res_shader_buffers(vctx, PIPE_SHADER_COMPUTE);
 345    virgl_attach_res_shader_images(vctx, PIPE_SHADER_COMPUTE);
 346
 347    virgl_attach_res_atomic_buffers(vctx);
 348 }
 349
 350 static struct pipe_surface *virgl_create_surface(struct pipe_context *ctx,
 351                                                 struct pipe_resource *resource,
 352                                                 const struct pipe_surface *templ)
 353 {
 354    struct virgl_context *vctx = virgl_context(ctx);
 355    struct virgl_surface *surf;
 356    struct virgl_resource *res = virgl_resource(resource);
 357    uint32_t handle;
 358
 359    /* no support for buffer surfaces */
 360    if (resource->target == PIPE_BUFFER)
 361       return NULL;
 362
 363    surf = CALLOC_STRUCT(virgl_surface);
 364    if (!surf)
 365       return NULL;
 366
 367    assert(ctx->screen->get_param(ctx->screen,
 368                                  PIPE_CAP_DEST_SURFACE_SRGB_CONTROL) ||
 369           (util_format_is_srgb(templ->format) ==
 370            util_format_is_srgb(resource->format)));
 371
 372    virgl_resource_dirty(res, 0);
 373    handle = virgl_object_assign_handle();
 374    pipe_reference_init(&surf->base.reference, 1);
 375    pipe_resource_reference(&surf->base.texture, resource);
 376    surf->base.context = ctx;
 377    surf->base.format = templ->format;
 378
 379    surf->base.width = u_minify(resource->width0, templ->u.tex.level);
 380    surf->base.height = u_minify(resource->height0, templ->u.tex.level);
 381    surf->base.u.tex.level = templ->u.tex.level;
 382    surf->base.u.tex.first_layer = templ->u.tex.first_layer;
 383    surf->base.u.tex.last_layer = templ->u.tex.last_layer;
 384
 385    virgl_encoder_create_surface(vctx, handle, res, &surf->base);
 386    surf->handle = handle;
 387    return &surf->base;
 388 }
 389
 390 static void virgl_surface_destroy(struct pipe_context *ctx,
 391                                  struct pipe_surface *psurf)
 392 {
 393    struct virgl_context *vctx = virgl_context(ctx);
 394    struct virgl_surface *surf = virgl_surface(psurf);
 395
 396    pipe_resource_reference(&surf->base.texture, NULL);
 397    virgl_encode_delete_object(vctx, surf->handle, VIRGL_OBJECT_SURFACE);
 398    FREE(surf);
 399 }
 400
 401 static void *virgl_create_blend_state(struct pipe_context *ctx,
 402                                               const struct pipe_blend_state *blend_state)
 403 {
 404    struct virgl_context *vctx = virgl_context(ctx);
 405    uint32_t handle;
 406    handle = virgl_object_assign_handle();
 407
 408    virgl_encode_blend_state(vctx, handle, blend_state);
 409    return (void *)(unsigned long)handle;
 410
 411 }
 412
 413 static void virgl_bind_blend_state(struct pipe_context *ctx,
 414                                            void *blend_state)
 415 {
 416    struct virgl_context *vctx = virgl_context(ctx);
 417    uint32_t handle = (unsigned long)blend_state;
 418    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_BLEND);
 419 }
 420
 421 static void virgl_delete_blend_state(struct pipe_context *ctx,
 422                                      void *blend_state)
 423 {
 424    struct virgl_context *vctx = virgl_context(ctx);
 425    uint32_t handle = (unsigned long)blend_state;
 426    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_BLEND);
 427 }
 428
 429 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context *ctx,
 430                                                    const struct pipe_depth_stencil_alpha_state *blend_state)
 431 {
 432    struct virgl_context *vctx = virgl_context(ctx);
 433    uint32_t handle;
 434    handle = virgl_object_assign_handle();
 435
 436    virgl_encode_dsa_state(vctx, handle, blend_state);
 437    return (void *)(unsigned long)handle;
 438 }
 439
 440 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context *ctx,
 441                                                 void *blend_state)
 442 {
 443    struct virgl_context *vctx = virgl_context(ctx);
 444    uint32_t handle = (unsigned long)blend_state;
 445    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_DSA);
 446 }
 447
 448 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context *ctx,
 449                                                   void *dsa_state)
 450 {
 451    struct virgl_context *vctx = virgl_context(ctx);
 452    uint32_t handle = (unsigned long)dsa_state;
 453    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_DSA);
 454 }
 455
 456 static void *virgl_create_rasterizer_state(struct pipe_context *ctx,
 457                                                    const struct pipe_rasterizer_state *rs_state)
 458 {
 459    struct virgl_context *vctx = virgl_context(ctx);
 460    struct virgl_rasterizer_state *vrs = CALLOC_STRUCT(virgl_rasterizer_state);
 461
 462    if (!vrs)
 463       return NULL;
 464    vrs->rs = *rs_state;
 465    vrs->handle = virgl_object_assign_handle();
 466
 467    assert(rs_state->depth_clip_near ||
 468           virgl_screen(ctx->screen)->caps.caps.v1.bset.depth_clip_disable);
 469
 470    virgl_encode_rasterizer_state(vctx, vrs->handle, rs_state);
 471    return (void *)vrs;
 472 }
 473
 474 static void virgl_bind_rasterizer_state(struct pipe_context *ctx,
 475                                                 void *rs_state)
 476 {
 477    struct virgl_context *vctx = virgl_context(ctx);
 478    uint32_t handle = 0;
 479    if (rs_state) {
 480       struct virgl_rasterizer_state *vrs = rs_state;
 481       vctx->rs_state = *vrs;
 482       handle = vrs->handle;
 483    }
 484    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_RASTERIZER);
 485 }
 486
 487 static void virgl_delete_rasterizer_state(struct pipe_context *ctx,
 488                                          void *rs_state)
 489 {
 490    struct virgl_context *vctx = virgl_context(ctx);
 491    struct virgl_rasterizer_state *vrs = rs_state;
 492    virgl_encode_delete_object(vctx, vrs->handle, VIRGL_OBJECT_RASTERIZER);
 493    FREE(vrs);
 494 }
 495
 496 static void virgl_set_framebuffer_state(struct pipe_context *ctx,
 497                                                 const struct pipe_framebuffer_state *state)
 498 {
 499    struct virgl_context *vctx = virgl_context(ctx);
 500
 501    vctx->framebuffer = *state;
 502    virgl_encoder_set_framebuffer_state(vctx, state);
 503    virgl_attach_res_framebuffer(vctx);
 504 }
 505
 506 static void virgl_set_viewport_states(struct pipe_context *ctx,
 507                                      unsigned start_slot,
 508                                      unsigned num_viewports,
 509                                      const struct pipe_viewport_state *state)
 510 {
 511    struct virgl_context *vctx = virgl_context(ctx);
 512    virgl_encoder_set_viewport_states(vctx, start_slot, num_viewports, state);
 513 }
 514
 515 static void *virgl_create_vertex_elements_state(struct pipe_context *ctx,
 516                                                         unsigned num_elements,
 517                                                         const struct pipe_vertex_element *elements)
 518 {
 519    struct pipe_vertex_element new_elements[PIPE_MAX_ATTRIBS];
 520    struct virgl_context *vctx = virgl_context(ctx);
 521    struct virgl_vertex_elements_state *state =
 522       CALLOC_STRUCT(virgl_vertex_elements_state);
 523
 524    for (int i = 0; i < num_elements; ++i) {
 525       if (elements[i].instance_divisor) {
 526          /* Virglrenderer doesn't deal with instance_divisor correctly if
 527           * there isn't a 1:1 relationship between elements and bindings.
 528           * So let's make sure there is, by duplicating bindings.
 529           */
 530          for (int j = 0; j < num_elements; ++j) {
 531             new_elements[j] = elements[j];
 532             new_elements[j].vertex_buffer_index = j;
 533             state->binding_map[j] = elements[j].vertex_buffer_index;
 534          }
 535          elements = new_elements;
 536          state->num_bindings = num_elements;
 537          break;
 538       }
 539    }
 540
 541    state->handle = virgl_object_assign_handle();
 542    virgl_encoder_create_vertex_elements(vctx, state->handle,
 543                                        num_elements, elements);
 544    return state;
 545 }
 546
 547 static void virgl_delete_vertex_elements_state(struct pipe_context *ctx,
 548                                               void *ve)
 549 {
 550    struct virgl_context *vctx = virgl_context(ctx);
 551    struct virgl_vertex_elements_state *state =
 552       (struct virgl_vertex_elements_state *)ve;
 553    virgl_encode_delete_object(vctx, state->handle, VIRGL_OBJECT_VERTEX_ELEMENTS);
 554    FREE(state);
 555 }
 556
 557 static void virgl_bind_vertex_elements_state(struct pipe_context *ctx,
 558                                                      void *ve)
 559 {
 560    struct virgl_context *vctx = virgl_context(ctx);
 561    struct virgl_vertex_elements_state *state =
 562       (struct virgl_vertex_elements_state *)ve;
 563    vctx->vertex_elements = state;
 564    virgl_encode_bind_object(vctx, state ? state->handle : 0,
 565                             VIRGL_OBJECT_VERTEX_ELEMENTS);
 566    vctx->vertex_array_dirty = TRUE;
 567 }
 568
 569 static void virgl_set_vertex_buffers(struct pipe_context *ctx,
 570                                     unsigned start_slot,
 571                                     unsigned num_buffers,
 572                                     const struct pipe_vertex_buffer *buffers)
 573 {
 574    struct virgl_context *vctx = virgl_context(ctx);
 575
 576    util_set_vertex_buffers_count(vctx->vertex_buffer,
 577                                  &vctx->num_vertex_buffers,
 578                                  buffers, start_slot, num_buffers);
 579
 580    if (buffers) {
 581       for (unsigned i = 0; i < num_buffers; i++) {
 582          struct virgl_resource *res =
 583             virgl_resource(buffers[i].buffer.resource);
 584          if (res && !buffers[i].is_user_buffer)
 585             res->bind_history |= PIPE_BIND_VERTEX_BUFFER;
 586       }
 587    }
 588
 589    vctx->vertex_array_dirty = TRUE;
 590 }
 591
 592 static void virgl_hw_set_vertex_buffers(struct virgl_context *vctx)
 593 {
 594    if (vctx->vertex_array_dirty) {
 595       struct virgl_vertex_elements_state *ve = vctx->vertex_elements;
 596
 597       if (ve->num_bindings) {
 598          struct pipe_vertex_buffer vertex_buffers[PIPE_MAX_ATTRIBS];
 599          for (int i = 0; i < ve->num_bindings; ++i)
 600             vertex_buffers[i] = vctx->vertex_buffer[ve->binding_map[i]];
 601
 602          virgl_encoder_set_vertex_buffers(vctx, ve->num_bindings, vertex_buffers);
 603       } else
 604          virgl_encoder_set_vertex_buffers(vctx, vctx->num_vertex_buffers, vctx->vertex_buffer);
 605
 606       virgl_attach_res_vertex_buffers(vctx);
 607
 608       vctx->vertex_array_dirty = FALSE;
 609    }
 610 }
 611
 612 static void virgl_set_stencil_ref(struct pipe_context *ctx,
 613                                  const struct pipe_stencil_ref *ref)
 614 {
 615    struct virgl_context *vctx = virgl_context(ctx);
 616    virgl_encoder_set_stencil_ref(vctx, ref);
 617 }
 618
 619 static void virgl_set_blend_color(struct pipe_context *ctx,
 620                                  const struct pipe_blend_color *color)
 621 {
 622    struct virgl_context *vctx = virgl_context(ctx);
 623    virgl_encoder_set_blend_color(vctx, color);
 624 }
 625
 626 static void virgl_hw_set_index_buffer(struct virgl_context *vctx,
 627                                      struct virgl_indexbuf *ib)
 628 {
 629    virgl_encoder_set_index_buffer(vctx, ib);
 630    virgl_attach_res_index_buffer(vctx, ib);
 631 }
 632
 633 static void virgl_set_constant_buffer(struct pipe_context *ctx,
 634                                      enum pipe_shader_type shader, uint index,
 635                                      const struct pipe_constant_buffer *buf)
 636 {
 637    struct virgl_context *vctx = virgl_context(ctx);
 638    struct virgl_shader_binding_state *binding =
 639       &vctx->shader_bindings[shader];
 640
 641    if (buf && buf->buffer) {
 642       struct virgl_resource *res = virgl_resource(buf->buffer);
 643       res->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
 644
 645       virgl_encoder_set_uniform_buffer(vctx, shader, index,
 646                                        buf->buffer_offset,
 647                                        buf->buffer_size, res);
 648
 649       pipe_resource_reference(&binding->ubos[index].buffer, buf->buffer);
 650       binding->ubos[index] = *buf;
 651       binding->ubo_enabled_mask |= 1 << index;
 652    } else {
 653       static const struct pipe_constant_buffer dummy_ubo;
 654       if (!buf)
 655          buf = &dummy_ubo;
 656       virgl_encoder_write_constant_buffer(vctx, shader, index,
 657                                           buf->buffer_size / 4,
 658                                           buf->user_buffer);
 659
 660       pipe_resource_reference(&binding->ubos[index].buffer, NULL);
 661       binding->ubo_enabled_mask &= ~(1 << index);
 662    }
 663 }
 664
 665 static void *virgl_shader_encoder(struct pipe_context *ctx,
 666                                   const struct pipe_shader_state *shader,
 667                                   unsigned type)
 668 {
 669    struct virgl_context *vctx = virgl_context(ctx);
 670    uint32_t handle;
 671    struct tgsi_token *new_tokens;
 672    int ret;
 673
 674    new_tokens = virgl_tgsi_transform(vctx, shader->tokens);
 675    if (!new_tokens)
 676       return NULL;
 677
 678    handle = virgl_object_assign_handle();
 679    /* encode VS state */
 680    ret = virgl_encode_shader_state(vctx, handle, type,
 681                                    &shader->stream_output, 0,
 682                                    new_tokens);
 683    if (ret) {
 684       return NULL;
 685    }
 686
 687    FREE(new_tokens);
 688    return (void *)(unsigned long)handle;
 689
 690 }
 691 static void *virgl_create_vs_state(struct pipe_context *ctx,
 692                                    const struct pipe_shader_state *shader)
 693 {
 694    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_VERTEX);
 695 }
 696
 697 static void *virgl_create_tcs_state(struct pipe_context *ctx,
 698                                    const struct pipe_shader_state *shader)
 699 {
 700    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_CTRL);
 701 }
 702
 703 static void *virgl_create_tes_state(struct pipe_context *ctx,
 704                                    const struct pipe_shader_state *shader)
 705 {
 706    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_EVAL);
 707 }
 708
 709 static void *virgl_create_gs_state(struct pipe_context *ctx,
 710                                    const struct pipe_shader_state *shader)
 711 {
 712    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_GEOMETRY);
 713 }
 714
 715 static void *virgl_create_fs_state(struct pipe_context *ctx,
 716                                    const struct pipe_shader_state *shader)
 717 {
 718    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_FRAGMENT);
 719 }
 720
 721 static void
 722 virgl_delete_fs_state(struct pipe_context *ctx,
 723                      void *fs)
 724 {
 725    uint32_t handle = (unsigned long)fs;
 726    struct virgl_context *vctx = virgl_context(ctx);
 727
 728    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 729 }
 730
 731 static void
 732 virgl_delete_gs_state(struct pipe_context *ctx,
 733                      void *gs)
 734 {
 735    uint32_t handle = (unsigned long)gs;
 736    struct virgl_context *vctx = virgl_context(ctx);
 737
 738    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 739 }
 740
 741 static void
 742 virgl_delete_vs_state(struct pipe_context *ctx,
 743                      void *vs)
 744 {
 745    uint32_t handle = (unsigned long)vs;
 746    struct virgl_context *vctx = virgl_context(ctx);
 747
 748    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 749 }
 750
 751 static void
 752 virgl_delete_tcs_state(struct pipe_context *ctx,
 753                        void *tcs)
 754 {
 755    uint32_t handle = (unsigned long)tcs;
 756    struct virgl_context *vctx = virgl_context(ctx);
 757
 758    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 759 }
 760
 761 static void
 762 virgl_delete_tes_state(struct pipe_context *ctx,
 763                       void *tes)
 764 {
 765    uint32_t handle = (unsigned long)tes;
 766    struct virgl_context *vctx = virgl_context(ctx);
 767
 768    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 769 }
 770
 771 static void virgl_bind_vs_state(struct pipe_context *ctx,
 772                                         void *vss)
 773 {
 774    uint32_t handle = (unsigned long)vss;
 775    struct virgl_context *vctx = virgl_context(ctx);
 776
 777    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_VERTEX);
 778 }
 779
 780 static void virgl_bind_tcs_state(struct pipe_context *ctx,
 781                                void *vss)
 782 {
 783    uint32_t handle = (unsigned long)vss;
 784    struct virgl_context *vctx = virgl_context(ctx);
 785
 786    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_CTRL);
 787 }
 788
 789 static void virgl_bind_tes_state(struct pipe_context *ctx,
 790                                void *vss)
 791 {
 792    uint32_t handle = (unsigned long)vss;
 793    struct virgl_context *vctx = virgl_context(ctx);
 794
 795    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_EVAL);
 796 }
 797
 798 static void virgl_bind_gs_state(struct pipe_context *ctx,
 799                                void *vss)
 800 {
 801    uint32_t handle = (unsigned long)vss;
 802    struct virgl_context *vctx = virgl_context(ctx);
 803
 804    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_GEOMETRY);
 805 }
 806
 807
 808 static void virgl_bind_fs_state(struct pipe_context *ctx,
 809                                         void *vss)
 810 {
 811    uint32_t handle = (unsigned long)vss;
 812    struct virgl_context *vctx = virgl_context(ctx);
 813
 814    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_FRAGMENT);
 815 }
 816
 817 static void virgl_clear(struct pipe_context *ctx,
 818                                 unsigned buffers,
 819                                 const struct pipe_scissor_state *scissor_state,
 820                                 const union pipe_color_union *color,
 821                                 double depth, unsigned stencil)
 822 {
 823    struct virgl_context *vctx = virgl_context(ctx);
 824
 825    if (!vctx->num_draws)
 826       virgl_reemit_draw_resources(vctx);
 827    vctx->num_draws++;
 828
 829    virgl_encode_clear(vctx, buffers, color, depth, stencil);
 830 }
 831
 832 static void virgl_draw_vbo(struct pipe_context *ctx,
 833                                    const struct pipe_draw_info *dinfo)
 834 {
 835    struct virgl_context *vctx = virgl_context(ctx);
 836    struct virgl_screen *rs = virgl_screen(ctx->screen);
 837    struct virgl_indexbuf ib = {};
 838    struct pipe_draw_info info = *dinfo;
 839
 840    if (!dinfo->count_from_stream_output && !dinfo->indirect &&
 841        !dinfo->primitive_restart &&
 842        !u_trim_pipe_prim(dinfo->mode, (unsigned*)&dinfo->count))
 843       return;
 844
 845    if (!(rs->caps.caps.v1.prim_mask & (1 << dinfo->mode))) {
 846       util_primconvert_save_rasterizer_state(vctx->primconvert, &vctx->rs_state.rs);
 847       util_primconvert_draw_vbo(vctx->primconvert, dinfo);
 848       return;
 849    }
 850    if (info.index_size) {
 851            pipe_resource_reference(&ib.buffer, info.has_user_indices ? NULL : info.index.resource);
 852            ib.user_buffer = info.has_user_indices ? info.index.user : NULL;
 853            ib.index_size = dinfo->index_size;
 854            ib.offset = info.start * ib.index_size;
 855
 856            if (ib.user_buffer) {
 857                    u_upload_data(vctx->uploader, 0, info.count * ib.index_size, 4,
 858                                  ib.user_buffer, &ib.offset, &ib.buffer);
 859                    ib.user_buffer = NULL;
 860            }
 861    }
 862
 863    if (!vctx->num_draws)
 864       virgl_reemit_draw_resources(vctx);
 865    vctx->num_draws++;
 866
 867    virgl_hw_set_vertex_buffers(vctx);
 868    if (info.index_size)
 869       virgl_hw_set_index_buffer(vctx, &ib);
 870
 871    virgl_encoder_draw_vbo(vctx, &info);
 872
 873    pipe_resource_reference(&ib.buffer, NULL);
 874
 875 }
 876
 877 static void virgl_submit_cmd(struct virgl_winsys *vws,
 878                              struct virgl_cmd_buf *cbuf,
 879                              struct pipe_fence_handle **fence)
 880 {
 881    if (unlikely(virgl_debug & VIRGL_DEBUG_SYNC)) {
 882       struct pipe_fence_handle *sync_fence = NULL;
 883
 884       vws->submit_cmd(vws, cbuf, &sync_fence);
 885
 886       vws->fence_wait(vws, sync_fence, PIPE_TIMEOUT_INFINITE);
 887       vws->fence_reference(vws, &sync_fence, NULL);
 888    } else {
 889       vws->submit_cmd(vws, cbuf, fence);
 890    }
 891 }
 892
 893 static void virgl_flush_eq(struct virgl_context *ctx, void *closure,
 894                            struct pipe_fence_handle **fence)
 895 {
 896    struct virgl_screen *rs = virgl_screen(ctx->base.screen);
 897
 898    /* skip empty cbuf */
 899    if (ctx->cbuf->cdw == ctx->cbuf_initial_cdw &&
 900        ctx->queue.num_dwords == 0 &&
 901        !fence)
 902       return;
 903
 904    if (ctx->num_draws)
 905       u_upload_unmap(ctx->uploader);
 906
 907    /* send the buffer to the remote side for decoding */
 908    ctx->num_draws = ctx->num_compute = 0;
 909
 910    virgl_transfer_queue_clear(&ctx->queue, ctx->cbuf);
 911
 912    virgl_submit_cmd(rs->vws, ctx->cbuf, fence);
 913
 914    /* Reserve some space for transfers. */
 915    if (ctx->encoded_transfers)
 916       ctx->cbuf->cdw = VIRGL_MAX_TBUF_DWORDS;
 917
 918    virgl_encoder_set_sub_ctx(ctx, ctx->hw_sub_ctx_id);
 919
 920    ctx->cbuf_initial_cdw = ctx->cbuf->cdw;
 921
 922    /* We have flushed the command queue, including any pending copy transfers
 923     * involving staging resources.
 924     */
 925    ctx->queued_staging_res_size = 0;
 926 }
 927
 928 static void virgl_flush_from_st(struct pipe_context *ctx,
 929                                struct pipe_fence_handle **fence,
 930                                enum pipe_flush_flags flags)
 931 {
 932    struct virgl_context *vctx = virgl_context(ctx);
 933
 934    virgl_flush_eq(vctx, vctx, fence);
 935 }
 936
 937 static struct pipe_sampler_view *virgl_create_sampler_view(struct pipe_context *ctx,
 938                                       struct pipe_resource *texture,
 939                                       const struct pipe_sampler_view *state)
 940 {
 941    struct virgl_context *vctx = virgl_context(ctx);
 942    struct virgl_sampler_view *grview;
 943    uint32_t handle;
 944    struct virgl_resource *res;
 945
 946    if (!state)
 947       return NULL;
 948
 949    grview = CALLOC_STRUCT(virgl_sampler_view);
 950    if (!grview)
 951       return NULL;
 952
 953    res = virgl_resource(texture);
 954    handle = virgl_object_assign_handle();
 955    virgl_encode_sampler_view(vctx, handle, res, state);
 956
 957    grview->base = *state;
 958    grview->base.reference.count = 1;
 959
 960    grview->base.texture = NULL;
 961    grview->base.context = ctx;
 962    pipe_resource_reference(&grview->base.texture, texture);
 963    grview->handle = handle;
 964    return &grview->base;
 965 }
 966
 967 static void virgl_set_sampler_views(struct pipe_context *ctx,
 968                                    enum pipe_shader_type shader_type,
 969                                    unsigned start_slot,
 970                                    unsigned num_views,
 971                                    struct pipe_sampler_view **views)
 972 {
 973    struct virgl_context *vctx = virgl_context(ctx);
 974    struct virgl_shader_binding_state *binding =
 975       &vctx->shader_bindings[shader_type];
 976
 977    binding->view_enabled_mask &= ~u_bit_consecutive(start_slot, num_views);
 978    for (unsigned i = 0; i < num_views; i++) {
 979       unsigned idx = start_slot + i;
 980       if (views && views[i]) {
 981          struct virgl_resource *res = virgl_resource(views[i]->texture);
 982          res->bind_history |= PIPE_BIND_SAMPLER_VIEW;
 983
 984          pipe_sampler_view_reference(&binding->views[idx], views[i]);
 985          binding->view_enabled_mask |= 1 << idx;
 986       } else {
 987          pipe_sampler_view_reference(&binding->views[idx], NULL);
 988       }
 989    }
 990
 991    virgl_encode_set_sampler_views(vctx, shader_type,
 992          start_slot, num_views, (struct virgl_sampler_view **)binding->views);
 993    virgl_attach_res_sampler_views(vctx, shader_type);
 994 }
 995
 996 static void
 997 virgl_texture_barrier(struct pipe_context *ctx, unsigned flags)
 998 {
 999    struct virgl_context *vctx = virgl_context(ctx);
1000    struct virgl_screen *rs = virgl_screen(ctx->screen);
1001
1002    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER))
1003       return;
1004    virgl_encode_texture_barrier(vctx, flags);
1005 }
1006
1007 static void virgl_destroy_sampler_view(struct pipe_context *ctx,
1008                                  struct pipe_sampler_view *view)
1009 {
1010    struct virgl_context *vctx = virgl_context(ctx);
1011    struct virgl_sampler_view *grview = virgl_sampler_view(view);
1012
1013    virgl_encode_delete_object(vctx, grview->handle, VIRGL_OBJECT_SAMPLER_VIEW);
1014    pipe_resource_reference(&view->texture, NULL);
1015    FREE(view);
1016 }
1017
1018 static void *virgl_create_sampler_state(struct pipe_context *ctx,
1019                                         const struct pipe_sampler_state *state)
1020 {
1021    struct virgl_context *vctx = virgl_context(ctx);
1022    uint32_t handle;
1023
1024    handle = virgl_object_assign_handle();
1025
1026    virgl_encode_sampler_state(vctx, handle, state);
1027    return (void *)(unsigned long)handle;
1028 }
1029
1030 static void virgl_delete_sampler_state(struct pipe_context *ctx,
1031                                       void *ss)
1032 {
1033    struct virgl_context *vctx = virgl_context(ctx);
1034    uint32_t handle = (unsigned long)ss;
1035
1036    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SAMPLER_STATE);
1037 }
1038
1039 static void virgl_bind_sampler_states(struct pipe_context *ctx,
1040                                      enum pipe_shader_type shader,
1041                                      unsigned start_slot,
1042                                      unsigned num_samplers,
1043                                      void **samplers)
1044 {
1045    struct virgl_context *vctx = virgl_context(ctx);
1046    uint32_t handles[32];
1047    int i;
1048    for (i = 0; i < num_samplers; i++) {
1049       handles[i] = (unsigned long)(samplers[i]);
1050    }
1051    virgl_encode_bind_sampler_states(vctx, shader, start_slot, num_samplers, handles);
1052 }
1053
1054 static void virgl_set_polygon_stipple(struct pipe_context *ctx,
1055                                      const struct pipe_poly_stipple *ps)
1056 {
1057    struct virgl_context *vctx = virgl_context(ctx);
1058    virgl_encoder_set_polygon_stipple(vctx, ps);
1059 }
1060
1061 static void virgl_set_scissor_states(struct pipe_context *ctx,
1062                                     unsigned start_slot,
1063                                     unsigned num_scissor,
1064                                    const struct pipe_scissor_state *ss)
1065 {
1066    struct virgl_context *vctx = virgl_context(ctx);
1067    virgl_encoder_set_scissor_state(vctx, start_slot, num_scissor, ss);
1068 }
1069
1070 static void virgl_set_sample_mask(struct pipe_context *ctx,
1071                                  unsigned sample_mask)
1072 {
1073    struct virgl_context *vctx = virgl_context(ctx);
1074    virgl_encoder_set_sample_mask(vctx, sample_mask);
1075 }
1076
1077 static void virgl_set_min_samples(struct pipe_context *ctx,
1078                                  unsigned min_samples)
1079 {
1080    struct virgl_context *vctx = virgl_context(ctx);
1081    struct virgl_screen *rs = virgl_screen(ctx->screen);
1082
1083    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_SET_MIN_SAMPLES))
1084       return;
1085    virgl_encoder_set_min_samples(vctx, min_samples);
1086 }
1087
1088 static void virgl_set_clip_state(struct pipe_context *ctx,
1089                                 const struct pipe_clip_state *clip)
1090 {
1091    struct virgl_context *vctx = virgl_context(ctx);
1092    virgl_encoder_set_clip_state(vctx, clip);
1093 }
1094
1095 static void virgl_set_tess_state(struct pipe_context *ctx,
1096                                  const float default_outer_level[4],
1097                                  const float default_inner_level[2])
1098 {
1099    struct virgl_context *vctx = virgl_context(ctx);
1100    struct virgl_screen *rs = virgl_screen(ctx->screen);
1101
1102    if (!rs->caps.caps.v1.bset.has_tessellation_shaders)
1103       return;
1104    virgl_encode_set_tess_state(vctx, default_outer_level, default_inner_level);
1105 }
1106
1107 static void virgl_resource_copy_region(struct pipe_context *ctx,
1108                                       struct pipe_resource *dst,
1109                                       unsigned dst_level,
1110                                       unsigned dstx, unsigned dsty, unsigned dstz,
1111                                       struct pipe_resource *src,
1112                                       unsigned src_level,
1113                                       const struct pipe_box *src_box)
1114 {
1115    struct virgl_context *vctx = virgl_context(ctx);
1116    struct virgl_resource *dres = virgl_resource(dst);
1117    struct virgl_resource *sres = virgl_resource(src);
1118
1119    if (dres->u.b.target == PIPE_BUFFER)
1120       util_range_add(&dres->u.b, &dres->valid_buffer_range, dstx, dstx + src_box->width);
1121    virgl_resource_dirty(dres, dst_level);
1122
1123    virgl_encode_resource_copy_region(vctx, dres,
1124                                     dst_level, dstx, dsty, dstz,
1125                                     sres, src_level,
1126                                     src_box);
1127 }
1128
1129 static void
1130 virgl_flush_resource(struct pipe_context *pipe,
1131                     struct pipe_resource *resource)
1132 {
1133 }
1134
1135 static void virgl_blit(struct pipe_context *ctx,
1136                       const struct pipe_blit_info *blit)
1137 {
1138    struct virgl_context *vctx = virgl_context(ctx);
1139    struct virgl_resource *dres = virgl_resource(blit->dst.resource);
1140    struct virgl_resource *sres = virgl_resource(blit->src.resource);
1141
1142    assert(ctx->screen->get_param(ctx->screen,
1143                                  PIPE_CAP_DEST_SURFACE_SRGB_CONTROL) ||
1144           (util_format_is_srgb(blit->dst.resource->format) ==
1145             util_format_is_srgb(blit->dst.format)));
1146
1147    virgl_resource_dirty(dres, blit->dst.level);
1148    virgl_encode_blit(vctx, dres, sres,
1149                     blit);
1150 }
1151
1152 static void virgl_set_hw_atomic_buffers(struct pipe_context *ctx,
1153                                         unsigned start_slot,
1154                                         unsigned count,
1155                                         const struct pipe_shader_buffer *buffers)
1156 {
1157    struct virgl_context *vctx = virgl_context(ctx);
1158
1159    vctx->atomic_buffer_enabled_mask &= ~u_bit_consecutive(start_slot, count);
1160    for (unsigned i = 0; i < count; i++) {
1161       unsigned idx = start_slot + i;
1162       if (buffers && buffers[i].buffer) {
1163          struct virgl_resource *res = virgl_resource(buffers[i].buffer);
1164          res->bind_history |= PIPE_BIND_SHADER_BUFFER;
1165
1166          pipe_resource_reference(&vctx->atomic_buffers[idx].buffer,
1167                                  buffers[i].buffer);
1168          vctx->atomic_buffers[idx] = buffers[i];
1169          vctx->atomic_buffer_enabled_mask |= 1 << idx;
1170       } else {
1171          pipe_resource_reference(&vctx->atomic_buffers[idx].buffer, NULL);
1172       }
1173    }
1174
1175    virgl_encode_set_hw_atomic_buffers(vctx, start_slot, count, buffers);
1176 }
1177
1178 static void virgl_set_shader_buffers(struct pipe_context *ctx,
1179                                      enum pipe_shader_type shader,
1180                                      unsigned start_slot, unsigned count,
1181                                      const struct pipe_shader_buffer *buffers,
1182                                      unsigned writable_bitmask)
1183 {
1184    struct virgl_context *vctx = virgl_context(ctx);
1185    struct virgl_screen *rs = virgl_screen(ctx->screen);
1186    struct virgl_shader_binding_state *binding =
1187       &vctx->shader_bindings[shader];
1188
1189    binding->ssbo_enabled_mask &= ~u_bit_consecutive(start_slot, count);
1190    for (unsigned i = 0; i < count; i++) {
1191       unsigned idx = start_slot + i;
1192       if (buffers && buffers[i].buffer) {
1193          struct virgl_resource *res = virgl_resource(buffers[i].buffer);
1194          res->bind_history |= PIPE_BIND_SHADER_BUFFER;
1195
1196          pipe_resource_reference(&binding->ssbos[idx].buffer, buffers[i].buffer);
1197          binding->ssbos[idx] = buffers[i];
1198          binding->ssbo_enabled_mask |= 1 << idx;
1199       } else {
1200          pipe_resource_reference(&binding->ssbos[idx].buffer, NULL);
1201       }
1202    }
1203
1204    uint32_t max_shader_buffer = (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) ?
1205       rs->caps.caps.v2.max_shader_buffer_frag_compute :
1206       rs->caps.caps.v2.max_shader_buffer_other_stages;
1207    if (!max_shader_buffer)
1208       return;
1209    virgl_encode_set_shader_buffers(vctx, shader, start_slot, count, buffers);
1210 }
1211
1212 static void virgl_create_fence_fd(struct pipe_context *ctx,
1213                                   struct pipe_fence_handle **fence,
1214                                   int fd,
1215                                   enum pipe_fd_type type)
1216 {
1217    assert(type == PIPE_FD_TYPE_NATIVE_SYNC);
1218    struct virgl_screen *rs = virgl_screen(ctx->screen);
1219
1220    if (rs->vws->cs_create_fence)
1221       *fence = rs->vws->cs_create_fence(rs->vws, fd);
1222 }
1223
1224 static void virgl_fence_server_sync(struct pipe_context *ctx,
1225                                     struct pipe_fence_handle *fence)
1226 {
1227    struct virgl_context *vctx = virgl_context(ctx);
1228    struct virgl_screen *rs = virgl_screen(ctx->screen);
1229
1230    if (rs->vws->fence_server_sync)
1231       rs->vws->fence_server_sync(rs->vws, vctx->cbuf, fence);
1232 }
1233
1234 static void virgl_set_shader_images(struct pipe_context *ctx,
1235                                     enum pipe_shader_type shader,
1236                                     unsigned start_slot, unsigned count,
1237                                     const struct pipe_image_view *images)
1238 {
1239    struct virgl_context *vctx = virgl_context(ctx);
1240    struct virgl_screen *rs = virgl_screen(ctx->screen);
1241    struct virgl_shader_binding_state *binding =
1242       &vctx->shader_bindings[shader];
1243
1244    binding->image_enabled_mask &= ~u_bit_consecutive(start_slot, count);
1245    for (unsigned i = 0; i < count; i++) {
1246       unsigned idx = start_slot + i;
1247       if (images && images[i].resource) {
1248          struct virgl_resource *res = virgl_resource(images[i].resource);
1249          res->bind_history |= PIPE_BIND_SHADER_IMAGE;
1250
1251          pipe_resource_reference(&binding->images[idx].resource,
1252                                  images[i].resource);
1253          binding->images[idx] = images[i];
1254          binding->image_enabled_mask |= 1 << idx;
1255       } else {
1256          pipe_resource_reference(&binding->images[idx].resource, NULL);
1257       }
1258    }
1259
1260    uint32_t max_shader_images = (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) ?
1261      rs->caps.caps.v2.max_shader_image_frag_compute :
1262      rs->caps.caps.v2.max_shader_image_other_stages;
1263    if (!max_shader_images)
1264       return;
1265    virgl_encode_set_shader_images(vctx, shader, start_slot, count, images);
1266 }
1267
1268 static void virgl_memory_barrier(struct pipe_context *ctx,
1269                                  unsigned flags)
1270 {
1271    struct virgl_context *vctx = virgl_context(ctx);
1272    struct virgl_screen *rs = virgl_screen(ctx->screen);
1273
1274    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_MEMORY_BARRIER))
1275       return;
1276    virgl_encode_memory_barrier(vctx, flags);
1277 }
1278
1279 static void *virgl_create_compute_state(struct pipe_context *ctx,
1280                                         const struct pipe_compute_state *state)
1281 {
1282    struct virgl_context *vctx = virgl_context(ctx);
1283    uint32_t handle;
1284    const struct tgsi_token *new_tokens = state->prog;
1285    struct pipe_stream_output_info so_info = {};
1286    int ret;
1287
1288    handle = virgl_object_assign_handle();
1289    ret = virgl_encode_shader_state(vctx, handle, PIPE_SHADER_COMPUTE,
1290                                    &so_info,
1291                                    state->req_local_mem,
1292                                    new_tokens);
1293    if (ret) {
1294       return NULL;
1295    }
1296
1297    return (void *)(unsigned long)handle;
1298 }
1299
1300 static void virgl_bind_compute_state(struct pipe_context *ctx, void *state)
1301 {
1302    uint32_t handle = (unsigned long)state;
1303    struct virgl_context *vctx = virgl_context(ctx);
1304
1305    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_COMPUTE);
1306 }
1307
1308 static void virgl_delete_compute_state(struct pipe_context *ctx, void *state)
1309 {
1310    uint32_t handle = (unsigned long)state;
1311    struct virgl_context *vctx = virgl_context(ctx);
1312
1313    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
1314 }
1315
1316 static void virgl_launch_grid(struct pipe_context *ctx,
1317                               const struct pipe_grid_info *info)
1318 {
1319    struct virgl_context *vctx = virgl_context(ctx);
1320
1321    if (!vctx->num_compute)
1322       virgl_reemit_compute_resources(vctx);
1323    vctx->num_compute++;
1324
1325    virgl_encode_launch_grid(vctx, info);
1326 }
1327
1328 static void
1329 virgl_release_shader_binding(struct virgl_context *vctx,
1330                              enum pipe_shader_type shader_type)
1331 {
1332    struct virgl_shader_binding_state *binding =
1333       &vctx->shader_bindings[shader_type];
1334
1335    while (binding->view_enabled_mask) {
1336       int i = u_bit_scan(&binding->view_enabled_mask);
1337       pipe_sampler_view_reference(
1338             (struct pipe_sampler_view **)&binding->views[i], NULL);
1339    }
1340
1341    while (binding->ubo_enabled_mask) {
1342       int i = u_bit_scan(&binding->ubo_enabled_mask);
1343       pipe_resource_reference(&binding->ubos[i].buffer, NULL);
1344    }
1345
1346    while (binding->ssbo_enabled_mask) {
1347       int i = u_bit_scan(&binding->ssbo_enabled_mask);
1348       pipe_resource_reference(&binding->ssbos[i].buffer, NULL);
1349    }
1350
1351    while (binding->image_enabled_mask) {
1352       int i = u_bit_scan(&binding->image_enabled_mask);
1353       pipe_resource_reference(&binding->images[i].resource, NULL);
1354    }
1355 }
1356
1357 static void
1358 virgl_context_destroy( struct pipe_context *ctx )
1359 {
1360    struct virgl_context *vctx = virgl_context(ctx);
1361    struct virgl_screen *rs = virgl_screen(ctx->screen);
1362    enum pipe_shader_type shader_type;
1363
1364    vctx->framebuffer.zsbuf = NULL;
1365    vctx->framebuffer.nr_cbufs = 0;
1366    virgl_encoder_destroy_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1367    virgl_flush_eq(vctx, vctx, NULL);
1368
1369    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++)
1370       virgl_release_shader_binding(vctx, shader_type);
1371
1372    while (vctx->atomic_buffer_enabled_mask) {
1373       int i = u_bit_scan(&vctx->atomic_buffer_enabled_mask);
1374       pipe_resource_reference(&vctx->atomic_buffers[i].buffer, NULL);
1375    }
1376
1377    rs->vws->cmd_buf_destroy(vctx->cbuf);
1378    if (vctx->uploader)
1379       u_upload_destroy(vctx->uploader);
1380    if (vctx->supports_staging)
1381       virgl_staging_destroy(&vctx->staging);
1382    util_primconvert_destroy(vctx->primconvert);
1383    virgl_transfer_queue_fini(&vctx->queue);
1384
1385    slab_destroy_child(&vctx->transfer_pool);
1386    FREE(vctx);
1387 }
1388
1389 static void virgl_get_sample_position(struct pipe_context *ctx,
1390                                       unsigned sample_count,
1391                                       unsigned index,
1392                                       float *out_value)
1393 {
1394    struct virgl_context *vctx = virgl_context(ctx);
1395    struct virgl_screen *vs = virgl_screen(vctx->base.screen);
1396
1397    if (sample_count > vs->caps.caps.v1.max_samples) {
1398       debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
1399                    sample_count, vs->caps.caps.v1.max_samples);
1400       return;
1401    }
1402
1403    /* The following is basically copied from dri/i965gen6_get_sample_position
1404     * The only addition is that we hold the msaa positions for all sample
1405     * counts in a flat array. */
1406    uint32_t bits = 0;
1407    if (sample_count == 1) {
1408       out_value[0] = out_value[1] = 0.5f;
1409       return;
1410    } else if (sample_count == 2) {
1411       bits = vs->caps.caps.v2.sample_locations[0] >> (8 * index);
1412    } else if (sample_count <= 4) {
1413       bits = vs->caps.caps.v2.sample_locations[1] >> (8 * index);
1414    } else if (sample_count <= 8) {
1415       bits = vs->caps.caps.v2.sample_locations[2 + (index >> 2)] >> (8 * (index & 3));
1416    } else if (sample_count <= 16) {
1417       bits = vs->caps.caps.v2.sample_locations[4 + (index >> 2)] >> (8 * (index & 3));
1418    }
1419    out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
1420    out_value[1] = (bits & 0xf) / 16.0f;
1421
1422    if (virgl_debug & VIRGL_DEBUG_VERBOSE)
1423       debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
1424                    index, sample_count, out_value[0], out_value[1]);
1425 }
1426
1427 static void virgl_send_tweaks(struct virgl_context *vctx, struct virgl_screen *rs)
1428 {
1429    if (rs->tweak_gles_emulate_bgra)
1430       virgl_encode_tweak(vctx, virgl_tweak_gles_brga_emulate, 1);
1431
1432    if (rs->tweak_gles_apply_bgra_dest_swizzle)
1433       virgl_encode_tweak(vctx, virgl_tweak_gles_brga_apply_dest_swizzle, 1);
1434
1435    if (rs->tweak_gles_tf3_value > 0)
1436       virgl_encode_tweak(vctx, virgl_tweak_gles_tf3_samples_passes_multiplier,
1437                          rs->tweak_gles_tf3_value);
1438 }
1439
1440 struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
1441                                           void *priv,
1442                                           unsigned flags)
1443 {
1444    struct virgl_context *vctx;
1445    struct virgl_screen *rs = virgl_screen(pscreen);
1446    vctx = CALLOC_STRUCT(virgl_context);
1447    const char *host_debug_flagstring;
1448
1449    vctx->cbuf = rs->vws->cmd_buf_create(rs->vws, VIRGL_MAX_CMDBUF_DWORDS);
1450    if (!vctx->cbuf) {
1451       FREE(vctx);
1452       return NULL;
1453    }
1454
1455    vctx->base.destroy = virgl_context_destroy;
1456    vctx->base.create_surface = virgl_create_surface;
1457    vctx->base.surface_destroy = virgl_surface_destroy;
1458    vctx->base.set_framebuffer_state = virgl_set_framebuffer_state;
1459    vctx->base.create_blend_state = virgl_create_blend_state;
1460    vctx->base.bind_blend_state = virgl_bind_blend_state;
1461    vctx->base.delete_blend_state = virgl_delete_blend_state;
1462    vctx->base.create_depth_stencil_alpha_state = virgl_create_depth_stencil_alpha_state;
1463    vctx->base.bind_depth_stencil_alpha_state = virgl_bind_depth_stencil_alpha_state;
1464    vctx->base.delete_depth_stencil_alpha_state = virgl_delete_depth_stencil_alpha_state;
1465    vctx->base.create_rasterizer_state = virgl_create_rasterizer_state;
1466    vctx->base.bind_rasterizer_state = virgl_bind_rasterizer_state;
1467    vctx->base.delete_rasterizer_state = virgl_delete_rasterizer_state;
1468
1469    vctx->base.set_viewport_states = virgl_set_viewport_states;
1470    vctx->base.create_vertex_elements_state = virgl_create_vertex_elements_state;
1471    vctx->base.bind_vertex_elements_state = virgl_bind_vertex_elements_state;
1472    vctx->base.delete_vertex_elements_state = virgl_delete_vertex_elements_state;
1473    vctx->base.set_vertex_buffers = virgl_set_vertex_buffers;
1474    vctx->base.set_constant_buffer = virgl_set_constant_buffer;
1475
1476    vctx->base.set_tess_state = virgl_set_tess_state;
1477    vctx->base.create_vs_state = virgl_create_vs_state;
1478    vctx->base.create_tcs_state = virgl_create_tcs_state;
1479    vctx->base.create_tes_state = virgl_create_tes_state;
1480    vctx->base.create_gs_state = virgl_create_gs_state;
1481    vctx->base.create_fs_state = virgl_create_fs_state;
1482
1483    vctx->base.bind_vs_state = virgl_bind_vs_state;
1484    vctx->base.bind_tcs_state = virgl_bind_tcs_state;
1485    vctx->base.bind_tes_state = virgl_bind_tes_state;
1486    vctx->base.bind_gs_state = virgl_bind_gs_state;
1487    vctx->base.bind_fs_state = virgl_bind_fs_state;
1488
1489    vctx->base.delete_vs_state = virgl_delete_vs_state;
1490    vctx->base.delete_tcs_state = virgl_delete_tcs_state;
1491    vctx->base.delete_tes_state = virgl_delete_tes_state;
1492    vctx->base.delete_gs_state = virgl_delete_gs_state;
1493    vctx->base.delete_fs_state = virgl_delete_fs_state;
1494
1495    vctx->base.create_compute_state = virgl_create_compute_state;
1496    vctx->base.bind_compute_state = virgl_bind_compute_state;
1497    vctx->base.delete_compute_state = virgl_delete_compute_state;
1498    vctx->base.launch_grid = virgl_launch_grid;
1499
1500    vctx->base.clear = virgl_clear;
1501    vctx->base.draw_vbo = virgl_draw_vbo;
1502    vctx->base.flush = virgl_flush_from_st;
1503    vctx->base.screen = pscreen;
1504    vctx->base.create_sampler_view = virgl_create_sampler_view;
1505    vctx->base.sampler_view_destroy = virgl_destroy_sampler_view;
1506    vctx->base.set_sampler_views = virgl_set_sampler_views;
1507    vctx->base.texture_barrier = virgl_texture_barrier;
1508
1509    vctx->base.create_sampler_state = virgl_create_sampler_state;
1510    vctx->base.delete_sampler_state = virgl_delete_sampler_state;
1511    vctx->base.bind_sampler_states = virgl_bind_sampler_states;
1512
1513    vctx->base.set_polygon_stipple = virgl_set_polygon_stipple;
1514    vctx->base.set_scissor_states = virgl_set_scissor_states;
1515    vctx->base.set_sample_mask = virgl_set_sample_mask;
1516    vctx->base.set_min_samples = virgl_set_min_samples;
1517    vctx->base.set_stencil_ref = virgl_set_stencil_ref;
1518    vctx->base.set_clip_state = virgl_set_clip_state;
1519
1520    vctx->base.set_blend_color = virgl_set_blend_color;
1521
1522    vctx->base.get_sample_position = virgl_get_sample_position;
1523
1524    vctx->base.resource_copy_region = virgl_resource_copy_region;
1525    vctx->base.flush_resource = virgl_flush_resource;
1526    vctx->base.blit =  virgl_blit;
1527    vctx->base.create_fence_fd = virgl_create_fence_fd;
1528    vctx->base.fence_server_sync = virgl_fence_server_sync;
1529
1530    vctx->base.set_shader_buffers = virgl_set_shader_buffers;
1531    vctx->base.set_hw_atomic_buffers = virgl_set_hw_atomic_buffers;
1532    vctx->base.set_shader_images = virgl_set_shader_images;
1533    vctx->base.memory_barrier = virgl_memory_barrier;
1534
1535    virgl_init_context_resource_functions(&vctx->base);
1536    virgl_init_query_functions(vctx);
1537    virgl_init_so_functions(vctx);
1538
1539    slab_create_child(&vctx->transfer_pool, &rs->transfer_pool);
1540    virgl_transfer_queue_init(&vctx->queue, vctx);
1541    vctx->encoded_transfers = (rs->vws->supports_encoded_transfers &&
1542                        (rs->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFER));
1543
1544    /* Reserve some space for transfers. */
1545    if (vctx->encoded_transfers)
1546       vctx->cbuf->cdw = VIRGL_MAX_TBUF_DWORDS;
1547
1548    vctx->primconvert = util_primconvert_create(&vctx->base, rs->caps.caps.v1.prim_mask);
1549    vctx->uploader = u_upload_create(&vctx->base, 1024 * 1024,
1550                                      PIPE_BIND_INDEX_BUFFER, PIPE_USAGE_STREAM, 0);
1551    if (!vctx->uploader)
1552            goto fail;
1553    vctx->base.stream_uploader = vctx->uploader;
1554    vctx->base.const_uploader = vctx->uploader;
1555
1556    /* We use a special staging buffer as the source of copy transfers. */
1557    if ((rs->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_TRANSFER) &&
1558        vctx->encoded_transfers) {
1559       virgl_staging_init(&vctx->staging, &vctx->base, 1024 * 1024);
1560       vctx->supports_staging = true;
1561    }
1562
1563    vctx->hw_sub_ctx_id = rs->sub_ctx_id++;
1564    virgl_encoder_create_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1565
1566    virgl_encoder_set_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1567
1568    if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_GUEST_MAY_INIT_LOG) {
1569       host_debug_flagstring = getenv("VIRGL_HOST_DEBUG");
1570       if (host_debug_flagstring)
1571          virgl_encode_host_debug_flagstring(vctx, host_debug_flagstring);
1572    }
1573
1574    if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_APP_TWEAK_SUPPORT)
1575       virgl_send_tweaks(vctx, rs);
1576
1577    return &vctx->base;
1578 fail:
1579    virgl_context_destroy(&vctx->base);
1580    return NULL;
1581 }