src/gallium/drivers/virgl/virgl_screen.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "util/u_memory.h"
  24 #include "util/format/u_format.h"
  25 #include "util/format/u_format_s3tc.h"
  26 #include "util/u_screen.h"
  27 #include "util/u_video.h"
  28 #include "util/u_math.h"
  29 #include "util/os_time.h"
  30 #include "util/xmlconfig.h"
  31 #include "pipe/p_defines.h"
  32 #include "pipe/p_screen.h"
  33
  34 #include "tgsi/tgsi_exec.h"
  35
  36 #include "virgl_screen.h"
  37 #include "virgl_resource.h"
  38 #include "virgl_public.h"
  39 #include "virgl_context.h"
  40 #include "virgl_protocol.h"
  41
  42 int virgl_debug = 0;
  43 static const struct debug_named_value debug_options[] = {
  44    { "verbose",   VIRGL_DEBUG_VERBOSE,             NULL },
  45    { "tgsi",      VIRGL_DEBUG_TGSI,                NULL },
  46    { "emubgra",   VIRGL_DEBUG_EMULATE_BGRA,        "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
  47    { "bgraswz",   VIRGL_DEBUG_BGRA_DEST_SWIZZLE,   "Enable tweak to swizzle emulated BGRA on GLES hosts" },
  48    { "sync",      VIRGL_DEBUG_SYNC,                "Sync after every flush" },
  49    { "xfer",      VIRGL_DEBUG_XFER,                "Do not optimize for transfers" },
  50    DEBUG_NAMED_VALUE_END
  51 };
  52 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
  53
  54 static const char *
  55 virgl_get_vendor(struct pipe_screen *screen)
  56 {
  57    return "Red Hat";
  58 }
  59
  60
  61 static const char *
  62 virgl_get_name(struct pipe_screen *screen)
  63 {
  64    return "virgl";
  65 }
  66
  67 static int
  68 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
  69 {
  70    struct virgl_screen *vscreen = virgl_screen(screen);
  71    switch (param) {
  72    case PIPE_CAP_NPOT_TEXTURES:
  73       return 1;
  74    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  75    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  76    case PIPE_CAP_VERTEX_SHADER_SATURATE:
  77       return 1;
  78    case PIPE_CAP_ANISOTROPIC_FILTER:
  79       return 1;
  80    case PIPE_CAP_POINT_SPRITE:
  81       return 1;
  82    case PIPE_CAP_MAX_RENDER_TARGETS:
  83       return vscreen->caps.caps.v1.max_render_targets;
  84    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  85       return vscreen->caps.caps.v1.max_dual_source_render_targets;
  86    case PIPE_CAP_OCCLUSION_QUERY:
  87       return vscreen->caps.caps.v1.bset.occlusion_query;
  88    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  89    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  90       return vscreen->caps.caps.v1.bset.mirror_clamp;
  91    case PIPE_CAP_TEXTURE_SWIZZLE:
  92       return 1;
  93    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
  94       if (vscreen->caps.caps.v2.max_texture_2d_size)
  95          return vscreen->caps.caps.v2.max_texture_2d_size;
  96       return 16384;
  97    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  98       if (vscreen->caps.caps.v2.max_texture_3d_size)
  99          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
 100       return 9; /* 256 x 256 x 256 */
 101    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 102       if (vscreen->caps.caps.v2.max_texture_cube_size)
 103          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
 104       return 13; /* 4K x 4K */
 105    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106       return 1;
 107    case PIPE_CAP_INDEP_BLEND_ENABLE:
 108       return vscreen->caps.caps.v1.bset.indep_blend_enable;
 109    case PIPE_CAP_INDEP_BLEND_FUNC:
 110       return vscreen->caps.caps.v1.bset.indep_blend_func;
 111    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 112    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 113    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 114       return 1;
 115    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 116       return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
 117    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 118       if (vscreen->caps.caps.v1.bset.depth_clip_disable)
 119          return 1;
 120       if (vscreen->caps.caps.v2.host_feature_check_version >= 3)
 121          return 2;
 122       return 0;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return vscreen->caps.caps.v1.max_streamout_buffers;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127       return 16*4;
 128    case PIPE_CAP_PRIMITIVE_RESTART:
 129       return vscreen->caps.caps.v1.bset.primitive_restart;
 130    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 131       return vscreen->caps.caps.v1.bset.shader_stencil_export;
 132    case PIPE_CAP_TGSI_INSTANCEID:
 133    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 134       return 1;
 135    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 136       return vscreen->caps.caps.v1.bset.seamless_cube_map;
 137    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 138       return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
 139    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 140       return vscreen->caps.caps.v1.max_texture_array_layers;
 141    case PIPE_CAP_MIN_TEXEL_OFFSET:
 142       return vscreen->caps.caps.v2.min_texel_offset;
 143    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 144       return vscreen->caps.caps.v2.min_texture_gather_offset;
 145    case PIPE_CAP_MAX_TEXEL_OFFSET:
 146       return vscreen->caps.caps.v2.max_texel_offset;
 147    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 148       return vscreen->caps.caps.v2.max_texture_gather_offset;
 149    case PIPE_CAP_CONDITIONAL_RENDER:
 150       return vscreen->caps.caps.v1.bset.conditional_render;
 151    case PIPE_CAP_TEXTURE_BARRIER:
 152       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
 153    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 154       return 1;
 155    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 156    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 157       return vscreen->caps.caps.v1.bset.color_clamping;
 158    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 159       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
 160             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 161    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 162       return vscreen->caps.caps.v1.glsl_level;
 163    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 164       return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
 165    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 166    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 167       return 0;
 168    case PIPE_CAP_COMPUTE:
 169       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
 170    case PIPE_CAP_USER_VERTEX_BUFFERS:
 171       return 0;
 172    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 173       return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
 174    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 175    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 176       return vscreen->caps.caps.v1.bset.streamout_pause_resume;
 177    case PIPE_CAP_START_INSTANCE:
 178       return vscreen->caps.caps.v1.bset.start_instance;
 179    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 180    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 181    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 182    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 183    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 184       return 0;
 185    case PIPE_CAP_QUERY_TIMESTAMP:
 186       return 1;
 187    case PIPE_CAP_QUERY_TIME_ELAPSED:
 188       return 1;
 189    case PIPE_CAP_TGSI_TEXCOORD:
 190       return 0;
 191    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 192       return VIRGL_MAP_BUFFER_ALIGNMENT;
 193    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 194       return vscreen->caps.caps.v1.max_tbo_size > 0;
 195    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 196       return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
 197    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 198       return 0;
 199    case PIPE_CAP_CUBE_MAP_ARRAY:
 200       return vscreen->caps.caps.v1.bset.cube_map_array;
 201    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 202       return vscreen->caps.caps.v1.bset.texture_multisample;
 203    case PIPE_CAP_MAX_VIEWPORTS:
 204       return vscreen->caps.caps.v1.max_viewports;
 205    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 206       return vscreen->caps.caps.v1.max_tbo_size;
 207    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 208    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 209    case PIPE_CAP_ENDIANNESS:
 210       return 0;
 211    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 212    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 213       return 1;
 214    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 215       return 0;
 216    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 217       return vscreen->caps.caps.v2.max_geom_output_vertices;
 218    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 219       return vscreen->caps.caps.v2.max_geom_total_output_components;
 220    case PIPE_CAP_TEXTURE_QUERY_LOD:
 221       return vscreen->caps.caps.v1.bset.texture_query_lod;
 222    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 223       return vscreen->caps.caps.v1.max_texture_gather_components;
 224    case PIPE_CAP_DRAW_INDIRECT:
 225       return vscreen->caps.caps.v1.bset.has_indirect_draw;
 226    case PIPE_CAP_SAMPLE_SHADING:
 227    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 228       return vscreen->caps.caps.v1.bset.has_sample_shading;
 229    case PIPE_CAP_CULL_DISTANCE:
 230       return vscreen->caps.caps.v1.bset.has_cull;
 231    case PIPE_CAP_MAX_VERTEX_STREAMS:
 232       return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
 233               (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
 234    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 235       return vscreen->caps.caps.v1.bset.conditional_render_inverted;
 236    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 237       return vscreen->caps.caps.v1.bset.derivative_control;
 238    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 239       return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
 240    case PIPE_CAP_QUERY_SO_OVERFLOW:
 241       return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
 242    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 243       return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
 244    case PIPE_CAP_DOUBLES:
 245       return vscreen->caps.caps.v1.bset.has_fp64 ||
 246             (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64);
 247    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 248       return vscreen->caps.caps.v2.max_shader_patch_varyings;
 249    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 250       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
 251    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 252       return vscreen->caps.caps.v2.max_vertex_attrib_stride;
 253    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 254       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
 255    case PIPE_CAP_TGSI_TXQS:
 256       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
 257    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 258       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
 259    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 260       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
 261    case PIPE_CAP_FBFETCH:
 262       return (vscreen->caps.caps.v2.capability_bits &
 263               VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
 264    case PIPE_CAP_TGSI_CLOCK:
 265       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
 266    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 267       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
 268    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 269       return vscreen->caps.caps.v2.max_combined_shader_buffers;
 270    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 271       return vscreen->caps.caps.v2.max_combined_atomic_counters;
 272    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 273       return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
 274    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 275    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 276       return 1; /* TODO: need to introduce a hw-cap for this */
 277    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 278       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
 279    case PIPE_CAP_MAX_VARYINGS:
 280       if (vscreen->caps.caps.v1.glsl_level < 150)
 281          return vscreen->caps.caps.v2.max_vertex_attribs;
 282       return 32;
 283    case PIPE_CAP_FAKE_SW_MSAA:
 284       /* If the host supports only one sample (e.g., if it is using softpipe),
 285        * fake multisampling to able to advertise higher GL versions. */
 286       return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
 287    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 288       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
 289    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 290       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
 291    case PIPE_CAP_TEXTURE_GATHER_SM5:
 292    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 293    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 294    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 295    case PIPE_CAP_VERTEXID_NOBASE:
 296    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 297    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 298    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 299    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 300    case PIPE_CAP_SHAREABLE_SHADERS:
 301    case PIPE_CAP_DRAW_PARAMETERS:
 302    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 303    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 304    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 305    case PIPE_CAP_INVALIDATE_BUFFER:
 306    case PIPE_CAP_GENERATE_MIPMAP:
 307    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 308    case PIPE_CAP_STRING_MARKER:
 309    case PIPE_CAP_QUERY_MEMORY_INFO:
 310    case PIPE_CAP_PCI_GROUP:
 311    case PIPE_CAP_PCI_BUS:
 312    case PIPE_CAP_PCI_DEVICE:
 313    case PIPE_CAP_PCI_FUNCTION:
 314    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 315    case PIPE_CAP_TGSI_VOTE:
 316    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 317    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 318    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 319    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 320    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 321    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 322    case PIPE_CAP_INT64:
 323    case PIPE_CAP_INT64_DIVMOD:
 324    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 325    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 326    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 327    case PIPE_CAP_TGSI_BALLOT:
 328    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 329    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 330    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 331    case PIPE_CAP_POST_DEPTH_COVERAGE:
 332    case PIPE_CAP_BINDLESS_TEXTURE:
 333    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 334    case PIPE_CAP_MEMOBJ:
 335    case PIPE_CAP_LOAD_CONSTBUF:
 336    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 337    case PIPE_CAP_TILE_RASTER_ORDER:
 338    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 339    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 340    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 341    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 342    case PIPE_CAP_FENCE_SIGNAL:
 343    case PIPE_CAP_CONSTBUF0_FLAGS:
 344    case PIPE_CAP_PACKED_UNIFORMS:
 345    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 346    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 347    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 348    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 349    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 350    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 351    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 352    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 353       return 0;
 354    case PIPE_CAP_CLEAR_TEXTURE:
 355       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLEAR_TEXTURE;
 356    case PIPE_CAP_CLIP_HALFZ:
 357       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
 358    case PIPE_CAP_MAX_GS_INVOCATIONS:
 359       return 32;
 360    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 361       return 1 << 27;
 362    case PIPE_CAP_VENDOR_ID:
 363       return 0x1af4;
 364    case PIPE_CAP_DEVICE_ID:
 365       return 0x1010;
 366    case PIPE_CAP_ACCELERATED:
 367       return 1;
 368    case PIPE_CAP_UMA:
 369    case PIPE_CAP_VIDEO_MEMORY:
 370       return 0;
 371    case PIPE_CAP_NATIVE_FENCE_FD:
 372       return vscreen->vws->supports_fences;
 373    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 374       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
 375             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 376    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 377       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 378    default:
 379       return u_pipe_screen_get_param_defaults(screen, param);
 380    }
 381 }
 382
 383 static int
 384 virgl_get_shader_param(struct pipe_screen *screen,
 385                        enum pipe_shader_type shader,
 386                        enum pipe_shader_cap param)
 387 {
 388    struct virgl_screen *vscreen = virgl_screen(screen);
 389
 390    if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
 391        !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
 392       return 0;
 393
 394    if (shader == PIPE_SHADER_COMPUTE &&
 395        !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 396      return 0;
 397
 398    switch(shader)
 399    {
 400    case PIPE_SHADER_FRAGMENT:
 401    case PIPE_SHADER_VERTEX:
 402    case PIPE_SHADER_GEOMETRY:
 403    case PIPE_SHADER_TESS_CTRL:
 404    case PIPE_SHADER_TESS_EVAL:
 405    case PIPE_SHADER_COMPUTE:
 406       switch (param) {
 407       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 408       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 409       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 410       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 411          return INT_MAX;
 412       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 413       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 414       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 415          return 1;
 416       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 417       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 418          return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 419       case PIPE_SHADER_CAP_MAX_INPUTS:
 420          if (vscreen->caps.caps.v1.glsl_level < 150)
 421             return vscreen->caps.caps.v2.max_vertex_attribs;
 422          return (shader == PIPE_SHADER_VERTEX ||
 423                  shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
 424       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 425          if (shader == PIPE_SHADER_FRAGMENT)
 426             return vscreen->caps.caps.v1.max_render_targets;
 427          return vscreen->caps.caps.v2.max_vertex_outputs;
 428      // case PIPE_SHADER_CAP_MAX_CONSTS:
 429      //    return 4096;
 430       case PIPE_SHADER_CAP_MAX_TEMPS:
 431          return 256;
 432       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 433          return vscreen->caps.caps.v1.max_uniform_blocks;
 434     //  case PIPE_SHADER_CAP_MAX_ADDRS:
 435      //    return 1;
 436       case PIPE_SHADER_CAP_SUBROUTINES:
 437          return 1;
 438       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 439             return 16;
 440       case PIPE_SHADER_CAP_INTEGERS:
 441          return vscreen->caps.caps.v1.glsl_level >= 130;
 442       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 443          return 32;
 444       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 445          return 4096 * sizeof(float[4]);
 446       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 447          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 448             return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
 449          else
 450             return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
 451       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 452          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 453             return vscreen->caps.caps.v2.max_shader_image_frag_compute;
 454          else
 455             return vscreen->caps.caps.v2.max_shader_image_other_stages;
 456       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 457          return (1 << PIPE_SHADER_IR_TGSI);
 458       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 459          return vscreen->caps.caps.v2.max_atomic_counters[shader];
 460       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 461          return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
 462       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 463       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 464       case PIPE_SHADER_CAP_INT64_ATOMICS:
 465       case PIPE_SHADER_CAP_FP16:
 466       case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 467       case PIPE_SHADER_CAP_INT16:
 468          return 0;
 469       default:
 470          return 0;
 471       }
 472    default:
 473       return 0;
 474    }
 475 }
 476
 477 static float
 478 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 479 {
 480    struct virgl_screen *vscreen = virgl_screen(screen);
 481    switch (param) {
 482    case PIPE_CAPF_MAX_LINE_WIDTH:
 483       return vscreen->caps.caps.v2.max_aliased_line_width;
 484    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 485       return vscreen->caps.caps.v2.max_smooth_line_width;
 486    case PIPE_CAPF_MAX_POINT_WIDTH:
 487       return vscreen->caps.caps.v2.max_aliased_point_size;
 488    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 489       return vscreen->caps.caps.v2.max_smooth_point_size;
 490    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 491       return 16.0;
 492    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 493       return vscreen->caps.caps.v2.max_texture_lod_bias;
 494    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 495    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 496    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 497       return 0.0f;
 498    }
 499    /* should only get here on unhandled cases */
 500    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 501    return 0.0;
 502 }
 503
 504 static int
 505 virgl_get_compute_param(struct pipe_screen *screen,
 506                         enum pipe_shader_ir ir_type,
 507                         enum pipe_compute_cap param,
 508                         void *ret)
 509 {
 510    struct virgl_screen *vscreen = virgl_screen(screen);
 511    if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 512       return 0;
 513    switch (param) {
 514    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 515       if (ret) {
 516          uint64_t *grid_size = ret;
 517          grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
 518          grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
 519          grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
 520       }
 521       return 3 * sizeof(uint64_t) ;
 522    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 523       if (ret) {
 524          uint64_t *block_size = ret;
 525          block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
 526          block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
 527          block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
 528       }
 529       return 3 * sizeof(uint64_t);
 530    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 531       if (ret) {
 532          uint64_t *max_threads_per_block = ret;
 533          *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
 534       }
 535       return sizeof(uint64_t);
 536    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 537       if (ret) {
 538          uint64_t *max_local_size = ret;
 539          /* Value reported by the closed source driver. */
 540          *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
 541       }
 542       return sizeof(uint64_t);
 543    default:
 544       break;
 545    }
 546    return 0;
 547 }
 548
 549 static bool
 550 has_format_bit(struct virgl_supported_format_mask *mask,
 551                enum virgl_formats fmt)
 552 {
 553    assert(fmt < VIRGL_FORMAT_MAX);
 554    unsigned val = (unsigned)fmt;
 555    unsigned idx = val / 32;
 556    unsigned bit = val % 32;
 557    assert(idx < ARRAY_SIZE(mask->bitmask));
 558    return (mask->bitmask[idx] & (1u << bit)) != 0;
 559 }
 560
 561 bool
 562 virgl_has_readback_format(struct pipe_screen *screen,
 563                           enum virgl_formats fmt)
 564 {
 565    struct virgl_screen *vscreen = virgl_screen(screen);
 566    return has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats,
 567                          fmt);
 568 }
 569
 570 static bool
 571 virgl_is_vertex_format_supported(struct pipe_screen *screen,
 572                                  enum pipe_format format)
 573 {
 574    struct virgl_screen *vscreen = virgl_screen(screen);
 575    const struct util_format_description *format_desc;
 576    int i;
 577
 578    format_desc = util_format_description(format);
 579    if (!format_desc)
 580       return false;
 581
 582    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 583       int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
 584       int big = vformat / 32;
 585       int small = vformat % 32;
 586       if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
 587          return false;
 588       return true;
 589    }
 590
 591    /* Find the first non-VOID channel. */
 592    for (i = 0; i < 4; i++) {
 593       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 594          break;
 595       }
 596    }
 597
 598    if (i == 4)
 599       return false;
 600
 601    if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
 602       return false;
 603
 604    if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
 605       return false;
 606    return true;
 607 }
 608
 609 static bool
 610 virgl_format_check_bitmask(enum pipe_format format,
 611                            uint32_t bitmask[16],
 612                            bool may_emulate_bgra)
 613 {
 614    enum virgl_formats vformat = pipe_to_virgl_format(format);
 615    int big = vformat / 32;
 616    int small = vformat % 32;
 617    if ((bitmask[big] & (1 << small)))
 618       return true;
 619
 620    /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
 621     * emulate it by using a swizzled RGBx */
 622    if (may_emulate_bgra) {
 623       if (format == PIPE_FORMAT_B8G8R8A8_SRGB)
 624          format = PIPE_FORMAT_R8G8B8A8_SRGB;
 625       else if (format == PIPE_FORMAT_B8G8R8X8_SRGB)
 626          format = PIPE_FORMAT_R8G8B8X8_SRGB;
 627       else {
 628          return false;
 629       }
 630
 631       vformat = pipe_to_virgl_format(format);
 632       big = vformat / 32;
 633       small = vformat % 32;
 634       if (bitmask[big] & (1 << small))
 635          return true;
 636    }
 637    return false;
 638 }
 639
 640 /**
 641  * Query format support for creating a texture, drawing surface, etc.
 642  * \param format  the format to test
 643  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 644  */
 645 static bool
 646 virgl_is_format_supported( struct pipe_screen *screen,
 647                                  enum pipe_format format,
 648                                  enum pipe_texture_target target,
 649                                  unsigned sample_count,
 650                                  unsigned storage_sample_count,
 651                                  unsigned bind)
 652 {
 653    struct virgl_screen *vscreen = virgl_screen(screen);
 654    const struct util_format_description *format_desc;
 655    int i;
 656
 657    union virgl_caps *caps = &vscreen->caps.caps;
 658    boolean may_emulate_bgra = (caps->v2.capability_bits &
 659                                VIRGL_CAP_APP_TWEAK_SUPPORT) &&
 660                                vscreen->tweak_gles_emulate_bgra;
 661
 662    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 663       return false;
 664
 665    if (!util_is_power_of_two_or_zero(sample_count))
 666       return false;
 667
 668    assert(target == PIPE_BUFFER ||
 669           target == PIPE_TEXTURE_1D ||
 670           target == PIPE_TEXTURE_1D_ARRAY ||
 671           target == PIPE_TEXTURE_2D ||
 672           target == PIPE_TEXTURE_2D_ARRAY ||
 673           target == PIPE_TEXTURE_RECT ||
 674           target == PIPE_TEXTURE_3D ||
 675           target == PIPE_TEXTURE_CUBE ||
 676           target == PIPE_TEXTURE_CUBE_ARRAY);
 677
 678    format_desc = util_format_description(format);
 679    if (!format_desc)
 680       return false;
 681
 682    if (util_format_is_intensity(format))
 683       return false;
 684
 685    if (sample_count > 1) {
 686       if (!caps->v1.bset.texture_multisample)
 687          return false;
 688
 689       if (bind & PIPE_BIND_SHADER_IMAGE) {
 690          if (sample_count > caps->v2.max_image_samples)
 691             return false;
 692       }
 693
 694       if (sample_count > caps->v1.max_samples)
 695          return false;
 696    }
 697
 698    if (bind & PIPE_BIND_VERTEX_BUFFER) {
 699       return virgl_is_vertex_format_supported(screen, format);
 700    }
 701
 702    if (util_format_is_compressed(format) && target == PIPE_BUFFER)
 703       return false;
 704
 705    /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
 706    if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
 707        format == PIPE_FORMAT_R32G32B32_SINT ||
 708        format == PIPE_FORMAT_R32G32B32_UINT) &&
 709        target != PIPE_BUFFER)
 710       return false;
 711
 712    if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
 713         format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
 714         format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
 715        target == PIPE_TEXTURE_3D)
 716       return false;
 717
 718
 719    if (bind & PIPE_BIND_RENDER_TARGET) {
 720       /* For ARB_framebuffer_no_attachments. */
 721       if (format == PIPE_FORMAT_NONE)
 722          return TRUE;
 723
 724       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 725          return false;
 726
 727       /*
 728        * Although possible, it is unnatural to render into compressed or YUV
 729        * surfaces. So disable these here to avoid going into weird paths
 730        * inside gallium frontends.
 731        */
 732       if (format_desc->block.width != 1 ||
 733           format_desc->block.height != 1)
 734          return false;
 735
 736       if (!virgl_format_check_bitmask(format,
 737                                       caps->v1.render.bitmask,
 738                                       may_emulate_bgra))
 739          return false;
 740    }
 741
 742    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 743       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 744          return false;
 745    }
 746
 747    if (bind & PIPE_BIND_SCANOUT) {
 748       if (!virgl_format_check_bitmask(format, caps->v2.scanout.bitmask, false))
 749          return false;
 750    }
 751
 752    /*
 753     * All other operations (sampling, transfer, etc).
 754     */
 755
 756    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 757       goto out_lookup;
 758    }
 759    if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 760       goto out_lookup;
 761    }
 762    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
 763       goto out_lookup;
 764    }
 765    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC) {
 766       goto out_lookup;
 767    }
 768
 769    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 770       goto out_lookup;
 771    } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 772       goto out_lookup;
 773    }
 774
 775    /* Find the first non-VOID channel. */
 776    for (i = 0; i < 4; i++) {
 777       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 778          break;
 779       }
 780    }
 781
 782    if (i == 4)
 783       return false;
 784
 785    /* no L4A4 */
 786    if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
 787       return false;
 788
 789  out_lookup:
 790    return virgl_format_check_bitmask(format,
 791                                      caps->v1.sampler.bitmask,
 792                                      may_emulate_bgra);
 793 }
 794
 795 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
 796                                       struct pipe_resource *res,
 797                                       unsigned level, unsigned layer,
 798                                     void *winsys_drawable_handle, struct pipe_box *sub_box)
 799 {
 800    struct virgl_screen *vscreen = virgl_screen(screen);
 801    struct virgl_winsys *vws = vscreen->vws;
 802    struct virgl_resource *vres = virgl_resource(res);
 803
 804    if (vws->flush_frontbuffer)
 805       vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
 806                              sub_box);
 807 }
 808
 809 static void virgl_fence_reference(struct pipe_screen *screen,
 810                                   struct pipe_fence_handle **ptr,
 811                                   struct pipe_fence_handle *fence)
 812 {
 813    struct virgl_screen *vscreen = virgl_screen(screen);
 814    struct virgl_winsys *vws = vscreen->vws;
 815
 816    vws->fence_reference(vws, ptr, fence);
 817 }
 818
 819 static bool virgl_fence_finish(struct pipe_screen *screen,
 820                                struct pipe_context *ctx,
 821                                struct pipe_fence_handle *fence,
 822                                uint64_t timeout)
 823 {
 824    struct virgl_screen *vscreen = virgl_screen(screen);
 825    struct virgl_winsys *vws = vscreen->vws;
 826
 827    return vws->fence_wait(vws, fence, timeout);
 828 }
 829
 830 static int virgl_fence_get_fd(struct pipe_screen *screen,
 831             struct pipe_fence_handle *fence)
 832 {
 833    struct virgl_screen *vscreen = virgl_screen(screen);
 834    struct virgl_winsys *vws = vscreen->vws;
 835
 836    return vws->fence_get_fd(vws, fence);
 837 }
 838
 839 static uint64_t
 840 virgl_get_timestamp(struct pipe_screen *_screen)
 841 {
 842    return os_time_get_nano();
 843 }
 844
 845 static void
 846 virgl_destroy_screen(struct pipe_screen *screen)
 847 {
 848    struct virgl_screen *vscreen = virgl_screen(screen);
 849    struct virgl_winsys *vws = vscreen->vws;
 850
 851    slab_destroy_parent(&vscreen->transfer_pool);
 852
 853    if (vws)
 854       vws->destroy(vws);
 855    FREE(vscreen);
 856 }
 857
 858 static void
 859 fixup_formats(union virgl_caps *caps, struct virgl_supported_format_mask *mask)
 860 {
 861    const size_t size = ARRAY_SIZE(mask->bitmask);
 862    for (int i = 0; i < size; ++i) {
 863       if (mask->bitmask[i] != 0)
 864          return; /* we got some formats, we definately have a new protocol */
 865    }
 866
 867    /* old protocol used; fall back to considering all sampleable formats valid
 868     * readback-formats
 869     */
 870    for (int i = 0; i < size; ++i)
 871       mask->bitmask[i] = caps->v1.sampler.bitmask[i];
 872 }
 873
 874 struct pipe_screen *
 875 virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config)
 876 {
 877    struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
 878
 879    const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra";
 880    const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
 881    const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
 882
 883    if (!screen)
 884       return NULL;
 885
 886    virgl_debug = debug_get_option_virgl_debug();
 887
 888    if (config && config->options) {
 889       screen->tweak_gles_emulate_bgra =
 890             driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA);
 891       screen->tweak_gles_apply_bgra_dest_swizzle =
 892             driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE);
 893       screen->tweak_gles_tf3_value =
 894             driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
 895    }
 896
 897    screen->tweak_gles_emulate_bgra |= !!(virgl_debug & VIRGL_DEBUG_EMULATE_BGRA);
 898    screen->tweak_gles_apply_bgra_dest_swizzle |= !!(virgl_debug & VIRGL_DEBUG_BGRA_DEST_SWIZZLE);
 899
 900    screen->vws = vws;
 901    screen->base.get_name = virgl_get_name;
 902    screen->base.get_vendor = virgl_get_vendor;
 903    screen->base.get_param = virgl_get_param;
 904    screen->base.get_shader_param = virgl_get_shader_param;
 905    screen->base.get_compute_param = virgl_get_compute_param;
 906    screen->base.get_paramf = virgl_get_paramf;
 907    screen->base.is_format_supported = virgl_is_format_supported;
 908    screen->base.destroy = virgl_destroy_screen;
 909    screen->base.context_create = virgl_context_create;
 910    screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
 911    screen->base.get_timestamp = virgl_get_timestamp;
 912    screen->base.fence_reference = virgl_fence_reference;
 913    //screen->base.fence_signalled = virgl_fence_signalled;
 914    screen->base.fence_finish = virgl_fence_finish;
 915    screen->base.fence_get_fd = virgl_fence_get_fd;
 916
 917    virgl_init_screen_resource_functions(&screen->base);
 918
 919    vws->get_caps(vws, &screen->caps);
 920    fixup_formats(&screen->caps.caps,
 921                  &screen->caps.caps.v2.supported_readback_formats);
 922    fixup_formats(&screen->caps.caps, &screen->caps.caps.v2.scanout);
 923
 924    screen->refcnt = 1;
 925
 926    slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
 927
 928    return &screen->base;
 929 }