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[mesa.git] / src / gallium / frontends / vallium / val_pipeline.c
1 /*
2 * Copyright © 2019 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "val_private.h"
25
26 #include "glsl_types.h"
27 #include "spirv/nir_spirv.h"
28 #include "nir/nir_builder.h"
29 #include "val_lower_vulkan_resource.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32
33 #define SPIR_V_MAGIC_NUMBER 0x07230203
34
35 VkResult val_CreateShaderModule(
36 VkDevice _device,
37 const VkShaderModuleCreateInfo* pCreateInfo,
38 const VkAllocationCallbacks* pAllocator,
39 VkShaderModule* pShaderModule)
40 {
41 VAL_FROM_HANDLE(val_device, device, _device);
42 struct val_shader_module *module;
43
44 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
45 assert(pCreateInfo->flags == 0);
46
47 module = vk_alloc2(&device->alloc, pAllocator,
48 sizeof(*module) + pCreateInfo->codeSize, 8,
49 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
50 if (module == NULL)
51 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
52
53 vk_object_base_init(&device->vk, &module->base,
54 VK_OBJECT_TYPE_SHADER_MODULE);
55 module->size = pCreateInfo->codeSize;
56 memcpy(module->data, pCreateInfo->pCode, module->size);
57
58 *pShaderModule = val_shader_module_to_handle(module);
59
60 return VK_SUCCESS;
61
62 }
63
64 void val_DestroyShaderModule(
65 VkDevice _device,
66 VkShaderModule _module,
67 const VkAllocationCallbacks* pAllocator)
68 {
69 VAL_FROM_HANDLE(val_device, device, _device);
70 VAL_FROM_HANDLE(val_shader_module, module, _module);
71
72 if (!_module)
73 return;
74 vk_object_base_finish(&module->base);
75 vk_free2(&device->alloc, pAllocator, module);
76 }
77
78 void val_DestroyPipeline(
79 VkDevice _device,
80 VkPipeline _pipeline,
81 const VkAllocationCallbacks* pAllocator)
82 {
83 VAL_FROM_HANDLE(val_device, device, _device);
84 VAL_FROM_HANDLE(val_pipeline, pipeline, _pipeline);
85
86 if (!_pipeline)
87 return;
88
89 if (pipeline->shader_cso[PIPE_SHADER_VERTEX])
90 device->queue.ctx->delete_vs_state(device->queue.ctx, pipeline->shader_cso[PIPE_SHADER_VERTEX]);
91 if (pipeline->shader_cso[PIPE_SHADER_FRAGMENT])
92 device->queue.ctx->delete_fs_state(device->queue.ctx, pipeline->shader_cso[PIPE_SHADER_FRAGMENT]);
93 if (pipeline->shader_cso[PIPE_SHADER_GEOMETRY])
94 device->queue.ctx->delete_gs_state(device->queue.ctx, pipeline->shader_cso[PIPE_SHADER_GEOMETRY]);
95 if (pipeline->shader_cso[PIPE_SHADER_TESS_CTRL])
96 device->queue.ctx->delete_tcs_state(device->queue.ctx, pipeline->shader_cso[PIPE_SHADER_TESS_CTRL]);
97 if (pipeline->shader_cso[PIPE_SHADER_TESS_EVAL])
98 device->queue.ctx->delete_tes_state(device->queue.ctx, pipeline->shader_cso[PIPE_SHADER_TESS_EVAL]);
99 if (pipeline->shader_cso[PIPE_SHADER_COMPUTE])
100 device->queue.ctx->delete_compute_state(device->queue.ctx, pipeline->shader_cso[PIPE_SHADER_COMPUTE]);
101
102 if (!pipeline->is_compute_pipeline) {
103 for (unsigned i = 0; i < pipeline->graphics_create_info.stageCount; i++)
104 if (pipeline->graphics_create_info.pStages[i].pSpecializationInfo)
105 free((void *)pipeline->graphics_create_info.pStages[i].pSpecializationInfo);
106
107 free((void *)pipeline->graphics_create_info.pStages);
108 free((void *)pipeline->graphics_create_info.pVertexInputState->pVertexBindingDescriptions);
109 free((void *)pipeline->graphics_create_info.pVertexInputState->pVertexAttributeDescriptions);
110 free((void *)pipeline->graphics_create_info.pVertexInputState);
111 free((void *)pipeline->graphics_create_info.pInputAssemblyState);
112 if (pipeline->graphics_create_info.pViewportState) {
113 free((void *)pipeline->graphics_create_info.pViewportState->pViewports);
114 free((void *)pipeline->graphics_create_info.pViewportState->pScissors);
115 }
116 free((void *)pipeline->graphics_create_info.pViewportState);
117
118 if (pipeline->graphics_create_info.pTessellationState)
119 free((void *)pipeline->graphics_create_info.pTessellationState);
120 free((void *)pipeline->graphics_create_info.pRasterizationState);
121 free((void *)pipeline->graphics_create_info.pMultisampleState);
122 free((void *)pipeline->graphics_create_info.pDepthStencilState);
123 if (pipeline->graphics_create_info.pColorBlendState)
124 free((void *)pipeline->graphics_create_info.pColorBlendState->pAttachments);
125 free((void *)pipeline->graphics_create_info.pColorBlendState);
126 if (pipeline->graphics_create_info.pDynamicState)
127 free((void *)pipeline->graphics_create_info.pDynamicState->pDynamicStates);
128 free((void *)pipeline->graphics_create_info.pDynamicState);
129 } else
130 if (pipeline->compute_create_info.stage.pSpecializationInfo)
131 free((void *)pipeline->compute_create_info.stage.pSpecializationInfo);
132 vk_object_base_finish(&pipeline->base);
133 vk_free2(&device->alloc, pAllocator, pipeline);
134 }
135
136 static VkResult
137 deep_copy_shader_stage(struct VkPipelineShaderStageCreateInfo *dst,
138 const struct VkPipelineShaderStageCreateInfo *src)
139 {
140 dst->sType = src->sType;
141 dst->pNext = NULL;
142 dst->flags = src->flags;
143 dst->stage = src->stage;
144 dst->module = src->module;
145 dst->pName = src->pName;
146 dst->pSpecializationInfo = NULL;
147 if (src->pSpecializationInfo) {
148 const VkSpecializationInfo *src_spec = src->pSpecializationInfo;
149 VkSpecializationInfo *dst_spec = malloc(sizeof(VkSpecializationInfo) +
150 src_spec->mapEntryCount * sizeof(VkSpecializationMapEntry) +
151 src_spec->dataSize);
152 VkSpecializationMapEntry *maps = (VkSpecializationMapEntry *)(dst_spec + 1);
153 dst_spec->pMapEntries = maps;
154 void *pdata = (void *)(dst_spec->pMapEntries + src_spec->mapEntryCount);
155 dst_spec->pData = pdata;
156
157
158 dst_spec->mapEntryCount = src_spec->mapEntryCount;
159 dst_spec->dataSize = src_spec->dataSize;
160 memcpy(pdata, src_spec->pData, src->pSpecializationInfo->dataSize);
161 memcpy(maps, src_spec->pMapEntries, src_spec->mapEntryCount * sizeof(VkSpecializationMapEntry));
162 dst->pSpecializationInfo = dst_spec;
163 }
164 return VK_SUCCESS;
165 }
166
167 static VkResult
168 deep_copy_vertex_input_state(struct VkPipelineVertexInputStateCreateInfo *dst,
169 const struct VkPipelineVertexInputStateCreateInfo *src)
170 {
171 int i;
172 VkVertexInputBindingDescription *dst_binding_descriptions;
173 VkVertexInputAttributeDescription *dst_attrib_descriptions;
174 dst->sType = src->sType;
175 dst->pNext = NULL;
176 dst->flags = src->flags;
177 dst->vertexBindingDescriptionCount = src->vertexBindingDescriptionCount;
178
179 dst_binding_descriptions = malloc(src->vertexBindingDescriptionCount * sizeof(VkVertexInputBindingDescription));
180 if (!dst_binding_descriptions)
181 return VK_ERROR_OUT_OF_HOST_MEMORY;
182 for (i = 0; i < dst->vertexBindingDescriptionCount; i++) {
183 memcpy(&dst_binding_descriptions[i], &src->pVertexBindingDescriptions[i], sizeof(VkVertexInputBindingDescription));
184 }
185 dst->pVertexBindingDescriptions = dst_binding_descriptions;
186
187 dst->vertexAttributeDescriptionCount = src->vertexAttributeDescriptionCount;
188
189 dst_attrib_descriptions = malloc(src->vertexAttributeDescriptionCount * sizeof(VkVertexInputAttributeDescription));
190 if (!dst_attrib_descriptions)
191 return VK_ERROR_OUT_OF_HOST_MEMORY;
192
193 for (i = 0; i < dst->vertexAttributeDescriptionCount; i++) {
194 memcpy(&dst_attrib_descriptions[i], &src->pVertexAttributeDescriptions[i], sizeof(VkVertexInputAttributeDescription));
195 }
196 dst->pVertexAttributeDescriptions = dst_attrib_descriptions;
197 return VK_SUCCESS;
198 }
199
200 static VkResult
201 deep_copy_viewport_state(VkPipelineViewportStateCreateInfo *dst,
202 const VkPipelineViewportStateCreateInfo *src)
203 {
204 int i;
205 VkViewport *viewports;
206 VkRect2D *scissors;
207 dst->sType = src->sType;
208 dst->pNext = src->pNext;
209
210 dst->flags = src->flags;
211
212 if (src->pViewports) {
213 viewports = malloc(src->viewportCount * sizeof(VkViewport));
214 for (i = 0; i < src->viewportCount; i++)
215 memcpy(&viewports[i], &src->pViewports[i], sizeof(VkViewport));
216 dst->pViewports = viewports;
217 } else
218 dst->pViewports = NULL;
219 dst->viewportCount = src->viewportCount;
220
221 if (src->pScissors) {
222 scissors = malloc(src->scissorCount * sizeof(VkRect2D));
223 for (i = 0; i < src->scissorCount; i++)
224 memcpy(&scissors[i], &src->pScissors[i], sizeof(VkRect2D));
225 dst->pScissors = scissors;
226 } else
227 dst->pScissors = NULL;
228 dst->scissorCount = src->scissorCount;
229
230 return VK_SUCCESS;
231 }
232
233 static VkResult
234 deep_copy_color_blend_state(VkPipelineColorBlendStateCreateInfo *dst,
235 const VkPipelineColorBlendStateCreateInfo *src)
236 {
237 VkPipelineColorBlendAttachmentState *attachments;
238 dst->sType = src->sType;
239 dst->pNext = src->pNext;
240 dst->flags = src->flags;
241 dst->logicOpEnable = src->logicOpEnable;
242 dst->logicOp = src->logicOp;
243
244 attachments = malloc(src->attachmentCount * sizeof(VkPipelineColorBlendAttachmentState));
245 memcpy(attachments, src->pAttachments, src->attachmentCount * sizeof(VkPipelineColorBlendAttachmentState));
246 dst->attachmentCount = src->attachmentCount;
247 dst->pAttachments = attachments;
248
249 memcpy(&dst->blendConstants, &src->blendConstants, sizeof(float) * 4);
250
251 return VK_SUCCESS;
252 }
253
254 static VkResult
255 deep_copy_dynamic_state(VkPipelineDynamicStateCreateInfo *dst,
256 const VkPipelineDynamicStateCreateInfo *src)
257 {
258 VkDynamicState *dynamic_states;
259 dst->sType = src->sType;
260 dst->pNext = src->pNext;
261 dst->flags = src->flags;
262
263 dynamic_states = malloc(src->dynamicStateCount * sizeof(VkDynamicState));
264 if (!dynamic_states)
265 return VK_ERROR_OUT_OF_HOST_MEMORY;
266
267 memcpy(dynamic_states, src->pDynamicStates, src->dynamicStateCount * sizeof(VkDynamicState));
268 dst->dynamicStateCount = src->dynamicStateCount;
269 dst->pDynamicStates = dynamic_states;
270 return VK_SUCCESS;
271 }
272
273 static VkResult
274 deep_copy_graphics_create_info(VkGraphicsPipelineCreateInfo *dst,
275 const VkGraphicsPipelineCreateInfo *src)
276 {
277 int i;
278 VkResult result;
279 VkPipelineShaderStageCreateInfo *stages;
280 VkPipelineVertexInputStateCreateInfo *vertex_input;
281 VkPipelineInputAssemblyStateCreateInfo *input_assembly;
282 VkPipelineRasterizationStateCreateInfo* raster_state;
283
284 dst->sType = src->sType;
285 dst->pNext = NULL;
286 dst->flags = src->flags;
287 dst->layout = src->layout;
288 dst->renderPass = src->renderPass;
289 dst->subpass = src->subpass;
290 dst->basePipelineHandle = src->basePipelineHandle;
291 dst->basePipelineIndex = src->basePipelineIndex;
292
293 /* pStages */
294 dst->stageCount = src->stageCount;
295 stages = malloc(dst->stageCount * sizeof(VkPipelineShaderStageCreateInfo));
296 for (i = 0 ; i < dst->stageCount; i++) {
297 result = deep_copy_shader_stage(&stages[i], &src->pStages[i]);
298 if (result != VK_SUCCESS)
299 return result;
300 }
301 dst->pStages = stages;
302
303 /* pVertexInputState */
304 vertex_input = malloc(sizeof(VkPipelineVertexInputStateCreateInfo));
305 result = deep_copy_vertex_input_state(vertex_input,
306 src->pVertexInputState);
307 if (result != VK_SUCCESS)
308 return result;
309 dst->pVertexInputState = vertex_input;
310
311 /* pInputAssemblyState */
312 input_assembly = malloc(sizeof(VkPipelineInputAssemblyStateCreateInfo));
313 if (!input_assembly)
314 return VK_ERROR_OUT_OF_HOST_MEMORY;
315 memcpy(input_assembly, src->pInputAssemblyState, sizeof(VkPipelineInputAssemblyStateCreateInfo));
316 dst->pInputAssemblyState = input_assembly;
317
318 /* pTessellationState */
319 if (src->pTessellationState) {
320 VkPipelineTessellationStateCreateInfo *tess_state;
321 tess_state = malloc(sizeof(VkPipelineTessellationStateCreateInfo));
322 if (!tess_state)
323 return VK_ERROR_OUT_OF_HOST_MEMORY;
324 memcpy(tess_state, src->pTessellationState, sizeof(VkPipelineTessellationStateCreateInfo));
325 dst->pTessellationState = tess_state;
326 }
327
328
329 /* pViewportState */
330 if (src->pViewportState) {
331 VkPipelineViewportStateCreateInfo *viewport_state;
332 viewport_state = malloc(sizeof(VkPipelineViewportStateCreateInfo));
333 if (!viewport_state)
334 return VK_ERROR_OUT_OF_HOST_MEMORY;
335 deep_copy_viewport_state(viewport_state, src->pViewportState);
336 dst->pViewportState = viewport_state;
337 } else
338 dst->pViewportState = NULL;
339
340 /* pRasterizationState */
341 raster_state = malloc(sizeof(VkPipelineRasterizationStateCreateInfo));
342 if (!raster_state)
343 return VK_ERROR_OUT_OF_HOST_MEMORY;
344 memcpy(raster_state, src->pRasterizationState, sizeof(VkPipelineRasterizationStateCreateInfo));
345 dst->pRasterizationState = raster_state;
346
347 /* pMultisampleState */
348 if (src->pMultisampleState) {
349 VkPipelineMultisampleStateCreateInfo* ms_state;
350 ms_state = malloc(sizeof(VkPipelineMultisampleStateCreateInfo) + sizeof(VkSampleMask));
351 if (!ms_state)
352 return VK_ERROR_OUT_OF_HOST_MEMORY;
353 /* does samplemask need deep copy? */
354 memcpy(ms_state, src->pMultisampleState, sizeof(VkPipelineMultisampleStateCreateInfo));
355 if (src->pMultisampleState->pSampleMask) {
356 VkSampleMask *sample_mask = (VkSampleMask *)(ms_state + 1);
357 sample_mask[0] = src->pMultisampleState->pSampleMask[0];
358 ms_state->pSampleMask = sample_mask;
359 }
360 dst->pMultisampleState = ms_state;
361 } else
362 dst->pMultisampleState = NULL;
363
364 /* pDepthStencilState */
365 if (src->pDepthStencilState) {
366 VkPipelineDepthStencilStateCreateInfo* ds_state;
367
368 ds_state = malloc(sizeof(VkPipelineDepthStencilStateCreateInfo));
369 if (!ds_state)
370 return VK_ERROR_OUT_OF_HOST_MEMORY;
371 memcpy(ds_state, src->pDepthStencilState, sizeof(VkPipelineDepthStencilStateCreateInfo));
372 dst->pDepthStencilState = ds_state;
373 } else
374 dst->pDepthStencilState = NULL;
375
376 /* pColorBlendState */
377 if (src->pColorBlendState) {
378 VkPipelineColorBlendStateCreateInfo* cb_state;
379
380 cb_state = malloc(sizeof(VkPipelineColorBlendStateCreateInfo));
381 if (!cb_state)
382 return VK_ERROR_OUT_OF_HOST_MEMORY;
383 deep_copy_color_blend_state(cb_state, src->pColorBlendState);
384 dst->pColorBlendState = cb_state;
385 } else
386 dst->pColorBlendState = NULL;
387
388 if (src->pDynamicState) {
389 VkPipelineDynamicStateCreateInfo* dyn_state;
390
391 /* pDynamicState */
392 dyn_state = malloc(sizeof(VkPipelineDynamicStateCreateInfo));
393 if (!dyn_state)
394 return VK_ERROR_OUT_OF_HOST_MEMORY;
395 deep_copy_dynamic_state(dyn_state, src->pDynamicState);
396 dst->pDynamicState = dyn_state;
397 } else
398 dst->pDynamicState = NULL;
399
400 return VK_SUCCESS;
401 }
402
403 static VkResult
404 deep_copy_compute_create_info(VkComputePipelineCreateInfo *dst,
405 const VkComputePipelineCreateInfo *src)
406 {
407 VkResult result;
408 dst->sType = src->sType;
409 dst->pNext = NULL;
410 dst->flags = src->flags;
411 dst->layout = src->layout;
412 dst->basePipelineHandle = src->basePipelineHandle;
413 dst->basePipelineIndex = src->basePipelineIndex;
414
415 result = deep_copy_shader_stage(&dst->stage, &src->stage);
416 if (result != VK_SUCCESS)
417 return result;
418 return VK_SUCCESS;
419 }
420
421 static inline unsigned
422 st_shader_stage_to_ptarget(gl_shader_stage stage)
423 {
424 switch (stage) {
425 case MESA_SHADER_VERTEX:
426 return PIPE_SHADER_VERTEX;
427 case MESA_SHADER_FRAGMENT:
428 return PIPE_SHADER_FRAGMENT;
429 case MESA_SHADER_GEOMETRY:
430 return PIPE_SHADER_GEOMETRY;
431 case MESA_SHADER_TESS_CTRL:
432 return PIPE_SHADER_TESS_CTRL;
433 case MESA_SHADER_TESS_EVAL:
434 return PIPE_SHADER_TESS_EVAL;
435 case MESA_SHADER_COMPUTE:
436 return PIPE_SHADER_COMPUTE;
437 default:
438 break;
439 }
440
441 assert(!"should not be reached");
442 return PIPE_SHADER_VERTEX;
443 }
444
445 static void
446 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
447 {
448 assert(glsl_type_is_vector_or_scalar(type));
449
450 uint32_t comp_size = glsl_type_is_boolean(type)
451 ? 4 : glsl_get_bit_size(type) / 8;
452 unsigned length = glsl_get_vector_elements(type);
453 *size = comp_size * length,
454 *align = comp_size;
455 }
456
457 #define OPT(pass, ...) ({ \
458 bool this_progress = false; \
459 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
460 if (this_progress) \
461 progress = true; \
462 this_progress; \
463 })
464
465 static void
466 val_shader_compile_to_ir(struct val_pipeline *pipeline,
467 struct val_shader_module *module,
468 const char *entrypoint_name,
469 gl_shader_stage stage,
470 const VkSpecializationInfo *spec_info)
471 {
472 nir_shader *nir;
473 const nir_shader_compiler_options *drv_options = pipeline->device->pscreen->get_compiler_options(pipeline->device->pscreen, PIPE_SHADER_IR_NIR, st_shader_stage_to_ptarget(stage));
474 bool progress;
475 uint32_t *spirv = (uint32_t *) module->data;
476 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
477 assert(module->size % 4 == 0);
478
479 uint32_t num_spec_entries = 0;
480 struct nir_spirv_specialization *spec_entries = NULL;
481 if (spec_info && spec_info->mapEntryCount > 0) {
482 num_spec_entries = spec_info->mapEntryCount;
483 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
484 for (uint32_t i = 0; i < num_spec_entries; i++) {
485 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
486 const void *data =
487 spec_info->pData + entry.offset;
488 assert((const void *)(data + entry.size) <=
489 spec_info->pData + spec_info->dataSize);
490
491 spec_entries[i].id = entry.constantID;
492 switch (entry.size) {
493 case 8:
494 spec_entries[i].value.u64 = *(const uint64_t *)data;
495 break;
496 case 4:
497 spec_entries[i].value.u32 = *(const uint32_t *)data;
498 break;
499 case 2:
500 spec_entries[i].value.u16 = *(const uint16_t *)data;
501 break;
502 case 1:
503 spec_entries[i].value.u8 = *(const uint8_t *)data;
504 break;
505 default:
506 assert(!"Invalid spec constant size");
507 break;
508 }
509 }
510 }
511 struct val_device *pdevice = pipeline->device;
512 const struct spirv_to_nir_options spirv_options = {
513 .environment = NIR_SPIRV_VULKAN,
514 .lower_ubo_ssbo_access_to_offsets = true,
515 .caps = {
516 .float64 = (pdevice->pscreen->get_param(pdevice->pscreen, PIPE_CAP_DOUBLES) == 1),
517 .int16 = true,
518 .int64 = (pdevice->pscreen->get_param(pdevice->pscreen, PIPE_CAP_INT64) == 1),
519 .tessellation = true,
520 .image_ms_array = true,
521 .storage_image_ms = true,
522 .geometry_streams = true,
523 .storage_16bit = true,
524 .variable_pointers = true,
525 },
526 .ubo_addr_format = nir_address_format_32bit_index_offset,
527 .ssbo_addr_format = nir_address_format_32bit_index_offset,
528 .phys_ssbo_addr_format = nir_address_format_64bit_global,
529 .push_const_addr_format = nir_address_format_logical,
530 .shared_addr_format = nir_address_format_32bit_offset,
531 .frag_coord_is_sysval = false,
532 };
533
534 nir = spirv_to_nir(spirv, module->size / 4,
535 spec_entries, num_spec_entries,
536 stage, entrypoint_name, &spirv_options, drv_options);
537
538 nir_validate_shader(nir, NULL);
539
540 free(spec_entries);
541
542 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
543 NIR_PASS_V(nir, nir_lower_returns);
544 NIR_PASS_V(nir, nir_inline_functions);
545 NIR_PASS_V(nir, nir_copy_prop);
546 NIR_PASS_V(nir, nir_opt_deref);
547
548 /* Pick off the single entrypoint that we want */
549 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
550 if (!func->is_entrypoint)
551 exec_node_remove(&func->node);
552 }
553 assert(exec_list_length(&nir->functions) == 1);
554
555 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
556 NIR_PASS_V(nir, nir_split_var_copies);
557 NIR_PASS_V(nir, nir_split_per_member_structs);
558
559 NIR_PASS_V(nir, nir_remove_dead_variables,
560 nir_var_shader_in | nir_var_shader_out | nir_var_system_value, NULL);
561
562 if (stage == MESA_SHADER_FRAGMENT)
563 val_lower_input_attachments(nir, false);
564 NIR_PASS_V(nir, nir_lower_system_values);
565 NIR_PASS_V(nir, nir_lower_compute_system_values);
566
567 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
568 nir_remove_dead_variables(nir, nir_var_uniform, NULL);
569
570 val_lower_pipeline_layout(pipeline->device, pipeline->layout, nir);
571
572 NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
573 NIR_PASS_V(nir, nir_split_var_copies);
574 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
575
576 if (nir->info.stage == MESA_SHADER_COMPUTE) {
577 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, nir_var_mem_shared, shared_var_info);
578 NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_shared, nir_address_format_32bit_offset);
579 }
580
581 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_shader_temp, NULL);
582
583 if (nir->info.stage == MESA_SHADER_VERTEX ||
584 nir->info.stage == MESA_SHADER_GEOMETRY) {
585 NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
586 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
587 NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, true);
588 }
589
590 do {
591 progress = false;
592
593 progress |= OPT(nir_lower_flrp, 32|64, true, false);
594 progress |= OPT(nir_split_array_vars, nir_var_function_temp);
595 progress |= OPT(nir_shrink_vec_array_vars, nir_var_function_temp);
596 progress |= OPT(nir_opt_deref);
597 progress |= OPT(nir_lower_vars_to_ssa);
598
599 progress |= nir_copy_prop(nir);
600 progress |= nir_opt_dce(nir);
601 progress |= nir_opt_dead_cf(nir);
602 progress |= nir_opt_cse(nir);
603 progress |= nir_opt_algebraic(nir);
604 progress |= nir_opt_constant_folding(nir);
605 progress |= nir_opt_undef(nir);
606
607 progress |= nir_opt_deref(nir);
608 progress |= nir_lower_alu_to_scalar(nir, NULL, NULL);
609 } while (progress);
610
611 nir_lower_var_copies(nir);
612 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
613
614 nir_validate_shader(nir, NULL);
615 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
616
617 if (nir->info.stage != MESA_SHADER_VERTEX)
618 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs, nir->info.stage);
619 else {
620 nir->num_inputs = util_last_bit64(nir->info.inputs_read);
621 nir_foreach_shader_in_variable(var, nir) {
622 var->data.driver_location = var->data.location - VERT_ATTRIB_GENERIC0;
623 }
624 }
625 nir_assign_io_var_locations(nir, nir_var_shader_out, &nir->num_outputs,
626 nir->info.stage);
627 pipeline->pipeline_nir[stage] = nir;
628 }
629
630 static void fill_shader_prog(struct pipe_shader_state *state, gl_shader_stage stage, struct val_pipeline *pipeline)
631 {
632 state->type = PIPE_SHADER_IR_NIR;
633 state->ir.nir = pipeline->pipeline_nir[stage];
634 }
635
636 static void
637 merge_tess_info(struct shader_info *tes_info,
638 const struct shader_info *tcs_info)
639 {
640 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
641 *
642 * "PointMode. Controls generation of points rather than triangles
643 * or lines. This functionality defaults to disabled, and is
644 * enabled if either shader stage includes the execution mode.
645 *
646 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
647 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
648 * and OutputVertices, it says:
649 *
650 * "One mode must be set in at least one of the tessellation
651 * shader stages."
652 *
653 * So, the fields can be set in either the TCS or TES, but they must
654 * agree if set in both. Our backend looks at TES, so bitwise-or in
655 * the values from the TCS.
656 */
657 assert(tcs_info->tess.tcs_vertices_out == 0 ||
658 tes_info->tess.tcs_vertices_out == 0 ||
659 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
660 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
661
662 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
663 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
664 tcs_info->tess.spacing == tes_info->tess.spacing);
665 tes_info->tess.spacing |= tcs_info->tess.spacing;
666
667 assert(tcs_info->tess.primitive_mode == 0 ||
668 tes_info->tess.primitive_mode == 0 ||
669 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
670 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
671 tes_info->tess.ccw |= tcs_info->tess.ccw;
672 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
673 }
674
675 static gl_shader_stage
676 val_shader_stage(VkShaderStageFlagBits stage)
677 {
678 switch (stage) {
679 case VK_SHADER_STAGE_VERTEX_BIT:
680 return MESA_SHADER_VERTEX;
681 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
682 return MESA_SHADER_TESS_CTRL;
683 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
684 return MESA_SHADER_TESS_EVAL;
685 case VK_SHADER_STAGE_GEOMETRY_BIT:
686 return MESA_SHADER_GEOMETRY;
687 case VK_SHADER_STAGE_FRAGMENT_BIT:
688 return MESA_SHADER_FRAGMENT;
689 case VK_SHADER_STAGE_COMPUTE_BIT:
690 return MESA_SHADER_COMPUTE;
691 default:
692 unreachable("invalid VkShaderStageFlagBits");
693 return MESA_SHADER_NONE;
694 }
695 }
696
697 static VkResult
698 val_pipeline_compile(struct val_pipeline *pipeline,
699 gl_shader_stage stage)
700 {
701 struct val_device *device = pipeline->device;
702 device->physical_device->pscreen->finalize_nir(device->physical_device->pscreen, pipeline->pipeline_nir[stage], true);
703 if (stage == MESA_SHADER_COMPUTE) {
704 struct pipe_compute_state shstate = {};
705 shstate.prog = (void *)pipeline->pipeline_nir[MESA_SHADER_COMPUTE];
706 shstate.ir_type = PIPE_SHADER_IR_NIR;
707 shstate.req_local_mem = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.cs.shared_size;
708 pipeline->shader_cso[PIPE_SHADER_COMPUTE] = device->queue.ctx->create_compute_state(device->queue.ctx, &shstate);
709 } else {
710 struct pipe_shader_state shstate = {};
711 fill_shader_prog(&shstate, stage, pipeline);
712 switch (stage) {
713 case MESA_SHADER_FRAGMENT:
714 pipeline->shader_cso[PIPE_SHADER_FRAGMENT] = device->queue.ctx->create_fs_state(device->queue.ctx, &shstate);
715 break;
716 case MESA_SHADER_VERTEX:
717 pipeline->shader_cso[PIPE_SHADER_VERTEX] = device->queue.ctx->create_vs_state(device->queue.ctx, &shstate);
718 break;
719 case MESA_SHADER_GEOMETRY:
720 pipeline->shader_cso[PIPE_SHADER_GEOMETRY] = device->queue.ctx->create_gs_state(device->queue.ctx, &shstate);
721 break;
722 case MESA_SHADER_TESS_CTRL:
723 pipeline->shader_cso[PIPE_SHADER_TESS_CTRL] = device->queue.ctx->create_tcs_state(device->queue.ctx, &shstate);
724 break;
725 case MESA_SHADER_TESS_EVAL:
726 pipeline->shader_cso[PIPE_SHADER_TESS_EVAL] = device->queue.ctx->create_tes_state(device->queue.ctx, &shstate);
727 break;
728 default:
729 unreachable("illegal shader");
730 break;
731 }
732 }
733 return VK_SUCCESS;
734 }
735
736 static VkResult
737 val_graphics_pipeline_init(struct val_pipeline *pipeline,
738 struct val_device *device,
739 struct val_pipeline_cache *cache,
740 const VkGraphicsPipelineCreateInfo *pCreateInfo,
741 const VkAllocationCallbacks *alloc)
742 {
743 if (alloc == NULL)
744 alloc = &device->alloc;
745 pipeline->device = device;
746 pipeline->layout = val_pipeline_layout_from_handle(pCreateInfo->layout);
747 pipeline->force_min_sample = false;
748
749 /* recreate createinfo */
750 deep_copy_graphics_create_info(&pipeline->graphics_create_info, pCreateInfo);
751 pipeline->is_compute_pipeline = false;
752
753 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
754 VAL_FROM_HANDLE(val_shader_module, module,
755 pCreateInfo->pStages[i].module);
756 gl_shader_stage stage = val_shader_stage(pCreateInfo->pStages[i].stage);
757 val_shader_compile_to_ir(pipeline, module,
758 pCreateInfo->pStages[i].pName,
759 stage,
760 pCreateInfo->pStages[i].pSpecializationInfo);
761 }
762
763 if (pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]) {
764 if (pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.fs.uses_sample_qualifier ||
765 pipeline->pipeline_nir[MESA_SHADER_FRAGMENT]->info.system_values_read & (SYSTEM_BIT_SAMPLE_ID |
766 SYSTEM_BIT_SAMPLE_POS))
767 pipeline->force_min_sample = true;
768 }
769 if (pipeline->pipeline_nir[MESA_SHADER_TESS_CTRL]) {
770 nir_lower_patch_vertices(pipeline->pipeline_nir[MESA_SHADER_TESS_EVAL], pipeline->pipeline_nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
771 merge_tess_info(&pipeline->pipeline_nir[MESA_SHADER_TESS_EVAL]->info, &pipeline->pipeline_nir[MESA_SHADER_TESS_CTRL]->info);
772 pipeline->pipeline_nir[MESA_SHADER_TESS_EVAL]->info.tess.ccw = !pipeline->pipeline_nir[MESA_SHADER_TESS_EVAL]->info.tess.ccw;
773 }
774
775
776 bool has_fragment_shader = false;
777 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
778 gl_shader_stage stage = val_shader_stage(pCreateInfo->pStages[i].stage);
779 val_pipeline_compile(pipeline, stage);
780 if (stage == MESA_SHADER_FRAGMENT)
781 has_fragment_shader = true;
782 }
783
784 if (has_fragment_shader == false) {
785 /* create a dummy fragment shader for this pipeline. */
786 nir_builder b;
787
788 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
789 b.shader->info.name = ralloc_strdup(b.shader, "dummy_frag");
790
791 pipeline->pipeline_nir[MESA_SHADER_FRAGMENT] = b.shader;
792 struct pipe_shader_state shstate = {};
793 shstate.type = PIPE_SHADER_IR_NIR;
794 shstate.ir.nir = pipeline->pipeline_nir[MESA_SHADER_FRAGMENT];
795 pipeline->shader_cso[PIPE_SHADER_FRAGMENT] = device->queue.ctx->create_fs_state(device->queue.ctx, &shstate);
796 }
797 return VK_SUCCESS;
798 }
799
800 static VkResult
801 val_graphics_pipeline_create(
802 VkDevice _device,
803 VkPipelineCache _cache,
804 const VkGraphicsPipelineCreateInfo *pCreateInfo,
805 const VkAllocationCallbacks *pAllocator,
806 VkPipeline *pPipeline)
807 {
808 VAL_FROM_HANDLE(val_device, device, _device);
809 VAL_FROM_HANDLE(val_pipeline_cache, cache, _cache);
810 struct val_pipeline *pipeline;
811 VkResult result;
812
813 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
814
815 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
816 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
817 if (pipeline == NULL)
818 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
819
820 vk_object_base_init(&device->vk, &pipeline->base,
821 VK_OBJECT_TYPE_PIPELINE);
822 result = val_graphics_pipeline_init(pipeline, device, cache, pCreateInfo,
823 pAllocator);
824 if (result != VK_SUCCESS) {
825 vk_free2(&device->alloc, pAllocator, pipeline);
826 return result;
827 }
828
829 *pPipeline = val_pipeline_to_handle(pipeline);
830
831 return VK_SUCCESS;
832 }
833
834 VkResult val_CreateGraphicsPipelines(
835 VkDevice _device,
836 VkPipelineCache pipelineCache,
837 uint32_t count,
838 const VkGraphicsPipelineCreateInfo* pCreateInfos,
839 const VkAllocationCallbacks* pAllocator,
840 VkPipeline* pPipelines)
841 {
842 VkResult result = VK_SUCCESS;
843 unsigned i = 0;
844
845 for (; i < count; i++) {
846 VkResult r;
847 r = val_graphics_pipeline_create(_device,
848 pipelineCache,
849 &pCreateInfos[i],
850 pAllocator, &pPipelines[i]);
851 if (r != VK_SUCCESS) {
852 result = r;
853 pPipelines[i] = VK_NULL_HANDLE;
854 }
855 }
856
857 return result;
858 }
859
860 static VkResult
861 val_compute_pipeline_init(struct val_pipeline *pipeline,
862 struct val_device *device,
863 struct val_pipeline_cache *cache,
864 const VkComputePipelineCreateInfo *pCreateInfo,
865 const VkAllocationCallbacks *alloc)
866 {
867 VAL_FROM_HANDLE(val_shader_module, module,
868 pCreateInfo->stage.module);
869 if (alloc == NULL)
870 alloc = &device->alloc;
871 pipeline->device = device;
872 pipeline->layout = val_pipeline_layout_from_handle(pCreateInfo->layout);
873 pipeline->force_min_sample = false;
874
875 deep_copy_compute_create_info(&pipeline->compute_create_info, pCreateInfo);
876 pipeline->is_compute_pipeline = true;
877
878 val_shader_compile_to_ir(pipeline, module,
879 pCreateInfo->stage.pName,
880 MESA_SHADER_COMPUTE,
881 pCreateInfo->stage.pSpecializationInfo);
882 val_pipeline_compile(pipeline, MESA_SHADER_COMPUTE);
883 return VK_SUCCESS;
884 }
885
886 static VkResult
887 val_compute_pipeline_create(
888 VkDevice _device,
889 VkPipelineCache _cache,
890 const VkComputePipelineCreateInfo *pCreateInfo,
891 const VkAllocationCallbacks *pAllocator,
892 VkPipeline *pPipeline)
893 {
894 VAL_FROM_HANDLE(val_device, device, _device);
895 VAL_FROM_HANDLE(val_pipeline_cache, cache, _cache);
896 struct val_pipeline *pipeline;
897 VkResult result;
898
899 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO);
900
901 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
902 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
903 if (pipeline == NULL)
904 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
905
906 vk_object_base_init(&device->vk, &pipeline->base,
907 VK_OBJECT_TYPE_PIPELINE);
908 result = val_compute_pipeline_init(pipeline, device, cache, pCreateInfo,
909 pAllocator);
910 if (result != VK_SUCCESS) {
911 vk_free2(&device->alloc, pAllocator, pipeline);
912 return result;
913 }
914
915 *pPipeline = val_pipeline_to_handle(pipeline);
916
917 return VK_SUCCESS;
918 }
919
920 VkResult val_CreateComputePipelines(
921 VkDevice _device,
922 VkPipelineCache pipelineCache,
923 uint32_t count,
924 const VkComputePipelineCreateInfo* pCreateInfos,
925 const VkAllocationCallbacks* pAllocator,
926 VkPipeline* pPipelines)
927 {
928 VkResult result = VK_SUCCESS;
929 unsigned i = 0;
930
931 for (; i < count; i++) {
932 VkResult r;
933 r = val_compute_pipeline_create(_device,
934 pipelineCache,
935 &pCreateInfos[i],
936 pAllocator, &pPipelines[i]);
937 if (r != VK_SUCCESS) {
938 result = r;
939 pPipelines[i] = VK_NULL_HANDLE;
940 }
941 }
942
943 return result;
944 }