src/gallium/include/pipe/p_defines.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef PIPE_DEFINES_H
  29 #define PIPE_DEFINES_H
  30
  31 #include "p_compiler.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /**
  38  * Gallium error codes.
  39  *
  40  * - A zero value always means success.
  41  * - A negative value always means failure.
  42  * - The meaning of a positive value is function dependent.
  43  */
  44 enum pipe_error
  45 {
  46    PIPE_OK = 0,
  47    PIPE_ERROR = -1,    /**< Generic error */
  48    PIPE_ERROR_BAD_INPUT = -2,
  49    PIPE_ERROR_OUT_OF_MEMORY = -3,
  50    PIPE_ERROR_RETRY = -4
  51    /* TODO */
  52 };
  53
  54 enum pipe_blendfactor {
  55    PIPE_BLENDFACTOR_ONE = 1,
  56    PIPE_BLENDFACTOR_SRC_COLOR,
  57    PIPE_BLENDFACTOR_SRC_ALPHA,
  58    PIPE_BLENDFACTOR_DST_ALPHA,
  59    PIPE_BLENDFACTOR_DST_COLOR,
  60    PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE,
  61    PIPE_BLENDFACTOR_CONST_COLOR,
  62    PIPE_BLENDFACTOR_CONST_ALPHA,
  63    PIPE_BLENDFACTOR_SRC1_COLOR,
  64    PIPE_BLENDFACTOR_SRC1_ALPHA,
  65
  66    PIPE_BLENDFACTOR_ZERO = 0x11,
  67    PIPE_BLENDFACTOR_INV_SRC_COLOR,
  68    PIPE_BLENDFACTOR_INV_SRC_ALPHA,
  69    PIPE_BLENDFACTOR_INV_DST_ALPHA,
  70    PIPE_BLENDFACTOR_INV_DST_COLOR,
  71
  72    PIPE_BLENDFACTOR_INV_CONST_COLOR = 0x17,
  73    PIPE_BLENDFACTOR_INV_CONST_ALPHA,
  74    PIPE_BLENDFACTOR_INV_SRC1_COLOR,
  75    PIPE_BLENDFACTOR_INV_SRC1_ALPHA,
  76 };
  77
  78 enum pipe_blend_func {
  79    PIPE_BLEND_ADD,
  80    PIPE_BLEND_SUBTRACT,
  81    PIPE_BLEND_REVERSE_SUBTRACT,
  82    PIPE_BLEND_MIN,
  83    PIPE_BLEND_MAX,
  84 };
  85
  86 enum pipe_logicop {
  87    PIPE_LOGICOP_CLEAR,
  88    PIPE_LOGICOP_NOR,
  89    PIPE_LOGICOP_AND_INVERTED,
  90    PIPE_LOGICOP_COPY_INVERTED,
  91    PIPE_LOGICOP_AND_REVERSE,
  92    PIPE_LOGICOP_INVERT,
  93    PIPE_LOGICOP_XOR,
  94    PIPE_LOGICOP_NAND,
  95    PIPE_LOGICOP_AND,
  96    PIPE_LOGICOP_EQUIV,
  97    PIPE_LOGICOP_NOOP,
  98    PIPE_LOGICOP_OR_INVERTED,
  99    PIPE_LOGICOP_COPY,
 100    PIPE_LOGICOP_OR_REVERSE,
 101    PIPE_LOGICOP_OR,
 102    PIPE_LOGICOP_SET,
 103 };
 104
 105 #define PIPE_MASK_R  0x1
 106 #define PIPE_MASK_G  0x2
 107 #define PIPE_MASK_B  0x4
 108 #define PIPE_MASK_A  0x8
 109 #define PIPE_MASK_RGBA 0xf
 110 #define PIPE_MASK_Z  0x10
 111 #define PIPE_MASK_S  0x20
 112 #define PIPE_MASK_ZS 0x30
 113 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
 114
 115
 116 /**
 117  * Inequality functions.  Used for depth test, stencil compare, alpha
 118  * test, shadow compare, etc.
 119  */
 120 enum pipe_compare_func {
 121    PIPE_FUNC_NEVER,
 122    PIPE_FUNC_LESS,
 123    PIPE_FUNC_EQUAL,
 124    PIPE_FUNC_LEQUAL,
 125    PIPE_FUNC_GREATER,
 126    PIPE_FUNC_NOTEQUAL,
 127    PIPE_FUNC_GEQUAL,
 128    PIPE_FUNC_ALWAYS,
 129 };
 130
 131 /** Polygon fill mode */
 132 enum {
 133    PIPE_POLYGON_MODE_FILL,
 134    PIPE_POLYGON_MODE_LINE,
 135    PIPE_POLYGON_MODE_POINT,
 136    PIPE_POLYGON_MODE_FILL_RECTANGLE,
 137 };
 138
 139 /** Polygon face specification, eg for culling */
 140 #define PIPE_FACE_NONE           0
 141 #define PIPE_FACE_FRONT          1
 142 #define PIPE_FACE_BACK           2
 143 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
 144
 145 /** Stencil ops */
 146 enum pipe_stencil_op {
 147    PIPE_STENCIL_OP_KEEP,
 148    PIPE_STENCIL_OP_ZERO,
 149    PIPE_STENCIL_OP_REPLACE,
 150    PIPE_STENCIL_OP_INCR,
 151    PIPE_STENCIL_OP_DECR,
 152    PIPE_STENCIL_OP_INCR_WRAP,
 153    PIPE_STENCIL_OP_DECR_WRAP,
 154    PIPE_STENCIL_OP_INVERT,
 155 };
 156
 157 /** Texture types.
 158  * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D
 159  */
 160 enum pipe_texture_target
 161 {
 162    PIPE_BUFFER,
 163    PIPE_TEXTURE_1D,
 164    PIPE_TEXTURE_2D,
 165    PIPE_TEXTURE_3D,
 166    PIPE_TEXTURE_CUBE,
 167    PIPE_TEXTURE_RECT,
 168    PIPE_TEXTURE_1D_ARRAY,
 169    PIPE_TEXTURE_2D_ARRAY,
 170    PIPE_TEXTURE_CUBE_ARRAY,
 171    PIPE_MAX_TEXTURE_TYPES,
 172 };
 173
 174 enum pipe_tex_face {
 175    PIPE_TEX_FACE_POS_X,
 176    PIPE_TEX_FACE_NEG_X,
 177    PIPE_TEX_FACE_POS_Y,
 178    PIPE_TEX_FACE_NEG_Y,
 179    PIPE_TEX_FACE_POS_Z,
 180    PIPE_TEX_FACE_NEG_Z,
 181    PIPE_TEX_FACE_MAX,
 182 };
 183
 184 enum pipe_tex_wrap {
 185    PIPE_TEX_WRAP_REPEAT,
 186    PIPE_TEX_WRAP_CLAMP,
 187    PIPE_TEX_WRAP_CLAMP_TO_EDGE,
 188    PIPE_TEX_WRAP_CLAMP_TO_BORDER,
 189    PIPE_TEX_WRAP_MIRROR_REPEAT,
 190    PIPE_TEX_WRAP_MIRROR_CLAMP,
 191    PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE,
 192    PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER,
 193 };
 194
 195 /** Between mipmaps, ie mipfilter */
 196 enum pipe_tex_mipfilter {
 197    PIPE_TEX_MIPFILTER_NEAREST,
 198    PIPE_TEX_MIPFILTER_LINEAR,
 199    PIPE_TEX_MIPFILTER_NONE,
 200 };
 201
 202 /** Within a mipmap, ie min/mag filter */
 203 enum pipe_tex_filter {
 204    PIPE_TEX_FILTER_NEAREST,
 205    PIPE_TEX_FILTER_LINEAR,
 206 };
 207
 208 enum pipe_tex_compare {
 209    PIPE_TEX_COMPARE_NONE,
 210    PIPE_TEX_COMPARE_R_TO_TEXTURE,
 211 };
 212
 213 /**
 214  * Clear buffer bits
 215  */
 216 #define PIPE_CLEAR_DEPTH        (1 << 0)
 217 #define PIPE_CLEAR_STENCIL      (1 << 1)
 218 #define PIPE_CLEAR_COLOR0       (1 << 2)
 219 #define PIPE_CLEAR_COLOR1       (1 << 3)
 220 #define PIPE_CLEAR_COLOR2       (1 << 4)
 221 #define PIPE_CLEAR_COLOR3       (1 << 5)
 222 #define PIPE_CLEAR_COLOR4       (1 << 6)
 223 #define PIPE_CLEAR_COLOR5       (1 << 7)
 224 #define PIPE_CLEAR_COLOR6       (1 << 8)
 225 #define PIPE_CLEAR_COLOR7       (1 << 9)
 226 /** Combined flags */
 227 /** All color buffers currently bound */
 228 #define PIPE_CLEAR_COLOR        (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
 229                                  PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
 230                                  PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
 231                                  PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
 232 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
 233
 234 /**
 235  * Transfer object usage flags
 236  */
 237 enum pipe_transfer_usage
 238 {
 239    /**
 240     * Resource contents read back (or accessed directly) at transfer
 241     * create time.
 242     */
 243    PIPE_TRANSFER_READ = (1 << 0),
 244
 245    /**
 246     * Resource contents will be written back at transfer_unmap
 247     * time (or modified as a result of being accessed directly).
 248     */
 249    PIPE_TRANSFER_WRITE = (1 << 1),
 250
 251    /**
 252     * Read/modify/write
 253     */
 254    PIPE_TRANSFER_READ_WRITE = PIPE_TRANSFER_READ | PIPE_TRANSFER_WRITE,
 255
 256    /**
 257     * The transfer should map the texture storage directly. The driver may
 258     * return NULL if that isn't possible, and the state tracker needs to cope
 259     * with that and use an alternative path without this flag.
 260     *
 261     * E.g. the state tracker could have a simpler path which maps textures and
 262     * does read/modify/write cycles on them directly, and a more complicated
 263     * path which uses minimal read and write transfers.
 264     */
 265    PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2),
 266
 267    /**
 268     * Discards the memory within the mapped region.
 269     *
 270     * It should not be used with PIPE_TRANSFER_READ.
 271     *
 272     * See also:
 273     * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
 274     */
 275    PIPE_TRANSFER_DISCARD_RANGE = (1 << 8),
 276
 277    /**
 278     * Fail if the resource cannot be mapped immediately.
 279     *
 280     * See also:
 281     * - Direct3D's D3DLOCK_DONOTWAIT flag.
 282     * - Mesa's MESA_MAP_NOWAIT_BIT flag.
 283     * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
 284     */
 285    PIPE_TRANSFER_DONTBLOCK = (1 << 9),
 286
 287    /**
 288     * Do not attempt to synchronize pending operations on the resource when mapping.
 289     *
 290     * It should not be used with PIPE_TRANSFER_READ.
 291     *
 292     * See also:
 293     * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag.
 294     * - Direct3D's D3DLOCK_NOOVERWRITE flag.
 295     * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
 296     */
 297    PIPE_TRANSFER_UNSYNCHRONIZED = (1 << 10),
 298
 299    /**
 300     * Written ranges will be notified later with
 301     * pipe_context::transfer_flush_region.
 302     *
 303     * It should not be used with PIPE_TRANSFER_READ.
 304     *
 305     * See also:
 306     * - pipe_context::transfer_flush_region
 307     * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
 308     */
 309    PIPE_TRANSFER_FLUSH_EXPLICIT = (1 << 11),
 310
 311    /**
 312     * Discards all memory backing the resource.
 313     *
 314     * It should not be used with PIPE_TRANSFER_READ.
 315     *
 316     * This is equivalent to:
 317     * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT
 318     * - BufferData(NULL) on a GL buffer
 319     * - Direct3D's D3DLOCK_DISCARD flag.
 320     * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag.
 321     * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
 322     * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
 323     */
 324    PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE = (1 << 12),
 325
 326    /**
 327     * Allows the resource to be used for rendering while mapped.
 328     *
 329     * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
 330     * the resource.
 331     *
 332     * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
 333     * must be called to ensure the device can see what the CPU has written.
 334     */
 335    PIPE_TRANSFER_PERSISTENT = (1 << 13),
 336
 337    /**
 338     * If PERSISTENT is set, this ensures any writes done by the device are
 339     * immediately visible to the CPU and vice versa.
 340     *
 341     * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
 342     * the resource.
 343     */
 344    PIPE_TRANSFER_COHERENT = (1 << 14)
 345 };
 346
 347 /**
 348  * Flags for the flush function.
 349  */
 350 enum pipe_flush_flags
 351 {
 352    PIPE_FLUSH_END_OF_FRAME = (1 << 0),
 353    PIPE_FLUSH_DEFERRED = (1 << 1),
 354    PIPE_FLUSH_FENCE_FD = (1 << 2),
 355    PIPE_FLUSH_ASYNC = (1 << 3),
 356    PIPE_FLUSH_HINT_FINISH = (1 << 4),
 357    PIPE_FLUSH_TOP_OF_PIPE = (1 << 5),
 358    PIPE_FLUSH_BOTTOM_OF_PIPE = (1 << 6),
 359 };
 360
 361 /**
 362  * Flags for pipe_context::dump_debug_state.
 363  */
 364 #define PIPE_DUMP_DEVICE_STATUS_REGISTERS    (1 << 0)
 365
 366 /**
 367  * Create a compute-only context. Use in pipe_screen::context_create.
 368  * This disables draw, blit, and clear*, render_condition, and other graphics
 369  * functions. Interop with other graphics contexts is still allowed.
 370  * This allows scheduling jobs on a compute-only hardware command queue that
 371  * can run in parallel with graphics without stalling it.
 372  */
 373 #define PIPE_CONTEXT_COMPUTE_ONLY      (1 << 0)
 374
 375 /**
 376  * Gather debug information and expect that pipe_context::dump_debug_state
 377  * will be called. Use in pipe_screen::context_create.
 378  */
 379 #define PIPE_CONTEXT_DEBUG             (1 << 1)
 380
 381 /**
 382  * Whether out-of-bounds shader loads must return zero and out-of-bounds
 383  * shader stores must be dropped.
 384  */
 385 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2)
 386
 387 /**
 388  * Prefer threaded pipe_context. It also implies that video codec functions
 389  * will not be used. (they will be either no-ops or NULL when threading is
 390  * enabled)
 391  */
 392 #define PIPE_CONTEXT_PREFER_THREADED   (1 << 3)
 393
 394 /**
 395  * Create a high priority context.
 396  */
 397 #define PIPE_CONTEXT_HIGH_PRIORITY     (1 << 4)
 398
 399 /**
 400  * Create a low priority context.
 401  */
 402 #define PIPE_CONTEXT_LOW_PRIORITY      (1 << 5)
 403
 404 /**
 405  * Flags for pipe_context::memory_barrier.
 406  */
 407 #define PIPE_BARRIER_MAPPED_BUFFER     (1 << 0)
 408 #define PIPE_BARRIER_SHADER_BUFFER     (1 << 1)
 409 #define PIPE_BARRIER_QUERY_BUFFER      (1 << 2)
 410 #define PIPE_BARRIER_VERTEX_BUFFER     (1 << 3)
 411 #define PIPE_BARRIER_INDEX_BUFFER      (1 << 4)
 412 #define PIPE_BARRIER_CONSTANT_BUFFER   (1 << 5)
 413 #define PIPE_BARRIER_INDIRECT_BUFFER   (1 << 6)
 414 #define PIPE_BARRIER_TEXTURE           (1 << 7)
 415 #define PIPE_BARRIER_IMAGE             (1 << 8)
 416 #define PIPE_BARRIER_FRAMEBUFFER       (1 << 9)
 417 #define PIPE_BARRIER_STREAMOUT_BUFFER  (1 << 10)
 418 #define PIPE_BARRIER_GLOBAL_BUFFER     (1 << 11)
 419 #define PIPE_BARRIER_ALL               ((1 << 12) - 1)
 420
 421 /**
 422  * Flags for pipe_context::texture_barrier.
 423  */
 424 #define PIPE_TEXTURE_BARRIER_SAMPLER      (1 << 0)
 425 #define PIPE_TEXTURE_BARRIER_FRAMEBUFFER  (1 << 1)
 426
 427 /**
 428  * Resource binding flags -- state tracker must specify in advance all
 429  * the ways a resource might be used.
 430  */
 431 #define PIPE_BIND_DEPTH_STENCIL        (1 << 0) /* create_surface */
 432 #define PIPE_BIND_RENDER_TARGET        (1 << 1) /* create_surface */
 433 #define PIPE_BIND_BLENDABLE            (1 << 2) /* create_surface */
 434 #define PIPE_BIND_SAMPLER_VIEW         (1 << 3) /* create_sampler_view */
 435 #define PIPE_BIND_VERTEX_BUFFER        (1 << 4) /* set_vertex_buffers */
 436 #define PIPE_BIND_INDEX_BUFFER         (1 << 5) /* draw_elements */
 437 #define PIPE_BIND_CONSTANT_BUFFER      (1 << 6) /* set_constant_buffer */
 438 #define PIPE_BIND_DISPLAY_TARGET       (1 << 7) /* flush_front_buffer */
 439 /* gap */
 440 #define PIPE_BIND_STREAM_OUTPUT        (1 << 10) /* set_stream_output_buffers */
 441 #define PIPE_BIND_CURSOR               (1 << 11) /* mouse cursor */
 442 #define PIPE_BIND_CUSTOM               (1 << 12) /* state-tracker/winsys usages */
 443 #define PIPE_BIND_GLOBAL               (1 << 13) /* set_global_binding */
 444 #define PIPE_BIND_SHADER_BUFFER        (1 << 14) /* set_shader_buffers */
 445 #define PIPE_BIND_SHADER_IMAGE         (1 << 15) /* set_shader_images */
 446 #define PIPE_BIND_COMPUTE_RESOURCE     (1 << 16) /* set_compute_resources */
 447 #define PIPE_BIND_COMMAND_ARGS_BUFFER  (1 << 17) /* pipe_draw_info.indirect */
 448 #define PIPE_BIND_QUERY_BUFFER         (1 << 18) /* get_query_result_resource */
 449
 450 /**
 451  * The first two flags above were previously part of the amorphous
 452  * TEXTURE_USAGE, most of which are now descriptions of the ways a
 453  * particular texture can be bound to the gallium pipeline.  The two flags
 454  * below do not fit within that and probably need to be migrated to some
 455  * other place.
 456  *
 457  * It seems like scanout is used by the Xorg state tracker to ask for
 458  * a texture suitable for actual scanout (hence the name), which
 459  * implies extra layout constraints on some hardware.  It may also
 460  * have some special meaning regarding mouse cursor images.
 461  *
 462  * The shared flag is quite underspecified, but certainly isn't a
 463  * binding flag - it seems more like a message to the winsys to create
 464  * a shareable allocation.
 465  *
 466  * The third flag has been added to be able to force textures to be created
 467  * in linear mode (no tiling).
 468  */
 469 #define PIPE_BIND_SCANOUT     (1 << 19) /*  */
 470 #define PIPE_BIND_SHARED      (1 << 20) /* get_texture_handle ??? */
 471 #define PIPE_BIND_LINEAR      (1 << 21)
 472
 473
 474 /**
 475  * Flags for the driver about resource behaviour:
 476  */
 477 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
 478 #define PIPE_RESOURCE_FLAG_MAP_COHERENT   (1 << 1)
 479 #define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2)
 480 #define PIPE_RESOURCE_FLAG_SPARSE                (1 << 3)
 481 #define PIPE_RESOURCE_FLAG_DRV_PRIV    (1 << 16) /* driver/winsys private */
 482 #define PIPE_RESOURCE_FLAG_ST_PRIV     (1 << 24) /* state-tracker/winsys private */
 483
 484 /**
 485  * Hint about the expected lifecycle of a resource.
 486  * Sorted according to GPU vs CPU access.
 487  */
 488 enum pipe_resource_usage {
 489    PIPE_USAGE_DEFAULT,        /* fast GPU access */
 490    PIPE_USAGE_IMMUTABLE,      /* fast GPU access, immutable */
 491    PIPE_USAGE_DYNAMIC,        /* uploaded data is used multiple times */
 492    PIPE_USAGE_STREAM,         /* uploaded data is used once */
 493    PIPE_USAGE_STAGING,        /* fast CPU access */
 494 };
 495
 496 /**
 497  * Shaders
 498  */
 499 enum pipe_shader_type {
 500    PIPE_SHADER_VERTEX,
 501    PIPE_SHADER_FRAGMENT,
 502    PIPE_SHADER_GEOMETRY,
 503    PIPE_SHADER_TESS_CTRL,
 504    PIPE_SHADER_TESS_EVAL,
 505    PIPE_SHADER_COMPUTE,
 506    PIPE_SHADER_TYPES,
 507 };
 508
 509 /**
 510  * Primitive types:
 511  */
 512 enum pipe_prim_type {
 513    PIPE_PRIM_POINTS,
 514    PIPE_PRIM_LINES,
 515    PIPE_PRIM_LINE_LOOP,
 516    PIPE_PRIM_LINE_STRIP,
 517    PIPE_PRIM_TRIANGLES,
 518    PIPE_PRIM_TRIANGLE_STRIP,
 519    PIPE_PRIM_TRIANGLE_FAN,
 520    PIPE_PRIM_QUADS,
 521    PIPE_PRIM_QUAD_STRIP,
 522    PIPE_PRIM_POLYGON,
 523    PIPE_PRIM_LINES_ADJACENCY,
 524    PIPE_PRIM_LINE_STRIP_ADJACENCY,
 525    PIPE_PRIM_TRIANGLES_ADJACENCY,
 526    PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY,
 527    PIPE_PRIM_PATCHES,
 528    PIPE_PRIM_MAX,
 529 };
 530
 531 /**
 532  * Tessellator spacing types
 533  */
 534 enum pipe_tess_spacing {
 535    PIPE_TESS_SPACING_FRACTIONAL_ODD,
 536    PIPE_TESS_SPACING_FRACTIONAL_EVEN,
 537    PIPE_TESS_SPACING_EQUAL,
 538 };
 539
 540 /**
 541  * Query object types
 542  */
 543 enum pipe_query_type {
 544    PIPE_QUERY_OCCLUSION_COUNTER,
 545    PIPE_QUERY_OCCLUSION_PREDICATE,
 546    PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE,
 547    PIPE_QUERY_TIMESTAMP,
 548    PIPE_QUERY_TIMESTAMP_DISJOINT,
 549    PIPE_QUERY_TIME_ELAPSED,
 550    PIPE_QUERY_PRIMITIVES_GENERATED,
 551    PIPE_QUERY_PRIMITIVES_EMITTED,
 552    PIPE_QUERY_SO_STATISTICS,
 553    PIPE_QUERY_SO_OVERFLOW_PREDICATE,
 554    PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE,
 555    PIPE_QUERY_GPU_FINISHED,
 556    PIPE_QUERY_PIPELINE_STATISTICS,
 557    PIPE_QUERY_TYPES,
 558    /* start of driver queries, see pipe_screen::get_driver_query_info */
 559    PIPE_QUERY_DRIVER_SPECIFIC = 256,
 560 };
 561
 562 /**
 563  * Conditional rendering modes
 564  */
 565 enum pipe_render_cond_flag {
 566    PIPE_RENDER_COND_WAIT,
 567    PIPE_RENDER_COND_NO_WAIT,
 568    PIPE_RENDER_COND_BY_REGION_WAIT,
 569    PIPE_RENDER_COND_BY_REGION_NO_WAIT,
 570 };
 571
 572 /**
 573  * Point sprite coord modes
 574  */
 575 enum pipe_sprite_coord_mode {
 576    PIPE_SPRITE_COORD_UPPER_LEFT,
 577    PIPE_SPRITE_COORD_LOWER_LEFT,
 578 };
 579
 580 /**
 581  * Texture & format swizzles
 582  */
 583 enum pipe_swizzle {
 584    PIPE_SWIZZLE_X,
 585    PIPE_SWIZZLE_Y,
 586    PIPE_SWIZZLE_Z,
 587    PIPE_SWIZZLE_W,
 588    PIPE_SWIZZLE_0,
 589    PIPE_SWIZZLE_1,
 590    PIPE_SWIZZLE_NONE,
 591    PIPE_SWIZZLE_MAX, /**< Number of enums counter (must be last) */
 592 };
 593
 594 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
 595
 596
 597 /**
 598  * Device reset status.
 599  */
 600 enum pipe_reset_status
 601 {
 602    PIPE_NO_RESET,
 603    PIPE_GUILTY_CONTEXT_RESET,
 604    PIPE_INNOCENT_CONTEXT_RESET,
 605    PIPE_UNKNOWN_CONTEXT_RESET,
 606 };
 607
 608
 609 /**
 610  * resource_get_handle flags.
 611  */
 612 /* Requires pipe_context::flush_resource before external use. */
 613 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH  (1 << 0)
 614 /* Expected external use of the resource: */
 615 #define PIPE_HANDLE_USAGE_READ            (1 << 1)
 616 #define PIPE_HANDLE_USAGE_WRITE           (1 << 2)
 617 #define PIPE_HANDLE_USAGE_READ_WRITE      (PIPE_HANDLE_USAGE_READ | \
 618                                            PIPE_HANDLE_USAGE_WRITE)
 619
 620 /**
 621  * pipe_image_view access flags.
 622  */
 623 #define PIPE_IMAGE_ACCESS_READ       (1 << 0)
 624 #define PIPE_IMAGE_ACCESS_WRITE      (1 << 1)
 625 #define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \
 626                                       PIPE_IMAGE_ACCESS_WRITE)
 627
 628 /**
 629  * Implementation capabilities/limits which are queried through
 630  * pipe_screen::get_param()
 631  */
 632 enum pipe_cap
 633 {
 634    PIPE_CAP_NPOT_TEXTURES,
 635    PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS,
 636    PIPE_CAP_ANISOTROPIC_FILTER,
 637    PIPE_CAP_POINT_SPRITE,
 638    PIPE_CAP_MAX_RENDER_TARGETS,
 639    PIPE_CAP_OCCLUSION_QUERY,
 640    PIPE_CAP_QUERY_TIME_ELAPSED,
 641    PIPE_CAP_TEXTURE_SWIZZLE,
 642    PIPE_CAP_MAX_TEXTURE_2D_LEVELS,
 643    PIPE_CAP_MAX_TEXTURE_3D_LEVELS,
 644    PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS,
 645    PIPE_CAP_TEXTURE_MIRROR_CLAMP,
 646    PIPE_CAP_BLEND_EQUATION_SEPARATE,
 647    PIPE_CAP_SM3,
 648    PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS,
 649    PIPE_CAP_PRIMITIVE_RESTART,
 650    /** blend enables and write masks per rendertarget */
 651    PIPE_CAP_INDEP_BLEND_ENABLE,
 652    /** different blend funcs per rendertarget */
 653    PIPE_CAP_INDEP_BLEND_FUNC,
 654    PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS,
 655    PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT,
 656    PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT,
 657    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
 658    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
 659    PIPE_CAP_DEPTH_CLIP_DISABLE,
 660    PIPE_CAP_SHADER_STENCIL_EXPORT,
 661    PIPE_CAP_TGSI_INSTANCEID,
 662    PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
 663    PIPE_CAP_FRAGMENT_COLOR_CLAMPED,
 664    PIPE_CAP_MIXED_COLORBUFFER_FORMATS,
 665    PIPE_CAP_SEAMLESS_CUBE_MAP,
 666    PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE,
 667    PIPE_CAP_MIN_TEXEL_OFFSET,
 668    PIPE_CAP_MAX_TEXEL_OFFSET,
 669    PIPE_CAP_CONDITIONAL_RENDER,
 670    PIPE_CAP_TEXTURE_BARRIER,
 671    PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS,
 672    PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS,
 673    PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME,
 674    PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS,
 675    PIPE_CAP_VERTEX_COLOR_UNCLAMPED,
 676    PIPE_CAP_VERTEX_COLOR_CLAMPED,
 677    PIPE_CAP_GLSL_FEATURE_LEVEL,
 678    PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION,
 679    PIPE_CAP_USER_VERTEX_BUFFERS,
 680    PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY,
 681    PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY,
 682    PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY,
 683    PIPE_CAP_COMPUTE,
 684    PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
 685    PIPE_CAP_START_INSTANCE,
 686    PIPE_CAP_QUERY_TIMESTAMP,
 687    PIPE_CAP_TEXTURE_MULTISAMPLE,
 688    PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT,
 689    PIPE_CAP_CUBE_MAP_ARRAY,
 690    PIPE_CAP_TEXTURE_BUFFER_OBJECTS,
 691    PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT,
 692    PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY,
 693    PIPE_CAP_TGSI_TEXCOORD,
 694    PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER,
 695    PIPE_CAP_QUERY_PIPELINE_STATISTICS,
 696    PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK,
 697    PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE,
 698    PIPE_CAP_MAX_VIEWPORTS,
 699    PIPE_CAP_ENDIANNESS,
 700    PIPE_CAP_MIXED_FRAMEBUFFER_SIZES,
 701    PIPE_CAP_TGSI_VS_LAYER_VIEWPORT,
 702    PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES,
 703    PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS,
 704    PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS,
 705    PIPE_CAP_TEXTURE_GATHER_SM5,
 706    PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT,
 707    PIPE_CAP_FAKE_SW_MSAA,
 708    PIPE_CAP_TEXTURE_QUERY_LOD,
 709    PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET,
 710    PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET,
 711    PIPE_CAP_SAMPLE_SHADING,
 712    PIPE_CAP_TEXTURE_GATHER_OFFSETS,
 713    PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION,
 714    PIPE_CAP_MAX_VERTEX_STREAMS,
 715    PIPE_CAP_DRAW_INDIRECT,
 716    PIPE_CAP_TGSI_FS_FINE_DERIVATIVE,
 717    PIPE_CAP_VENDOR_ID,
 718    PIPE_CAP_DEVICE_ID,
 719    PIPE_CAP_ACCELERATED,
 720    PIPE_CAP_VIDEO_MEMORY,
 721    PIPE_CAP_UMA,
 722    PIPE_CAP_CONDITIONAL_RENDER_INVERTED,
 723    PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE,
 724    PIPE_CAP_SAMPLER_VIEW_TARGET,
 725    PIPE_CAP_CLIP_HALFZ,
 726    PIPE_CAP_VERTEXID_NOBASE,
 727    PIPE_CAP_POLYGON_OFFSET_CLAMP,
 728    PIPE_CAP_MULTISAMPLE_Z_RESOLVE,
 729    PIPE_CAP_RESOURCE_FROM_USER_MEMORY,
 730    PIPE_CAP_DEVICE_RESET_STATUS_QUERY,
 731    PIPE_CAP_MAX_SHADER_PATCH_VARYINGS,
 732    PIPE_CAP_TEXTURE_FLOAT_LINEAR,
 733    PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR,
 734    PIPE_CAP_DEPTH_BOUNDS_TEST,
 735    PIPE_CAP_TGSI_TXQS,
 736    PIPE_CAP_FORCE_PERSAMPLE_INTERP,
 737    PIPE_CAP_SHAREABLE_SHADERS,
 738    PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS,
 739    PIPE_CAP_CLEAR_TEXTURE,
 740    PIPE_CAP_DRAW_PARAMETERS,
 741    PIPE_CAP_TGSI_PACK_HALF_FLOAT,
 742    PIPE_CAP_MULTI_DRAW_INDIRECT,
 743    PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS,
 744    PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL,
 745    PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL,
 746    PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT,
 747    PIPE_CAP_INVALIDATE_BUFFER,
 748    PIPE_CAP_GENERATE_MIPMAP,
 749    PIPE_CAP_STRING_MARKER,
 750    PIPE_CAP_SURFACE_REINTERPRET_BLOCKS,
 751    PIPE_CAP_QUERY_BUFFER_OBJECT,
 752    PIPE_CAP_QUERY_MEMORY_INFO,
 753    PIPE_CAP_PCI_GROUP,
 754    PIPE_CAP_PCI_BUS,
 755    PIPE_CAP_PCI_DEVICE,
 756    PIPE_CAP_PCI_FUNCTION,
 757    PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT,
 758    PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR,
 759    PIPE_CAP_CULL_DISTANCE,
 760    PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES,
 761    PIPE_CAP_TGSI_VOTE,
 762    PIPE_CAP_MAX_WINDOW_RECTANGLES,
 763    PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED,
 764    PIPE_CAP_VIEWPORT_SUBPIXEL_BITS,
 765    PIPE_CAP_MIXED_COLOR_DEPTH_BITS,
 766    PIPE_CAP_TGSI_ARRAY_COMPONENTS,
 767    PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS,
 768    PIPE_CAP_TGSI_CAN_READ_OUTPUTS,
 769    PIPE_CAP_NATIVE_FENCE_FD,
 770    PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY,
 771    PIPE_CAP_TGSI_FS_FBFETCH,
 772    PIPE_CAP_TGSI_MUL_ZERO_WINS,
 773    PIPE_CAP_DOUBLES,
 774    PIPE_CAP_INT64,
 775    PIPE_CAP_INT64_DIVMOD,
 776    PIPE_CAP_TGSI_TEX_TXF_LZ,
 777    PIPE_CAP_TGSI_CLOCK,
 778    PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE,
 779    PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE,
 780    PIPE_CAP_TGSI_BALLOT,
 781    PIPE_CAP_TGSI_TES_LAYER_VIEWPORT,
 782    PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX,
 783    PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION,
 784    PIPE_CAP_POST_DEPTH_COVERAGE,
 785    PIPE_CAP_BINDLESS_TEXTURE,
 786    PIPE_CAP_NIR_SAMPLERS_AS_DEREF,
 787    PIPE_CAP_QUERY_SO_OVERFLOW,
 788    PIPE_CAP_MEMOBJ,
 789    PIPE_CAP_LOAD_CONSTBUF,
 790    PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS,
 791    PIPE_CAP_TILE_RASTER_ORDER,
 792    PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES,
 793    PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET,
 794    PIPE_CAP_CONTEXT_PRIORITY_MASK,
 795 };
 796
 797 /**
 798  * Possible bits for PIPE_CAP_CONTEXT_PRIORITY_MASK param, which should
 799  * return a bitmask of the supported priorities.  If the driver does not
 800  * support prioritized contexts, it can return 0.
 801  *
 802  * Note that these match __DRI2_RENDER_HAS_CONTEXT_PRIORITY_*
 803  */
 804 #define PIPE_CONTEXT_PRIORITY_LOW     (1 << 0)
 805 #define PIPE_CONTEXT_PRIORITY_MEDIUM  (1 << 1)
 806 #define PIPE_CONTEXT_PRIORITY_HIGH    (1 << 2)
 807
 808 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
 809 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
 810
 811 enum pipe_endian
 812 {
 813    PIPE_ENDIAN_LITTLE = 0,
 814    PIPE_ENDIAN_BIG = 1,
 815 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
 816    PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE
 817 #elif defined(PIPE_ARCH_BIG_ENDIAN)
 818    PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG
 819 #endif
 820 };
 821
 822 /**
 823  * Implementation limits which are queried through
 824  * pipe_screen::get_paramf()
 825  */
 826 enum pipe_capf
 827 {
 828    PIPE_CAPF_MAX_LINE_WIDTH,
 829    PIPE_CAPF_MAX_LINE_WIDTH_AA,
 830    PIPE_CAPF_MAX_POINT_WIDTH,
 831    PIPE_CAPF_MAX_POINT_WIDTH_AA,
 832    PIPE_CAPF_MAX_TEXTURE_ANISOTROPY,
 833    PIPE_CAPF_MAX_TEXTURE_LOD_BIAS,
 834    PIPE_CAPF_GUARD_BAND_LEFT,
 835    PIPE_CAPF_GUARD_BAND_TOP,
 836    PIPE_CAPF_GUARD_BAND_RIGHT,
 837    PIPE_CAPF_GUARD_BAND_BOTTOM
 838 };
 839
 840 /** Shader caps not specific to any single stage */
 841 enum pipe_shader_cap
 842 {
 843    PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
 844    PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
 845    PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
 846    PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
 847    PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
 848    PIPE_SHADER_CAP_MAX_INPUTS,
 849    PIPE_SHADER_CAP_MAX_OUTPUTS,
 850    PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE,
 851    PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
 852    PIPE_SHADER_CAP_MAX_TEMPS,
 853    /* boolean caps */
 854    PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
 855    PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
 856    PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
 857    PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
 858    PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
 859    PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
 860    PIPE_SHADER_CAP_INTEGERS,
 861    PIPE_SHADER_CAP_INT64_ATOMICS,
 862    PIPE_SHADER_CAP_FP16,
 863    PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
 864    PIPE_SHADER_CAP_PREFERRED_IR,
 865    PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
 866    PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
 867    PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */
 868    PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED,
 869    PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED,
 870    PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE,
 871    PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT,
 872    PIPE_SHADER_CAP_MAX_SHADER_BUFFERS,
 873    PIPE_SHADER_CAP_SUPPORTED_IRS,
 874    PIPE_SHADER_CAP_MAX_SHADER_IMAGES,
 875    PIPE_SHADER_CAP_LOWER_IF_THRESHOLD,
 876    PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS,
 877    PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED,
 878    PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS,
 879    PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS,
 880 };
 881
 882 /**
 883  * Shader intermediate representation.
 884  *
 885  * Note that if the driver requests something other than TGSI, it must
 886  * always be prepared to receive TGSI in addition to its preferred IR.
 887  * If the driver requests TGSI as its preferred IR, it will *always*
 888  * get TGSI.
 889  *
 890  * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with
 891  * state trackers that only understand TGSI.
 892  */
 893 enum pipe_shader_ir
 894 {
 895    PIPE_SHADER_IR_TGSI = 0,
 896    PIPE_SHADER_IR_LLVM,
 897    PIPE_SHADER_IR_NATIVE,
 898    PIPE_SHADER_IR_NIR,
 899 };
 900
 901 /**
 902  * Compute-specific implementation capability.  They can be queried
 903  * using pipe_screen::get_compute_param.
 904  */
 905 enum pipe_compute_cap
 906 {
 907    PIPE_COMPUTE_CAP_ADDRESS_BITS,
 908    PIPE_COMPUTE_CAP_IR_TARGET,
 909    PIPE_COMPUTE_CAP_GRID_DIMENSION,
 910    PIPE_COMPUTE_CAP_MAX_GRID_SIZE,
 911    PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE,
 912    PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 913    PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 914    PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE,
 915    PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE,
 916    PIPE_COMPUTE_CAP_MAX_INPUT_SIZE,
 917    PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 918    PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
 919    PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
 920    PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
 921    PIPE_COMPUTE_CAP_SUBGROUP_SIZE,
 922    PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
 923 };
 924
 925 /**
 926  * Composite query types
 927  */
 928
 929 /**
 930  * Query result for PIPE_QUERY_SO_STATISTICS.
 931  */
 932 struct pipe_query_data_so_statistics
 933 {
 934    uint64_t num_primitives_written;
 935    uint64_t primitives_storage_needed;
 936 };
 937
 938 /**
 939  * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
 940  */
 941 struct pipe_query_data_timestamp_disjoint
 942 {
 943    uint64_t frequency;
 944    boolean  disjoint;
 945 };
 946
 947 /**
 948  * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
 949  */
 950 struct pipe_query_data_pipeline_statistics
 951 {
 952    uint64_t ia_vertices;    /**< Num vertices read by the vertex fetcher. */
 953    uint64_t ia_primitives;  /**< Num primitives read by the vertex fetcher. */
 954    uint64_t vs_invocations; /**< Num vertex shader invocations. */
 955    uint64_t gs_invocations; /**< Num geometry shader invocations. */
 956    uint64_t gs_primitives;  /**< Num primitives output by a geometry shader. */
 957    uint64_t c_invocations;  /**< Num primitives sent to the rasterizer. */
 958    uint64_t c_primitives;   /**< Num primitives that were rendered. */
 959    uint64_t ps_invocations; /**< Num pixel shader invocations. */
 960    uint64_t hs_invocations; /**< Num hull shader invocations. */
 961    uint64_t ds_invocations; /**< Num domain shader invocations. */
 962    uint64_t cs_invocations; /**< Num compute shader invocations. */
 963 };
 964
 965 /**
 966  * For batch queries.
 967  */
 968 union pipe_numeric_type_union
 969 {
 970    uint64_t u64;
 971    uint32_t u32;
 972    float f;
 973 };
 974
 975 /**
 976  * Query result (returned by pipe_context::get_query_result).
 977  */
 978 union pipe_query_result
 979 {
 980    /* PIPE_QUERY_OCCLUSION_PREDICATE */
 981    /* PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE */
 982    /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
 983    /* PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE */
 984    /* PIPE_QUERY_GPU_FINISHED */
 985    boolean b;
 986
 987    /* PIPE_QUERY_OCCLUSION_COUNTER */
 988    /* PIPE_QUERY_TIMESTAMP */
 989    /* PIPE_QUERY_TIME_ELAPSED */
 990    /* PIPE_QUERY_PRIMITIVES_GENERATED */
 991    /* PIPE_QUERY_PRIMITIVES_EMITTED */
 992    /* PIPE_DRIVER_QUERY_TYPE_UINT64 */
 993    /* PIPE_DRIVER_QUERY_TYPE_BYTES */
 994    /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */
 995    /* PIPE_DRIVER_QUERY_TYPE_HZ */
 996    uint64_t u64;
 997
 998    /* PIPE_DRIVER_QUERY_TYPE_UINT */
 999    uint32_t u32;
1000
1001    /* PIPE_DRIVER_QUERY_TYPE_FLOAT */
1002    /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */
1003    float f;
1004
1005    /* PIPE_QUERY_SO_STATISTICS */
1006    struct pipe_query_data_so_statistics so_statistics;
1007
1008    /* PIPE_QUERY_TIMESTAMP_DISJOINT */
1009    struct pipe_query_data_timestamp_disjoint timestamp_disjoint;
1010
1011    /* PIPE_QUERY_PIPELINE_STATISTICS */
1012    struct pipe_query_data_pipeline_statistics pipeline_statistics;
1013
1014    /* batch queries (variable length) */
1015    union pipe_numeric_type_union batch[1];
1016 };
1017
1018 enum pipe_query_value_type
1019 {
1020    PIPE_QUERY_TYPE_I32,
1021    PIPE_QUERY_TYPE_U32,
1022    PIPE_QUERY_TYPE_I64,
1023    PIPE_QUERY_TYPE_U64,
1024 };
1025
1026 union pipe_color_union
1027 {
1028    float f[4];
1029    int i[4];
1030    unsigned int ui[4];
1031 };
1032
1033 enum pipe_driver_query_type
1034 {
1035    PIPE_DRIVER_QUERY_TYPE_UINT64,
1036    PIPE_DRIVER_QUERY_TYPE_UINT,
1037    PIPE_DRIVER_QUERY_TYPE_FLOAT,
1038    PIPE_DRIVER_QUERY_TYPE_PERCENTAGE,
1039    PIPE_DRIVER_QUERY_TYPE_BYTES,
1040    PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
1041    PIPE_DRIVER_QUERY_TYPE_HZ,
1042    PIPE_DRIVER_QUERY_TYPE_DBM,
1043    PIPE_DRIVER_QUERY_TYPE_TEMPERATURE,
1044    PIPE_DRIVER_QUERY_TYPE_VOLTS,
1045    PIPE_DRIVER_QUERY_TYPE_AMPS,
1046    PIPE_DRIVER_QUERY_TYPE_WATTS,
1047 };
1048
1049 /* Whether an average value per frame or a cumulative value should be
1050  * displayed.
1051  */
1052 enum pipe_driver_query_result_type
1053 {
1054    PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE,
1055    PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE,
1056 };
1057
1058 /**
1059  * Some hardware requires some hardware-specific queries to be submitted
1060  * as batched queries. The corresponding query objects are created using
1061  * create_batch_query, and at most one such query may be active at
1062  * any time.
1063  */
1064 #define PIPE_DRIVER_QUERY_FLAG_BATCH     (1 << 0)
1065
1066 /* Do not list this query in the HUD. */
1067 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1)
1068
1069 struct pipe_driver_query_info
1070 {
1071    const char *name;
1072    unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */
1073    union pipe_numeric_type_union max_value; /* max value that can be returned */
1074    enum pipe_driver_query_type type;
1075    enum pipe_driver_query_result_type result_type;
1076    unsigned group_id;
1077    unsigned flags;
1078 };
1079
1080 struct pipe_driver_query_group_info
1081 {
1082    const char *name;
1083    unsigned max_active_queries;
1084    unsigned num_queries;
1085 };
1086
1087 enum pipe_fd_type
1088 {
1089    PIPE_FD_TYPE_NATIVE_SYNC,
1090 };
1091
1092 enum pipe_debug_type
1093 {
1094    PIPE_DEBUG_TYPE_OUT_OF_MEMORY = 1,
1095    PIPE_DEBUG_TYPE_ERROR,
1096    PIPE_DEBUG_TYPE_SHADER_INFO,
1097    PIPE_DEBUG_TYPE_PERF_INFO,
1098    PIPE_DEBUG_TYPE_INFO,
1099    PIPE_DEBUG_TYPE_FALLBACK,
1100    PIPE_DEBUG_TYPE_CONFORMANCE,
1101 };
1102
1103 #define PIPE_UUID_SIZE 16
1104
1105 #ifdef __cplusplus
1106 }
1107 #endif
1108
1109 #endif