src/gallium/include/pipe/p_defines.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef PIPE_DEFINES_H
  29 #define PIPE_DEFINES_H
  30
  31 #include "p_compiler.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /**
  38  * Gallium error codes.
  39  *
  40  * - A zero value always means success.
  41  * - A negative value always means failure.
  42  * - The meaning of a positive value is function dependent.
  43  */
  44 enum pipe_error
  45 {
  46    PIPE_OK = 0,
  47    PIPE_ERROR = -1,    /**< Generic error */
  48    PIPE_ERROR_BAD_INPUT = -2,
  49    PIPE_ERROR_OUT_OF_MEMORY = -3,
  50    PIPE_ERROR_RETRY = -4
  51    /* TODO */
  52 };
  53
  54 enum pipe_blendfactor {
  55    PIPE_BLENDFACTOR_ONE = 1,
  56    PIPE_BLENDFACTOR_SRC_COLOR,
  57    PIPE_BLENDFACTOR_SRC_ALPHA,
  58    PIPE_BLENDFACTOR_DST_ALPHA,
  59    PIPE_BLENDFACTOR_DST_COLOR,
  60    PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE,
  61    PIPE_BLENDFACTOR_CONST_COLOR,
  62    PIPE_BLENDFACTOR_CONST_ALPHA,
  63    PIPE_BLENDFACTOR_SRC1_COLOR,
  64    PIPE_BLENDFACTOR_SRC1_ALPHA,
  65
  66    PIPE_BLENDFACTOR_ZERO = 0x11,
  67    PIPE_BLENDFACTOR_INV_SRC_COLOR,
  68    PIPE_BLENDFACTOR_INV_SRC_ALPHA,
  69    PIPE_BLENDFACTOR_INV_DST_ALPHA,
  70    PIPE_BLENDFACTOR_INV_DST_COLOR,
  71
  72    PIPE_BLENDFACTOR_INV_CONST_COLOR = 0x17,
  73    PIPE_BLENDFACTOR_INV_CONST_ALPHA,
  74    PIPE_BLENDFACTOR_INV_SRC1_COLOR,
  75    PIPE_BLENDFACTOR_INV_SRC1_ALPHA,
  76 };
  77
  78 enum pipe_blend_func {
  79    PIPE_BLEND_ADD,
  80    PIPE_BLEND_SUBTRACT,
  81    PIPE_BLEND_REVERSE_SUBTRACT,
  82    PIPE_BLEND_MIN,
  83    PIPE_BLEND_MAX,
  84 };
  85
  86 enum pipe_logicop {
  87    PIPE_LOGICOP_CLEAR,
  88    PIPE_LOGICOP_NOR,
  89    PIPE_LOGICOP_AND_INVERTED,
  90    PIPE_LOGICOP_COPY_INVERTED,
  91    PIPE_LOGICOP_AND_REVERSE,
  92    PIPE_LOGICOP_INVERT,
  93    PIPE_LOGICOP_XOR,
  94    PIPE_LOGICOP_NAND,
  95    PIPE_LOGICOP_AND,
  96    PIPE_LOGICOP_EQUIV,
  97    PIPE_LOGICOP_NOOP,
  98    PIPE_LOGICOP_OR_INVERTED,
  99    PIPE_LOGICOP_COPY,
 100    PIPE_LOGICOP_OR_REVERSE,
 101    PIPE_LOGICOP_OR,
 102    PIPE_LOGICOP_SET,
 103 };
 104
 105 #define PIPE_MASK_R  0x1
 106 #define PIPE_MASK_G  0x2
 107 #define PIPE_MASK_B  0x4
 108 #define PIPE_MASK_A  0x8
 109 #define PIPE_MASK_RGBA 0xf
 110 #define PIPE_MASK_Z  0x10
 111 #define PIPE_MASK_S  0x20
 112 #define PIPE_MASK_ZS 0x30
 113 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
 114
 115
 116 /**
 117  * Inequality functions.  Used for depth test, stencil compare, alpha
 118  * test, shadow compare, etc.
 119  */
 120 enum pipe_compare_func {
 121    PIPE_FUNC_NEVER,
 122    PIPE_FUNC_LESS,
 123    PIPE_FUNC_EQUAL,
 124    PIPE_FUNC_LEQUAL,
 125    PIPE_FUNC_GREATER,
 126    PIPE_FUNC_NOTEQUAL,
 127    PIPE_FUNC_GEQUAL,
 128    PIPE_FUNC_ALWAYS,
 129 };
 130
 131 /** Polygon fill mode */
 132 enum {
 133    PIPE_POLYGON_MODE_FILL,
 134    PIPE_POLYGON_MODE_LINE,
 135    PIPE_POLYGON_MODE_POINT,
 136    PIPE_POLYGON_MODE_FILL_RECTANGLE,
 137 };
 138
 139 /** Polygon face specification, eg for culling */
 140 #define PIPE_FACE_NONE           0
 141 #define PIPE_FACE_FRONT          1
 142 #define PIPE_FACE_BACK           2
 143 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
 144
 145 /** Stencil ops */
 146 enum pipe_stencil_op {
 147    PIPE_STENCIL_OP_KEEP,
 148    PIPE_STENCIL_OP_ZERO,
 149    PIPE_STENCIL_OP_REPLACE,
 150    PIPE_STENCIL_OP_INCR,
 151    PIPE_STENCIL_OP_DECR,
 152    PIPE_STENCIL_OP_INCR_WRAP,
 153    PIPE_STENCIL_OP_DECR_WRAP,
 154    PIPE_STENCIL_OP_INVERT,
 155 };
 156
 157 /** Texture types.
 158  * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D
 159  */
 160 enum pipe_texture_target
 161 {
 162    PIPE_BUFFER,
 163    PIPE_TEXTURE_1D,
 164    PIPE_TEXTURE_2D,
 165    PIPE_TEXTURE_3D,
 166    PIPE_TEXTURE_CUBE,
 167    PIPE_TEXTURE_RECT,
 168    PIPE_TEXTURE_1D_ARRAY,
 169    PIPE_TEXTURE_2D_ARRAY,
 170    PIPE_TEXTURE_CUBE_ARRAY,
 171    PIPE_MAX_TEXTURE_TYPES,
 172 };
 173
 174 enum pipe_tex_face {
 175    PIPE_TEX_FACE_POS_X,
 176    PIPE_TEX_FACE_NEG_X,
 177    PIPE_TEX_FACE_POS_Y,
 178    PIPE_TEX_FACE_NEG_Y,
 179    PIPE_TEX_FACE_POS_Z,
 180    PIPE_TEX_FACE_NEG_Z,
 181    PIPE_TEX_FACE_MAX,
 182 };
 183
 184 enum pipe_tex_wrap {
 185    PIPE_TEX_WRAP_REPEAT,
 186    PIPE_TEX_WRAP_CLAMP,
 187    PIPE_TEX_WRAP_CLAMP_TO_EDGE,
 188    PIPE_TEX_WRAP_CLAMP_TO_BORDER,
 189    PIPE_TEX_WRAP_MIRROR_REPEAT,
 190    PIPE_TEX_WRAP_MIRROR_CLAMP,
 191    PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE,
 192    PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER,
 193 };
 194
 195 /** Between mipmaps, ie mipfilter */
 196 enum pipe_tex_mipfilter {
 197    PIPE_TEX_MIPFILTER_NEAREST,
 198    PIPE_TEX_MIPFILTER_LINEAR,
 199    PIPE_TEX_MIPFILTER_NONE,
 200 };
 201
 202 /** Within a mipmap, ie min/mag filter */
 203 enum pipe_tex_filter {
 204    PIPE_TEX_FILTER_NEAREST,
 205    PIPE_TEX_FILTER_LINEAR,
 206 };
 207
 208 enum pipe_tex_compare {
 209    PIPE_TEX_COMPARE_NONE,
 210    PIPE_TEX_COMPARE_R_TO_TEXTURE,
 211 };
 212
 213 /**
 214  * Clear buffer bits
 215  */
 216 #define PIPE_CLEAR_DEPTH        (1 << 0)
 217 #define PIPE_CLEAR_STENCIL      (1 << 1)
 218 #define PIPE_CLEAR_COLOR0       (1 << 2)
 219 #define PIPE_CLEAR_COLOR1       (1 << 3)
 220 #define PIPE_CLEAR_COLOR2       (1 << 4)
 221 #define PIPE_CLEAR_COLOR3       (1 << 5)
 222 #define PIPE_CLEAR_COLOR4       (1 << 6)
 223 #define PIPE_CLEAR_COLOR5       (1 << 7)
 224 #define PIPE_CLEAR_COLOR6       (1 << 8)
 225 #define PIPE_CLEAR_COLOR7       (1 << 9)
 226 /** Combined flags */
 227 /** All color buffers currently bound */
 228 #define PIPE_CLEAR_COLOR        (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
 229                                  PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
 230                                  PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
 231                                  PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
 232 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
 233
 234 /**
 235  * Transfer object usage flags
 236  */
 237 enum pipe_transfer_usage
 238 {
 239    /**
 240     * Resource contents read back (or accessed directly) at transfer
 241     * create time.
 242     */
 243    PIPE_TRANSFER_READ = (1 << 0),
 244
 245    /**
 246     * Resource contents will be written back at transfer_unmap
 247     * time (or modified as a result of being accessed directly).
 248     */
 249    PIPE_TRANSFER_WRITE = (1 << 1),
 250
 251    /**
 252     * Read/modify/write
 253     */
 254    PIPE_TRANSFER_READ_WRITE = PIPE_TRANSFER_READ | PIPE_TRANSFER_WRITE,
 255
 256    /**
 257     * The transfer should map the texture storage directly. The driver may
 258     * return NULL if that isn't possible, and the gallium frontend needs to cope
 259     * with that and use an alternative path without this flag.
 260     *
 261     * E.g. the gallium frontend could have a simpler path which maps textures and
 262     * does read/modify/write cycles on them directly, and a more complicated
 263     * path which uses minimal read and write transfers.
 264     *
 265     * This flag supresses implicit "DISCARD" for buffer_subdata.
 266     */
 267    PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2),
 268
 269    /**
 270     * Discards the memory within the mapped region.
 271     *
 272     * It should not be used with PIPE_TRANSFER_READ.
 273     *
 274     * See also:
 275     * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
 276     */
 277    PIPE_TRANSFER_DISCARD_RANGE = (1 << 8),
 278
 279    /**
 280     * Fail if the resource cannot be mapped immediately.
 281     *
 282     * See also:
 283     * - Direct3D's D3DLOCK_DONOTWAIT flag.
 284     * - Mesa's MESA_MAP_NOWAIT_BIT flag.
 285     * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
 286     */
 287    PIPE_TRANSFER_DONTBLOCK = (1 << 9),
 288
 289    /**
 290     * Do not attempt to synchronize pending operations on the resource when mapping.
 291     *
 292     * It should not be used with PIPE_TRANSFER_READ.
 293     *
 294     * See also:
 295     * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag.
 296     * - Direct3D's D3DLOCK_NOOVERWRITE flag.
 297     * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
 298     */
 299    PIPE_TRANSFER_UNSYNCHRONIZED = (1 << 10),
 300
 301    /**
 302     * Written ranges will be notified later with
 303     * pipe_context::transfer_flush_region.
 304     *
 305     * It should not be used with PIPE_TRANSFER_READ.
 306     *
 307     * See also:
 308     * - pipe_context::transfer_flush_region
 309     * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
 310     */
 311    PIPE_TRANSFER_FLUSH_EXPLICIT = (1 << 11),
 312
 313    /**
 314     * Discards all memory backing the resource.
 315     *
 316     * It should not be used with PIPE_TRANSFER_READ.
 317     *
 318     * This is equivalent to:
 319     * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT
 320     * - BufferData(NULL) on a GL buffer
 321     * - Direct3D's D3DLOCK_DISCARD flag.
 322     * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag.
 323     * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
 324     * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
 325     */
 326    PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE = (1 << 12),
 327
 328    /**
 329     * Allows the resource to be used for rendering while mapped.
 330     *
 331     * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
 332     * the resource.
 333     *
 334     * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
 335     * must be called to ensure the device can see what the CPU has written.
 336     */
 337    PIPE_TRANSFER_PERSISTENT = (1 << 13),
 338
 339    /**
 340     * If PERSISTENT is set, this ensures any writes done by the device are
 341     * immediately visible to the CPU and vice versa.
 342     *
 343     * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
 344     * the resource.
 345     */
 346    PIPE_TRANSFER_COHERENT = (1 << 14),
 347
 348    /**
 349     * Map a resource in a thread-safe manner, because the calling thread can
 350     * be any thread. It can only be used if both WRITE and UNSYNCHRONIZED are
 351     * set.
 352     */
 353    PIPE_TRANSFER_THREAD_SAFE = 1 << 15,
 354
 355    /**
 356     * This and higher bits are reserved for private use by drivers. Drivers
 357     * should use this as (PIPE_TRANSFER_DRV_PRV << i).
 358     */
 359    PIPE_TRANSFER_DRV_PRV = (1 << 24)
 360 };
 361
 362 /**
 363  * Flags for the flush function.
 364  */
 365 enum pipe_flush_flags
 366 {
 367    PIPE_FLUSH_END_OF_FRAME = (1 << 0),
 368    PIPE_FLUSH_DEFERRED = (1 << 1),
 369    PIPE_FLUSH_FENCE_FD = (1 << 2),
 370    PIPE_FLUSH_ASYNC = (1 << 3),
 371    PIPE_FLUSH_HINT_FINISH = (1 << 4),
 372    PIPE_FLUSH_TOP_OF_PIPE = (1 << 5),
 373    PIPE_FLUSH_BOTTOM_OF_PIPE = (1 << 6),
 374 };
 375
 376 /**
 377  * Flags for pipe_context::dump_debug_state.
 378  */
 379 #define PIPE_DUMP_DEVICE_STATUS_REGISTERS    (1 << 0)
 380
 381 /**
 382  * Create a compute-only context. Use in pipe_screen::context_create.
 383  * This disables draw, blit, and clear*, render_condition, and other graphics
 384  * functions. Interop with other graphics contexts is still allowed.
 385  * This allows scheduling jobs on a compute-only hardware command queue that
 386  * can run in parallel with graphics without stalling it.
 387  */
 388 #define PIPE_CONTEXT_COMPUTE_ONLY      (1 << 0)
 389
 390 /**
 391  * Gather debug information and expect that pipe_context::dump_debug_state
 392  * will be called. Use in pipe_screen::context_create.
 393  */
 394 #define PIPE_CONTEXT_DEBUG             (1 << 1)
 395
 396 /**
 397  * Whether out-of-bounds shader loads must return zero and out-of-bounds
 398  * shader stores must be dropped.
 399  */
 400 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2)
 401
 402 /**
 403  * Prefer threaded pipe_context. It also implies that video codec functions
 404  * will not be used. (they will be either no-ops or NULL when threading is
 405  * enabled)
 406  */
 407 #define PIPE_CONTEXT_PREFER_THREADED   (1 << 3)
 408
 409 /**
 410  * Create a high priority context.
 411  */
 412 #define PIPE_CONTEXT_HIGH_PRIORITY     (1 << 4)
 413
 414 /**
 415  * Create a low priority context.
 416  */
 417 #define PIPE_CONTEXT_LOW_PRIORITY      (1 << 5)
 418
 419 /** Stop execution if the device is reset. */
 420 #define PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET (1 << 6)
 421
 422 /**
 423  * Flags for pipe_context::memory_barrier.
 424  */
 425 #define PIPE_BARRIER_MAPPED_BUFFER     (1 << 0)
 426 #define PIPE_BARRIER_SHADER_BUFFER     (1 << 1)
 427 #define PIPE_BARRIER_QUERY_BUFFER      (1 << 2)
 428 #define PIPE_BARRIER_VERTEX_BUFFER     (1 << 3)
 429 #define PIPE_BARRIER_INDEX_BUFFER      (1 << 4)
 430 #define PIPE_BARRIER_CONSTANT_BUFFER   (1 << 5)
 431 #define PIPE_BARRIER_INDIRECT_BUFFER   (1 << 6)
 432 #define PIPE_BARRIER_TEXTURE           (1 << 7)
 433 #define PIPE_BARRIER_IMAGE             (1 << 8)
 434 #define PIPE_BARRIER_FRAMEBUFFER       (1 << 9)
 435 #define PIPE_BARRIER_STREAMOUT_BUFFER  (1 << 10)
 436 #define PIPE_BARRIER_GLOBAL_BUFFER     (1 << 11)
 437 #define PIPE_BARRIER_UPDATE_BUFFER     (1 << 12)
 438 #define PIPE_BARRIER_UPDATE_TEXTURE    (1 << 13)
 439 #define PIPE_BARRIER_ALL               ((1 << 14) - 1)
 440
 441 #define PIPE_BARRIER_UPDATE \
 442    (PIPE_BARRIER_UPDATE_BUFFER | PIPE_BARRIER_UPDATE_TEXTURE)
 443
 444 /**
 445  * Flags for pipe_context::texture_barrier.
 446  */
 447 #define PIPE_TEXTURE_BARRIER_SAMPLER      (1 << 0)
 448 #define PIPE_TEXTURE_BARRIER_FRAMEBUFFER  (1 << 1)
 449
 450 /**
 451  * Resource binding flags -- gallium frontends must specify in advance all
 452  * the ways a resource might be used.
 453  */
 454 #define PIPE_BIND_DEPTH_STENCIL        (1 << 0) /* create_surface */
 455 #define PIPE_BIND_RENDER_TARGET        (1 << 1) /* create_surface */
 456 #define PIPE_BIND_BLENDABLE            (1 << 2) /* create_surface */
 457 #define PIPE_BIND_SAMPLER_VIEW         (1 << 3) /* create_sampler_view */
 458 #define PIPE_BIND_VERTEX_BUFFER        (1 << 4) /* set_vertex_buffers */
 459 #define PIPE_BIND_INDEX_BUFFER         (1 << 5) /* draw_elements */
 460 #define PIPE_BIND_CONSTANT_BUFFER      (1 << 6) /* set_constant_buffer */
 461 #define PIPE_BIND_DISPLAY_TARGET       (1 << 7) /* flush_front_buffer */
 462 /* gap */
 463 #define PIPE_BIND_STREAM_OUTPUT        (1 << 10) /* set_stream_output_buffers */
 464 #define PIPE_BIND_CURSOR               (1 << 11) /* mouse cursor */
 465 #define PIPE_BIND_CUSTOM               (1 << 12) /* gallium frontend/winsys usages */
 466 #define PIPE_BIND_GLOBAL               (1 << 13) /* set_global_binding */
 467 #define PIPE_BIND_SHADER_BUFFER        (1 << 14) /* set_shader_buffers */
 468 #define PIPE_BIND_SHADER_IMAGE         (1 << 15) /* set_shader_images */
 469 #define PIPE_BIND_COMPUTE_RESOURCE     (1 << 16) /* set_compute_resources */
 470 #define PIPE_BIND_COMMAND_ARGS_BUFFER  (1 << 17) /* pipe_draw_info.indirect */
 471 #define PIPE_BIND_QUERY_BUFFER         (1 << 18) /* get_query_result_resource */
 472
 473 /**
 474  * The first two flags above were previously part of the amorphous
 475  * TEXTURE_USAGE, most of which are now descriptions of the ways a
 476  * particular texture can be bound to the gallium pipeline.  The two flags
 477  * below do not fit within that and probably need to be migrated to some
 478  * other place.
 479  *
 480  * Scanout is used to ask for a texture suitable for actual scanout (hence
 481  * the name), which implies extra layout constraints on some hardware.
 482  * It may also have some special meaning regarding mouse cursor images.
 483  *
 484  * The shared flag is quite underspecified, but certainly isn't a
 485  * binding flag - it seems more like a message to the winsys to create
 486  * a shareable allocation.
 487  *
 488  * The third flag has been added to be able to force textures to be created
 489  * in linear mode (no tiling).
 490  */
 491 #define PIPE_BIND_SCANOUT     (1 << 19) /*  */
 492 #define PIPE_BIND_SHARED      (1 << 20) /* get_texture_handle ??? */
 493 #define PIPE_BIND_LINEAR      (1 << 21)
 494
 495
 496 /**
 497  * Flags for the driver about resource behaviour:
 498  */
 499 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
 500 #define PIPE_RESOURCE_FLAG_MAP_COHERENT   (1 << 1)
 501 #define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2)
 502 #define PIPE_RESOURCE_FLAG_SPARSE                (1 << 3)
 503 #define PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE     (1 << 4)
 504 #define PIPE_RESOURCE_FLAG_ENCRYPTED             (1 << 5)
 505 #define PIPE_RESOURCE_FLAG_DRV_PRIV    (1 << 8) /* driver/winsys private */
 506 #define PIPE_RESOURCE_FLAG_FRONTEND_PRIV         (1 << 24) /* gallium frontend private */
 507
 508 /**
 509  * Hint about the expected lifecycle of a resource.
 510  * Sorted according to GPU vs CPU access.
 511  */
 512 enum pipe_resource_usage {
 513    PIPE_USAGE_DEFAULT,        /* fast GPU access */
 514    PIPE_USAGE_IMMUTABLE,      /* fast GPU access, immutable */
 515    PIPE_USAGE_DYNAMIC,        /* uploaded data is used multiple times */
 516    PIPE_USAGE_STREAM,         /* uploaded data is used once */
 517    PIPE_USAGE_STAGING,        /* fast CPU access */
 518 };
 519
 520 /**
 521  * Shaders
 522  */
 523 enum pipe_shader_type {
 524    PIPE_SHADER_VERTEX,
 525    PIPE_SHADER_FRAGMENT,
 526    PIPE_SHADER_GEOMETRY,
 527    PIPE_SHADER_TESS_CTRL,
 528    PIPE_SHADER_TESS_EVAL,
 529    PIPE_SHADER_COMPUTE,
 530    PIPE_SHADER_TYPES,
 531 };
 532
 533 /**
 534  * Primitive types:
 535  */
 536 enum pipe_prim_type {
 537    PIPE_PRIM_POINTS,
 538    PIPE_PRIM_LINES,
 539    PIPE_PRIM_LINE_LOOP,
 540    PIPE_PRIM_LINE_STRIP,
 541    PIPE_PRIM_TRIANGLES,
 542    PIPE_PRIM_TRIANGLE_STRIP,
 543    PIPE_PRIM_TRIANGLE_FAN,
 544    PIPE_PRIM_QUADS,
 545    PIPE_PRIM_QUAD_STRIP,
 546    PIPE_PRIM_POLYGON,
 547    PIPE_PRIM_LINES_ADJACENCY,
 548    PIPE_PRIM_LINE_STRIP_ADJACENCY,
 549    PIPE_PRIM_TRIANGLES_ADJACENCY,
 550    PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY,
 551    PIPE_PRIM_PATCHES,
 552    PIPE_PRIM_MAX,
 553 };
 554
 555 /**
 556  * Tessellator spacing types
 557  */
 558 enum pipe_tess_spacing {
 559    PIPE_TESS_SPACING_FRACTIONAL_ODD,
 560    PIPE_TESS_SPACING_FRACTIONAL_EVEN,
 561    PIPE_TESS_SPACING_EQUAL,
 562 };
 563
 564 /**
 565  * Query object types
 566  */
 567 enum pipe_query_type {
 568    PIPE_QUERY_OCCLUSION_COUNTER,
 569    PIPE_QUERY_OCCLUSION_PREDICATE,
 570    PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE,
 571    PIPE_QUERY_TIMESTAMP,
 572    PIPE_QUERY_TIMESTAMP_DISJOINT,
 573    PIPE_QUERY_TIME_ELAPSED,
 574    PIPE_QUERY_PRIMITIVES_GENERATED,
 575    PIPE_QUERY_PRIMITIVES_EMITTED,
 576    PIPE_QUERY_SO_STATISTICS,
 577    PIPE_QUERY_SO_OVERFLOW_PREDICATE,
 578    PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE,
 579    PIPE_QUERY_GPU_FINISHED,
 580    PIPE_QUERY_PIPELINE_STATISTICS,
 581    PIPE_QUERY_PIPELINE_STATISTICS_SINGLE,
 582    PIPE_QUERY_TYPES,
 583    /* start of driver queries, see pipe_screen::get_driver_query_info */
 584    PIPE_QUERY_DRIVER_SPECIFIC = 256,
 585 };
 586
 587 /**
 588  * Index for PIPE_QUERY_PIPELINE_STATISTICS subqueries.
 589  */
 590 enum pipe_statistics_query_index {
 591    PIPE_STAT_QUERY_IA_VERTICES,
 592    PIPE_STAT_QUERY_IA_PRIMITIVES,
 593    PIPE_STAT_QUERY_VS_INVOCATIONS,
 594    PIPE_STAT_QUERY_GS_INVOCATIONS,
 595    PIPE_STAT_QUERY_GS_PRIMITIVES,
 596    PIPE_STAT_QUERY_C_INVOCATIONS,
 597    PIPE_STAT_QUERY_C_PRIMITIVES,
 598    PIPE_STAT_QUERY_PS_INVOCATIONS,
 599    PIPE_STAT_QUERY_HS_INVOCATIONS,
 600    PIPE_STAT_QUERY_DS_INVOCATIONS,
 601    PIPE_STAT_QUERY_CS_INVOCATIONS,
 602 };
 603
 604 /**
 605  * Conditional rendering modes
 606  */
 607 enum pipe_render_cond_flag {
 608    PIPE_RENDER_COND_WAIT,
 609    PIPE_RENDER_COND_NO_WAIT,
 610    PIPE_RENDER_COND_BY_REGION_WAIT,
 611    PIPE_RENDER_COND_BY_REGION_NO_WAIT,
 612 };
 613
 614 /**
 615  * Point sprite coord modes
 616  */
 617 enum pipe_sprite_coord_mode {
 618    PIPE_SPRITE_COORD_UPPER_LEFT,
 619    PIPE_SPRITE_COORD_LOWER_LEFT,
 620 };
 621
 622 /**
 623  * Texture & format swizzles
 624  */
 625 enum pipe_swizzle {
 626    PIPE_SWIZZLE_X,
 627    PIPE_SWIZZLE_Y,
 628    PIPE_SWIZZLE_Z,
 629    PIPE_SWIZZLE_W,
 630    PIPE_SWIZZLE_0,
 631    PIPE_SWIZZLE_1,
 632    PIPE_SWIZZLE_NONE,
 633    PIPE_SWIZZLE_MAX, /**< Number of enums counter (must be last) */
 634 };
 635
 636 /**
 637  * Viewport swizzles
 638  */
 639 enum pipe_viewport_swizzle {
 640    PIPE_VIEWPORT_SWIZZLE_POSITIVE_X,
 641    PIPE_VIEWPORT_SWIZZLE_NEGATIVE_X,
 642    PIPE_VIEWPORT_SWIZZLE_POSITIVE_Y,
 643    PIPE_VIEWPORT_SWIZZLE_NEGATIVE_Y,
 644    PIPE_VIEWPORT_SWIZZLE_POSITIVE_Z,
 645    PIPE_VIEWPORT_SWIZZLE_NEGATIVE_Z,
 646    PIPE_VIEWPORT_SWIZZLE_POSITIVE_W,
 647    PIPE_VIEWPORT_SWIZZLE_NEGATIVE_W,
 648 };
 649
 650 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
 651
 652
 653 /**
 654  * Device reset status.
 655  */
 656 enum pipe_reset_status
 657 {
 658    PIPE_NO_RESET,
 659    PIPE_GUILTY_CONTEXT_RESET,
 660    PIPE_INNOCENT_CONTEXT_RESET,
 661    PIPE_UNKNOWN_CONTEXT_RESET,
 662 };
 663
 664
 665 /**
 666  * Conservative rasterization modes.
 667  */
 668 enum pipe_conservative_raster_mode
 669 {
 670    PIPE_CONSERVATIVE_RASTER_OFF,
 671
 672    /**
 673     * The post-snap mode means the conservative rasterization occurs after
 674     * the conversion from floating-point to fixed-point coordinates
 675     * on the subpixel grid.
 676     */
 677    PIPE_CONSERVATIVE_RASTER_POST_SNAP,
 678
 679    /**
 680     * The pre-snap mode means the conservative rasterization occurs before
 681     * the conversion from floating-point to fixed-point coordinates.
 682     */
 683    PIPE_CONSERVATIVE_RASTER_PRE_SNAP,
 684 };
 685
 686
 687 /**
 688  * resource_get_handle flags.
 689  */
 690 /* Requires pipe_context::flush_resource before external use. */
 691 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH     (1 << 0)
 692 /* Expected external use of the resource: */
 693 #define PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE  (1 << 1)
 694 #define PIPE_HANDLE_USAGE_SHADER_WRITE       (1 << 2)
 695
 696 /**
 697  * pipe_image_view access flags.
 698  */
 699 #define PIPE_IMAGE_ACCESS_READ       (1 << 0)
 700 #define PIPE_IMAGE_ACCESS_WRITE      (1 << 1)
 701 #define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \
 702                                       PIPE_IMAGE_ACCESS_WRITE)
 703
 704 /**
 705  * Implementation capabilities/limits which are queried through
 706  * pipe_screen::get_param()
 707  */
 708 enum pipe_cap
 709 {
 710    PIPE_CAP_GRAPHICS,
 711    PIPE_CAP_NPOT_TEXTURES,
 712    PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS,
 713    PIPE_CAP_ANISOTROPIC_FILTER,
 714    PIPE_CAP_POINT_SPRITE,
 715    PIPE_CAP_MAX_RENDER_TARGETS,
 716    PIPE_CAP_OCCLUSION_QUERY,
 717    PIPE_CAP_QUERY_TIME_ELAPSED,
 718    PIPE_CAP_TEXTURE_SHADOW_MAP,
 719    PIPE_CAP_TEXTURE_SWIZZLE,
 720    PIPE_CAP_MAX_TEXTURE_2D_SIZE,
 721    PIPE_CAP_MAX_TEXTURE_3D_LEVELS,
 722    PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS,
 723    PIPE_CAP_TEXTURE_MIRROR_CLAMP,
 724    PIPE_CAP_BLEND_EQUATION_SEPARATE,
 725    PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS,
 726    PIPE_CAP_PRIMITIVE_RESTART,
 727    /** subset of PRIMITIVE_RESTART where the restart index is always the fixed
 728     * maximum value for the index type
 729     */
 730    PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX,
 731    /** blend enables and write masks per rendertarget */
 732    PIPE_CAP_INDEP_BLEND_ENABLE,
 733    /** different blend funcs per rendertarget */
 734    PIPE_CAP_INDEP_BLEND_FUNC,
 735    PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS,
 736    PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT,
 737    PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT,
 738    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
 739    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
 740    PIPE_CAP_DEPTH_CLIP_DISABLE,
 741    PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE,
 742    PIPE_CAP_SHADER_STENCIL_EXPORT,
 743    PIPE_CAP_TGSI_INSTANCEID,
 744    PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
 745    PIPE_CAP_FRAGMENT_COLOR_CLAMPED,
 746    PIPE_CAP_MIXED_COLORBUFFER_FORMATS,
 747    PIPE_CAP_SEAMLESS_CUBE_MAP,
 748    PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE,
 749    PIPE_CAP_MIN_TEXEL_OFFSET,
 750    PIPE_CAP_MAX_TEXEL_OFFSET,
 751    PIPE_CAP_CONDITIONAL_RENDER,
 752    PIPE_CAP_TEXTURE_BARRIER,
 753    PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS,
 754    PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS,
 755    PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME,
 756    PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS,
 757    PIPE_CAP_VERTEX_COLOR_UNCLAMPED,
 758    PIPE_CAP_VERTEX_COLOR_CLAMPED,
 759    PIPE_CAP_GLSL_FEATURE_LEVEL,
 760    PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY,
 761    PIPE_CAP_ESSL_FEATURE_LEVEL,
 762    PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION,
 763    PIPE_CAP_USER_VERTEX_BUFFERS,
 764    PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY,
 765    PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY,
 766    PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY,
 767    PIPE_CAP_COMPUTE,
 768    PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
 769    PIPE_CAP_START_INSTANCE,
 770    PIPE_CAP_QUERY_TIMESTAMP,
 771    PIPE_CAP_TEXTURE_MULTISAMPLE,
 772    PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT,
 773    PIPE_CAP_CUBE_MAP_ARRAY,
 774    PIPE_CAP_TEXTURE_BUFFER_OBJECTS,
 775    PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT,
 776    PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY,
 777    PIPE_CAP_TGSI_TEXCOORD,
 778    PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER,
 779    PIPE_CAP_QUERY_PIPELINE_STATISTICS,
 780    PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK,
 781    PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE,
 782    PIPE_CAP_MAX_VIEWPORTS,
 783    PIPE_CAP_ENDIANNESS,
 784    PIPE_CAP_MIXED_FRAMEBUFFER_SIZES,
 785    PIPE_CAP_TGSI_VS_LAYER_VIEWPORT,
 786    PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES,
 787    PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS,
 788    PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS,
 789    PIPE_CAP_TEXTURE_GATHER_SM5,
 790    PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT,
 791    PIPE_CAP_FAKE_SW_MSAA,
 792    PIPE_CAP_TEXTURE_QUERY_LOD,
 793    PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET,
 794    PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET,
 795    PIPE_CAP_SAMPLE_SHADING,
 796    PIPE_CAP_TEXTURE_GATHER_OFFSETS,
 797    PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION,
 798    PIPE_CAP_MAX_VERTEX_STREAMS,
 799    PIPE_CAP_DRAW_INDIRECT,
 800    PIPE_CAP_TGSI_FS_FINE_DERIVATIVE,
 801    PIPE_CAP_VENDOR_ID,
 802    PIPE_CAP_DEVICE_ID,
 803    PIPE_CAP_ACCELERATED,
 804    PIPE_CAP_VIDEO_MEMORY,
 805    PIPE_CAP_UMA,
 806    PIPE_CAP_CONDITIONAL_RENDER_INVERTED,
 807    PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE,
 808    PIPE_CAP_SAMPLER_VIEW_TARGET,
 809    PIPE_CAP_CLIP_HALFZ,
 810    PIPE_CAP_VERTEXID_NOBASE,
 811    PIPE_CAP_POLYGON_OFFSET_CLAMP,
 812    PIPE_CAP_MULTISAMPLE_Z_RESOLVE,
 813    PIPE_CAP_RESOURCE_FROM_USER_MEMORY,
 814    PIPE_CAP_RESOURCE_FROM_USER_MEMORY_COMPUTE_ONLY,
 815    PIPE_CAP_DEVICE_RESET_STATUS_QUERY,
 816    PIPE_CAP_MAX_SHADER_PATCH_VARYINGS,
 817    PIPE_CAP_TEXTURE_FLOAT_LINEAR,
 818    PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR,
 819    PIPE_CAP_DEPTH_BOUNDS_TEST,
 820    PIPE_CAP_TGSI_TXQS,
 821    PIPE_CAP_FORCE_PERSAMPLE_INTERP,
 822    PIPE_CAP_SHAREABLE_SHADERS,
 823    PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS,
 824    PIPE_CAP_CLEAR_TEXTURE,
 825    PIPE_CAP_CLEAR_SCISSORED,
 826    PIPE_CAP_DRAW_PARAMETERS,
 827    PIPE_CAP_TGSI_PACK_HALF_FLOAT,
 828    PIPE_CAP_MULTI_DRAW_INDIRECT,
 829    PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS,
 830    PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL,
 831    PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL,
 832    PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL,
 833    PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT,
 834    PIPE_CAP_INVALIDATE_BUFFER,
 835    PIPE_CAP_GENERATE_MIPMAP,
 836    PIPE_CAP_STRING_MARKER,
 837    PIPE_CAP_SURFACE_REINTERPRET_BLOCKS,
 838    PIPE_CAP_QUERY_BUFFER_OBJECT,
 839    PIPE_CAP_QUERY_MEMORY_INFO,
 840    PIPE_CAP_PCI_GROUP,
 841    PIPE_CAP_PCI_BUS,
 842    PIPE_CAP_PCI_DEVICE,
 843    PIPE_CAP_PCI_FUNCTION,
 844    PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT,
 845    PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR,
 846    PIPE_CAP_CULL_DISTANCE,
 847    PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES,
 848    PIPE_CAP_TGSI_VOTE,
 849    PIPE_CAP_MAX_WINDOW_RECTANGLES,
 850    PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED,
 851    PIPE_CAP_VIEWPORT_SUBPIXEL_BITS,
 852    PIPE_CAP_RASTERIZER_SUBPIXEL_BITS,
 853    PIPE_CAP_MIXED_COLOR_DEPTH_BITS,
 854    PIPE_CAP_TGSI_ARRAY_COMPONENTS,
 855    PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS,
 856    PIPE_CAP_TGSI_CAN_READ_OUTPUTS,
 857    PIPE_CAP_NATIVE_FENCE_FD,
 858    PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY,
 859    PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS,
 860    PIPE_CAP_FBFETCH,
 861    PIPE_CAP_TGSI_MUL_ZERO_WINS,
 862    PIPE_CAP_DOUBLES,
 863    PIPE_CAP_INT64,
 864    PIPE_CAP_INT64_DIVMOD,
 865    PIPE_CAP_TGSI_TEX_TXF_LZ,
 866    PIPE_CAP_TGSI_CLOCK,
 867    PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE,
 868    PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE,
 869    PIPE_CAP_TGSI_BALLOT,
 870    PIPE_CAP_TGSI_TES_LAYER_VIEWPORT,
 871    PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX,
 872    PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION,
 873    PIPE_CAP_POST_DEPTH_COVERAGE,
 874    PIPE_CAP_BINDLESS_TEXTURE,
 875    PIPE_CAP_NIR_SAMPLERS_AS_DEREF,
 876    PIPE_CAP_QUERY_SO_OVERFLOW,
 877    PIPE_CAP_MEMOBJ,
 878    PIPE_CAP_LOAD_CONSTBUF,
 879    PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS,
 880    PIPE_CAP_TILE_RASTER_ORDER,
 881    PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES,
 882    PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS,
 883    PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET,
 884    PIPE_CAP_CONTEXT_PRIORITY_MASK,
 885    PIPE_CAP_FENCE_SIGNAL,
 886    PIPE_CAP_CONSTBUF0_FLAGS,
 887    PIPE_CAP_PACKED_UNIFORMS,
 888    PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES,
 889    PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES,
 890    PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES,
 891    PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES,
 892    PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS,
 893    PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE,
 894    PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE,
 895    PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS,
 896    PIPE_CAP_MAX_GS_INVOCATIONS,
 897    PIPE_CAP_MAX_SHADER_BUFFER_SIZE,
 898    PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE,
 899    PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS,
 900    PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS,
 901    PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS,
 902    PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET,
 903    PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET,
 904    PIPE_CAP_SURFACE_SAMPLE_COUNT,
 905    PIPE_CAP_TGSI_ATOMFADD,
 906    PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE,
 907    PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND,
 908    PIPE_CAP_DEST_SURFACE_SRGB_CONTROL,
 909    PIPE_CAP_NIR_COMPACT_ARRAYS,
 910    PIPE_CAP_MAX_VARYINGS,
 911    PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK,
 912    PIPE_CAP_COMPUTE_SHADER_DERIVATIVES,
 913    PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS,
 914    PIPE_CAP_IMAGE_LOAD_FORMATTED,
 915    PIPE_CAP_THROTTLE,
 916    PIPE_CAP_DMABUF,
 917    PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA,
 918    PIPE_CAP_FRAGMENT_SHADER_INTERLOCK,
 919    PIPE_CAP_FBFETCH_COHERENT,
 920    PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED,
 921    PIPE_CAP_ATOMIC_FLOAT_MINMAX,
 922    PIPE_CAP_TGSI_DIV,
 923    PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD,
 924    PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES,
 925    PIPE_CAP_VERTEX_SHADER_SATURATE,
 926    PIPE_CAP_TEXTURE_SHADOW_LOD,
 927    PIPE_CAP_SHADER_SAMPLES_IDENTICAL,
 928    PIPE_CAP_TGSI_ATOMINC_WRAP,
 929    PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF,
 930    PIPE_CAP_GL_SPIRV,
 931    PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS,
 932    PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION,
 933    PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE,
 934    PIPE_CAP_FLATSHADE,
 935    PIPE_CAP_ALPHA_TEST,
 936    PIPE_CAP_POINT_SIZE_FIXED,
 937    PIPE_CAP_TWO_SIDED_COLOR,
 938    PIPE_CAP_CLIP_PLANES,
 939    PIPE_CAP_MAX_VERTEX_BUFFERS,
 940    PIPE_CAP_OPENCL_INTEGER_FUNCTIONS,
 941    PIPE_CAP_INTEGER_MULTIPLY_32X16,
 942    /* Turn draw, dispatch, blit into NOOP */
 943    PIPE_CAP_FRONTEND_NOOP,
 944    PIPE_CAP_NIR_IMAGES_AS_DEREF,
 945    PIPE_CAP_PACKED_STREAM_OUTPUT,
 946    PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED,
 947    PIPE_CAP_PSIZ_CLAMPED,
 948    PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES,
 949    PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE,
 950    PIPE_CAP_VIEWPORT_SWIZZLE,
 951    PIPE_CAP_SYSTEM_SVM,
 952    PIPE_CAP_VIEWPORT_MASK,
 953    PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL,
 954    PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE,
 955    PIPE_CAP_GLSL_ZERO_INIT,
 956    PIPE_CAP_BLEND_EQUATION_ADVANCED,
 957 };
 958
 959 /**
 960  * Possible bits for PIPE_CAP_CONTEXT_PRIORITY_MASK param, which should
 961  * return a bitmask of the supported priorities.  If the driver does not
 962  * support prioritized contexts, it can return 0.
 963  *
 964  * Note that these match __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_*
 965  */
 966 #define PIPE_CONTEXT_PRIORITY_LOW     (1 << 0)
 967 #define PIPE_CONTEXT_PRIORITY_MEDIUM  (1 << 1)
 968 #define PIPE_CONTEXT_PRIORITY_HIGH    (1 << 2)
 969
 970 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
 971 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
 972
 973 enum pipe_endian
 974 {
 975    PIPE_ENDIAN_LITTLE = 0,
 976    PIPE_ENDIAN_BIG = 1,
 977 #if UTIL_ARCH_LITTLE_ENDIAN
 978    PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE
 979 #elif UTIL_ARCH_BIG_ENDIAN
 980    PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG
 981 #endif
 982 };
 983
 984 /**
 985  * Implementation limits which are queried through
 986  * pipe_screen::get_paramf()
 987  */
 988 enum pipe_capf
 989 {
 990    PIPE_CAPF_MAX_LINE_WIDTH,
 991    PIPE_CAPF_MAX_LINE_WIDTH_AA,
 992    PIPE_CAPF_MAX_POINT_WIDTH,
 993    PIPE_CAPF_MAX_POINT_WIDTH_AA,
 994    PIPE_CAPF_MAX_TEXTURE_ANISOTROPY,
 995    PIPE_CAPF_MAX_TEXTURE_LOD_BIAS,
 996    PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE,
 997    PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE,
 998    PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY,
 999 };
1000
1001 /** Shader caps not specific to any single stage */
1002 enum pipe_shader_cap
1003 {
1004    PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
1005    PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
1006    PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
1007    PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
1008    PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
1009    PIPE_SHADER_CAP_MAX_INPUTS,
1010    PIPE_SHADER_CAP_MAX_OUTPUTS,
1011    PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE,
1012    PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
1013    PIPE_SHADER_CAP_MAX_TEMPS,
1014    /* boolean caps */
1015    PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
1016    PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
1017    PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
1018    PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
1019    PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
1020    PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
1021    PIPE_SHADER_CAP_INTEGERS,
1022    PIPE_SHADER_CAP_INT64_ATOMICS,
1023    PIPE_SHADER_CAP_FP16,
1024    PIPE_SHADER_CAP_FP16_DERIVATIVES,
1025    PIPE_SHADER_CAP_INT16,
1026    PIPE_SHADER_CAP_GLSL_16BIT_CONSTS,
1027    PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
1028    PIPE_SHADER_CAP_PREFERRED_IR,
1029    PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
1030    PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
1031    PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */
1032    PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED,
1033    PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED,
1034    PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE,
1035    PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT,
1036    PIPE_SHADER_CAP_MAX_SHADER_BUFFERS,
1037    PIPE_SHADER_CAP_SUPPORTED_IRS,
1038    PIPE_SHADER_CAP_MAX_SHADER_IMAGES,
1039    PIPE_SHADER_CAP_LOWER_IF_THRESHOLD,
1040    PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS,
1041    PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED,
1042    PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS,
1043    PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS,
1044 };
1045
1046 /**
1047  * Shader intermediate representation.
1048  *
1049  * Note that if the driver requests something other than TGSI, it must
1050  * always be prepared to receive TGSI in addition to its preferred IR.
1051  * If the driver requests TGSI as its preferred IR, it will *always*
1052  * get TGSI.
1053  *
1054  * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with
1055  * gallium frontends that only understand TGSI.
1056  */
1057 enum pipe_shader_ir
1058 {
1059    PIPE_SHADER_IR_TGSI = 0,
1060    PIPE_SHADER_IR_NATIVE,
1061    PIPE_SHADER_IR_NIR,
1062    PIPE_SHADER_IR_NIR_SERIALIZED,
1063 };
1064
1065 /**
1066  * Compute-specific implementation capability.  They can be queried
1067  * using pipe_screen::get_compute_param.
1068  */
1069 enum pipe_compute_cap
1070 {
1071    PIPE_COMPUTE_CAP_ADDRESS_BITS,
1072    PIPE_COMPUTE_CAP_IR_TARGET,
1073    PIPE_COMPUTE_CAP_GRID_DIMENSION,
1074    PIPE_COMPUTE_CAP_MAX_GRID_SIZE,
1075    PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE,
1076    PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
1077    PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
1078    PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE,
1079    PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE,
1080    PIPE_COMPUTE_CAP_MAX_INPUT_SIZE,
1081    PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1082    PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
1083    PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
1084    PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
1085    PIPE_COMPUTE_CAP_SUBGROUP_SIZE,
1086    PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
1087 };
1088
1089 /**
1090  * Resource parameters. They can be queried using
1091  * pipe_screen::get_resource_param.
1092  */
1093 enum pipe_resource_param
1094 {
1095    PIPE_RESOURCE_PARAM_NPLANES,
1096    PIPE_RESOURCE_PARAM_STRIDE,
1097    PIPE_RESOURCE_PARAM_OFFSET,
1098    PIPE_RESOURCE_PARAM_MODIFIER,
1099    PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED,
1100    PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS,
1101    PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD,
1102 };
1103
1104 /**
1105  * Types of parameters for pipe_context::set_context_param.
1106  */
1107 enum pipe_context_param
1108 {
1109    /* A hint for the driver that it should pin its execution threads to
1110     * a group of cores sharing a specific L3 cache if the CPU has multiple
1111     * L3 caches. This is needed for good multithreading performance on
1112     * AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have
1113     * any internal threads or don't run on affected CPUs can ignore this.
1114     */
1115    PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
1116 };
1117
1118 /**
1119  * Composite query types
1120  */
1121
1122 /**
1123  * Query result for PIPE_QUERY_SO_STATISTICS.
1124  */
1125 struct pipe_query_data_so_statistics
1126 {
1127    uint64_t num_primitives_written;
1128    uint64_t primitives_storage_needed;
1129 };
1130
1131 /**
1132  * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
1133  */
1134 struct pipe_query_data_timestamp_disjoint
1135 {
1136    uint64_t frequency;
1137    bool     disjoint;
1138 };
1139
1140 /**
1141  * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
1142  */
1143 struct pipe_query_data_pipeline_statistics
1144 {
1145    uint64_t ia_vertices;    /**< Num vertices read by the vertex fetcher. */
1146    uint64_t ia_primitives;  /**< Num primitives read by the vertex fetcher. */
1147    uint64_t vs_invocations; /**< Num vertex shader invocations. */
1148    uint64_t gs_invocations; /**< Num geometry shader invocations. */
1149    uint64_t gs_primitives;  /**< Num primitives output by a geometry shader. */
1150    uint64_t c_invocations;  /**< Num primitives sent to the rasterizer. */
1151    uint64_t c_primitives;   /**< Num primitives that were rendered. */
1152    uint64_t ps_invocations; /**< Num pixel shader invocations. */
1153    uint64_t hs_invocations; /**< Num hull shader invocations. */
1154    uint64_t ds_invocations; /**< Num domain shader invocations. */
1155    uint64_t cs_invocations; /**< Num compute shader invocations. */
1156 };
1157
1158 /**
1159  * For batch queries.
1160  */
1161 union pipe_numeric_type_union
1162 {
1163    uint64_t u64;
1164    uint32_t u32;
1165    float f;
1166 };
1167
1168 /**
1169  * Query result (returned by pipe_context::get_query_result).
1170  */
1171 union pipe_query_result
1172 {
1173    /* PIPE_QUERY_OCCLUSION_PREDICATE */
1174    /* PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE */
1175    /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
1176    /* PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE */
1177    /* PIPE_QUERY_GPU_FINISHED */
1178    bool b;
1179
1180    /* PIPE_QUERY_OCCLUSION_COUNTER */
1181    /* PIPE_QUERY_TIMESTAMP */
1182    /* PIPE_QUERY_TIME_ELAPSED */
1183    /* PIPE_QUERY_PRIMITIVES_GENERATED */
1184    /* PIPE_QUERY_PRIMITIVES_EMITTED */
1185    /* PIPE_DRIVER_QUERY_TYPE_UINT64 */
1186    /* PIPE_DRIVER_QUERY_TYPE_BYTES */
1187    /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */
1188    /* PIPE_DRIVER_QUERY_TYPE_HZ */
1189    uint64_t u64;
1190
1191    /* PIPE_DRIVER_QUERY_TYPE_UINT */
1192    uint32_t u32;
1193
1194    /* PIPE_DRIVER_QUERY_TYPE_FLOAT */
1195    /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */
1196    float f;
1197
1198    /* PIPE_QUERY_SO_STATISTICS */
1199    struct pipe_query_data_so_statistics so_statistics;
1200
1201    /* PIPE_QUERY_TIMESTAMP_DISJOINT */
1202    struct pipe_query_data_timestamp_disjoint timestamp_disjoint;
1203
1204    /* PIPE_QUERY_PIPELINE_STATISTICS */
1205    struct pipe_query_data_pipeline_statistics pipeline_statistics;
1206
1207    /* batch queries (variable length) */
1208    union pipe_numeric_type_union batch[1];
1209 };
1210
1211 enum pipe_query_value_type
1212 {
1213    PIPE_QUERY_TYPE_I32,
1214    PIPE_QUERY_TYPE_U32,
1215    PIPE_QUERY_TYPE_I64,
1216    PIPE_QUERY_TYPE_U64,
1217 };
1218
1219 union pipe_color_union
1220 {
1221    float f[4];
1222    int i[4];
1223    unsigned int ui[4];
1224 };
1225
1226 enum pipe_driver_query_type
1227 {
1228    PIPE_DRIVER_QUERY_TYPE_UINT64,
1229    PIPE_DRIVER_QUERY_TYPE_UINT,
1230    PIPE_DRIVER_QUERY_TYPE_FLOAT,
1231    PIPE_DRIVER_QUERY_TYPE_PERCENTAGE,
1232    PIPE_DRIVER_QUERY_TYPE_BYTES,
1233    PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
1234    PIPE_DRIVER_QUERY_TYPE_HZ,
1235    PIPE_DRIVER_QUERY_TYPE_DBM,
1236    PIPE_DRIVER_QUERY_TYPE_TEMPERATURE,
1237    PIPE_DRIVER_QUERY_TYPE_VOLTS,
1238    PIPE_DRIVER_QUERY_TYPE_AMPS,
1239    PIPE_DRIVER_QUERY_TYPE_WATTS,
1240 };
1241
1242 /* Whether an average value per frame or a cumulative value should be
1243  * displayed.
1244  */
1245 enum pipe_driver_query_result_type
1246 {
1247    PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE,
1248    PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE,
1249 };
1250
1251 /**
1252  * Some hardware requires some hardware-specific queries to be submitted
1253  * as batched queries. The corresponding query objects are created using
1254  * create_batch_query, and at most one such query may be active at
1255  * any time.
1256  */
1257 #define PIPE_DRIVER_QUERY_FLAG_BATCH     (1 << 0)
1258
1259 /* Do not list this query in the HUD. */
1260 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1)
1261
1262 struct pipe_driver_query_info
1263 {
1264    const char *name;
1265    unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */
1266    union pipe_numeric_type_union max_value; /* max value that can be returned */
1267    enum pipe_driver_query_type type;
1268    enum pipe_driver_query_result_type result_type;
1269    unsigned group_id;
1270    unsigned flags;
1271 };
1272
1273 struct pipe_driver_query_group_info
1274 {
1275    const char *name;
1276    unsigned max_active_queries;
1277    unsigned num_queries;
1278 };
1279
1280 enum pipe_fd_type
1281 {
1282    PIPE_FD_TYPE_NATIVE_SYNC,
1283    PIPE_FD_TYPE_SYNCOBJ,
1284 };
1285
1286 /**
1287  * counter type and counter data type enums used by INTEL_performance_query
1288  * APIs in gallium drivers.
1289  */
1290 enum pipe_perf_counter_type
1291 {
1292    PIPE_PERF_COUNTER_TYPE_EVENT,
1293    PIPE_PERF_COUNTER_TYPE_DURATION_NORM,
1294    PIPE_PERF_COUNTER_TYPE_DURATION_RAW,
1295    PIPE_PERF_COUNTER_TYPE_THROUGHPUT,
1296    PIPE_PERF_COUNTER_TYPE_RAW,
1297    PIPE_PERF_COUNTER_TYPE_TIMESTAMP,
1298 };
1299
1300 enum pipe_perf_counter_data_type
1301 {
1302    PIPE_PERF_COUNTER_DATA_TYPE_BOOL32,
1303    PIPE_PERF_COUNTER_DATA_TYPE_UINT32,
1304    PIPE_PERF_COUNTER_DATA_TYPE_UINT64,
1305    PIPE_PERF_COUNTER_DATA_TYPE_FLOAT,
1306    PIPE_PERF_COUNTER_DATA_TYPE_DOUBLE,
1307 };
1308
1309 #define PIPE_UUID_SIZE 16
1310
1311 #ifdef __cplusplus
1312 }
1313 #endif
1314
1315 #endif