gallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*
[mesa.git] / src / gallium / include / pipe / p_shader_tokens.h
1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * Copyright 2009-2010 VMware, Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
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12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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27 **************************************************************************/
28
29 #ifndef P_SHADER_TOKENS_H
30 #define P_SHADER_TOKENS_H
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36
37 struct tgsi_header
38 {
39 unsigned HeaderSize : 8;
40 unsigned BodySize : 24;
41 };
42
43 struct tgsi_processor
44 {
45 unsigned Processor : 4; /* PIPE_SHADER_ */
46 unsigned Padding : 28;
47 };
48
49 enum tgsi_token_type {
50 TGSI_TOKEN_TYPE_DECLARATION,
51 TGSI_TOKEN_TYPE_IMMEDIATE,
52 TGSI_TOKEN_TYPE_INSTRUCTION,
53 TGSI_TOKEN_TYPE_PROPERTY,
54 };
55
56 struct tgsi_token
57 {
58 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_x */
59 unsigned NrTokens : 8; /**< UINT */
60 unsigned Padding : 20;
61 };
62
63 enum tgsi_file_type {
64 TGSI_FILE_NULL,
65 TGSI_FILE_CONSTANT,
66 TGSI_FILE_INPUT,
67 TGSI_FILE_OUTPUT,
68 TGSI_FILE_TEMPORARY,
69 TGSI_FILE_SAMPLER,
70 TGSI_FILE_ADDRESS,
71 TGSI_FILE_IMMEDIATE,
72 TGSI_FILE_PREDICATE,
73 TGSI_FILE_SYSTEM_VALUE,
74 TGSI_FILE_IMAGE,
75 TGSI_FILE_SAMPLER_VIEW,
76 TGSI_FILE_BUFFER,
77 TGSI_FILE_MEMORY,
78 TGSI_FILE_COUNT, /**< how many TGSI_FILE_ types */
79 };
80
81
82 #define TGSI_WRITEMASK_NONE 0x00
83 #define TGSI_WRITEMASK_X 0x01
84 #define TGSI_WRITEMASK_Y 0x02
85 #define TGSI_WRITEMASK_XY 0x03
86 #define TGSI_WRITEMASK_Z 0x04
87 #define TGSI_WRITEMASK_XZ 0x05
88 #define TGSI_WRITEMASK_YZ 0x06
89 #define TGSI_WRITEMASK_XYZ 0x07
90 #define TGSI_WRITEMASK_W 0x08
91 #define TGSI_WRITEMASK_XW 0x09
92 #define TGSI_WRITEMASK_YW 0x0A
93 #define TGSI_WRITEMASK_XYW 0x0B
94 #define TGSI_WRITEMASK_ZW 0x0C
95 #define TGSI_WRITEMASK_XZW 0x0D
96 #define TGSI_WRITEMASK_YZW 0x0E
97 #define TGSI_WRITEMASK_XYZW 0x0F
98
99 enum tgsi_interpolate_mode {
100 TGSI_INTERPOLATE_CONSTANT,
101 TGSI_INTERPOLATE_LINEAR,
102 TGSI_INTERPOLATE_PERSPECTIVE,
103 TGSI_INTERPOLATE_COLOR, /* special color case for smooth/flat */
104 TGSI_INTERPOLATE_COUNT,
105 };
106
107 enum tgsi_interpolate_loc {
108 TGSI_INTERPOLATE_LOC_CENTER,
109 TGSI_INTERPOLATE_LOC_CENTROID,
110 TGSI_INTERPOLATE_LOC_SAMPLE,
111 TGSI_INTERPOLATE_LOC_COUNT,
112 };
113
114 #define TGSI_CYLINDRICAL_WRAP_X (1 << 0)
115 #define TGSI_CYLINDRICAL_WRAP_Y (1 << 1)
116 #define TGSI_CYLINDRICAL_WRAP_Z (1 << 2)
117 #define TGSI_CYLINDRICAL_WRAP_W (1 << 3)
118
119 enum tgsi_memory_type {
120 TGSI_MEMORY_TYPE_GLOBAL, /* OpenCL global */
121 TGSI_MEMORY_TYPE_SHARED, /* OpenCL local / GLSL shared */
122 TGSI_MEMORY_TYPE_PRIVATE, /* OpenCL private */
123 TGSI_MEMORY_TYPE_INPUT, /* OpenCL kernel input params */
124 TGSI_MEMORY_TYPE_COUNT,
125 };
126
127 struct tgsi_declaration
128 {
129 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_DECLARATION */
130 unsigned NrTokens : 8; /**< UINT */
131 unsigned File : 4; /**< one of TGSI_FILE_x */
132 unsigned UsageMask : 4; /**< bitmask of TGSI_WRITEMASK_x flags */
133 unsigned Dimension : 1; /**< any extra dimension info? */
134 unsigned Semantic : 1; /**< BOOL, any semantic info? */
135 unsigned Interpolate : 1; /**< any interpolation info? */
136 unsigned Invariant : 1; /**< invariant optimization? */
137 unsigned Local : 1; /**< optimize as subroutine local variable? */
138 unsigned Array : 1; /**< extra array info? */
139 unsigned Atomic : 1; /**< atomic only? for TGSI_FILE_BUFFER */
140 unsigned MemType : 2; /**< TGSI_MEMORY_TYPE_x for TGSI_FILE_MEMORY */
141 unsigned Padding : 3;
142 };
143
144 struct tgsi_declaration_range
145 {
146 unsigned First : 16; /**< UINT */
147 unsigned Last : 16; /**< UINT */
148 };
149
150 struct tgsi_declaration_dimension
151 {
152 unsigned Index2D:16; /**< UINT */
153 unsigned Padding:16;
154 };
155
156 struct tgsi_declaration_interp
157 {
158 unsigned Interpolate : 4; /**< one of TGSI_INTERPOLATE_x */
159 unsigned Location : 2; /**< one of TGSI_INTERPOLATE_LOC_x */
160 unsigned CylindricalWrap:4; /**< TGSI_CYLINDRICAL_WRAP_x flags */
161 unsigned Padding : 22;
162 };
163
164 enum tgsi_semantic {
165 TGSI_SEMANTIC_POSITION,
166 TGSI_SEMANTIC_COLOR,
167 TGSI_SEMANTIC_BCOLOR, /**< back-face color */
168 TGSI_SEMANTIC_FOG,
169 TGSI_SEMANTIC_PSIZE,
170 TGSI_SEMANTIC_GENERIC,
171 TGSI_SEMANTIC_NORMAL,
172 TGSI_SEMANTIC_FACE,
173 TGSI_SEMANTIC_EDGEFLAG,
174 TGSI_SEMANTIC_PRIMID,
175 TGSI_SEMANTIC_INSTANCEID, /**< doesn't include start_instance */
176 TGSI_SEMANTIC_VERTEXID,
177 TGSI_SEMANTIC_STENCIL,
178 TGSI_SEMANTIC_CLIPDIST,
179 TGSI_SEMANTIC_CLIPVERTEX,
180 TGSI_SEMANTIC_GRID_SIZE, /**< grid size in blocks */
181 TGSI_SEMANTIC_BLOCK_ID, /**< id of the current block */
182 TGSI_SEMANTIC_BLOCK_SIZE, /**< block size in threads */
183 TGSI_SEMANTIC_THREAD_ID, /**< block-relative id of the current thread */
184 TGSI_SEMANTIC_TEXCOORD, /**< texture or sprite coordinates */
185 TGSI_SEMANTIC_PCOORD, /**< point sprite coordinate */
186 TGSI_SEMANTIC_VIEWPORT_INDEX, /**< viewport index */
187 TGSI_SEMANTIC_LAYER, /**< layer (rendertarget index) */
188 TGSI_SEMANTIC_CULLDIST,
189 TGSI_SEMANTIC_SAMPLEID,
190 TGSI_SEMANTIC_SAMPLEPOS,
191 TGSI_SEMANTIC_SAMPLEMASK,
192 TGSI_SEMANTIC_INVOCATIONID,
193 TGSI_SEMANTIC_VERTEXID_NOBASE,
194 TGSI_SEMANTIC_BASEVERTEX,
195 TGSI_SEMANTIC_PATCH, /**< generic per-patch semantic */
196 TGSI_SEMANTIC_TESSCOORD, /**< coordinate being processed by tess */
197 TGSI_SEMANTIC_TESSOUTER, /**< outer tessellation levels */
198 TGSI_SEMANTIC_TESSINNER, /**< inner tessellation levels */
199 TGSI_SEMANTIC_VERTICESIN, /**< number of input vertices */
200 TGSI_SEMANTIC_HELPER_INVOCATION, /**< current invocation is helper */
201 TGSI_SEMANTIC_BASEINSTANCE,
202 TGSI_SEMANTIC_DRAWID,
203 TGSI_SEMANTIC_COUNT, /**< number of semantic values */
204 };
205
206 struct tgsi_declaration_semantic
207 {
208 unsigned Name : 8; /**< one of TGSI_SEMANTIC_x */
209 unsigned Index : 16; /**< UINT */
210 unsigned Padding : 8;
211 };
212
213 struct tgsi_declaration_image {
214 unsigned Resource : 8; /**< one of TGSI_TEXTURE_ */
215 unsigned Raw : 1;
216 unsigned Writable : 1;
217 unsigned Format : 10; /**< one of PIPE_FORMAT_ */
218 unsigned Padding : 12;
219 };
220
221 enum tgsi_return_type {
222 TGSI_RETURN_TYPE_UNORM = 0,
223 TGSI_RETURN_TYPE_SNORM,
224 TGSI_RETURN_TYPE_SINT,
225 TGSI_RETURN_TYPE_UINT,
226 TGSI_RETURN_TYPE_FLOAT,
227 TGSI_RETURN_TYPE_COUNT
228 };
229
230 struct tgsi_declaration_sampler_view {
231 unsigned Resource : 8; /**< one of TGSI_TEXTURE_ */
232 unsigned ReturnTypeX : 6; /**< one of enum tgsi_return_type */
233 unsigned ReturnTypeY : 6; /**< one of enum tgsi_return_type */
234 unsigned ReturnTypeZ : 6; /**< one of enum tgsi_return_type */
235 unsigned ReturnTypeW : 6; /**< one of enum tgsi_return_type */
236 };
237
238 struct tgsi_declaration_array {
239 unsigned ArrayID : 10;
240 unsigned Padding : 22;
241 };
242
243 enum tgsi_imm_type {
244 TGSI_IMM_FLOAT32,
245 TGSI_IMM_UINT32,
246 TGSI_IMM_INT32,
247 TGSI_IMM_FLOAT64,
248 };
249
250 struct tgsi_immediate
251 {
252 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_IMMEDIATE */
253 unsigned NrTokens : 14; /**< UINT */
254 unsigned DataType : 4; /**< one of TGSI_IMM_x */
255 unsigned Padding : 10;
256 };
257
258 union tgsi_immediate_data
259 {
260 float Float;
261 unsigned Uint;
262 int Int;
263 };
264
265 enum tgsi_property_name {
266 TGSI_PROPERTY_GS_INPUT_PRIM,
267 TGSI_PROPERTY_GS_OUTPUT_PRIM,
268 TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES,
269 TGSI_PROPERTY_FS_COORD_ORIGIN,
270 TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
271 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS,
272 TGSI_PROPERTY_FS_DEPTH_LAYOUT,
273 TGSI_PROPERTY_VS_PROHIBIT_UCPS,
274 TGSI_PROPERTY_GS_INVOCATIONS,
275 TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION,
276 TGSI_PROPERTY_TCS_VERTICES_OUT,
277 TGSI_PROPERTY_TES_PRIM_MODE,
278 TGSI_PROPERTY_TES_SPACING,
279 TGSI_PROPERTY_TES_VERTEX_ORDER_CW,
280 TGSI_PROPERTY_TES_POINT_MODE,
281 TGSI_PROPERTY_NUM_CLIPDIST_ENABLED,
282 TGSI_PROPERTY_NUM_CULLDIST_ENABLED,
283 TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL,
284 TGSI_PROPERTY_NEXT_SHADER,
285 TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
286 TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
287 TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
288 TGSI_PROPERTY_COUNT,
289 };
290
291 struct tgsi_property {
292 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_PROPERTY */
293 unsigned NrTokens : 8; /**< UINT */
294 unsigned PropertyName : 8; /**< one of TGSI_PROPERTY */
295 unsigned Padding : 12;
296 };
297
298 enum tgsi_fs_coord_origin {
299 TGSI_FS_COORD_ORIGIN_UPPER_LEFT,
300 TGSI_FS_COORD_ORIGIN_LOWER_LEFT,
301 };
302
303 enum tgsi_fs_coord_pixcenter {
304 TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
305 TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
306 };
307
308 enum tgsi_fs_depth_layout {
309 TGSI_FS_DEPTH_LAYOUT_NONE,
310 TGSI_FS_DEPTH_LAYOUT_ANY,
311 TGSI_FS_DEPTH_LAYOUT_GREATER,
312 TGSI_FS_DEPTH_LAYOUT_LESS,
313 TGSI_FS_DEPTH_LAYOUT_UNCHANGED,
314 };
315
316 struct tgsi_property_data {
317 unsigned Data;
318 };
319
320 /* TGSI opcodes.
321 *
322 * For more information on semantics of opcodes and
323 * which APIs are known to use which opcodes, see
324 * gallium/docs/source/tgsi.rst
325 */
326 #define TGSI_OPCODE_ARL 0
327 #define TGSI_OPCODE_MOV 1
328 #define TGSI_OPCODE_LIT 2
329 #define TGSI_OPCODE_RCP 3
330 #define TGSI_OPCODE_RSQ 4
331 #define TGSI_OPCODE_EXP 5
332 #define TGSI_OPCODE_LOG 6
333 #define TGSI_OPCODE_MUL 7
334 #define TGSI_OPCODE_ADD 8
335 #define TGSI_OPCODE_DP3 9
336 #define TGSI_OPCODE_DP4 10
337 #define TGSI_OPCODE_DST 11
338 #define TGSI_OPCODE_MIN 12
339 #define TGSI_OPCODE_MAX 13
340 #define TGSI_OPCODE_SLT 14
341 #define TGSI_OPCODE_SGE 15
342 #define TGSI_OPCODE_MAD 16
343 #define TGSI_OPCODE_SUB 17
344 #define TGSI_OPCODE_LRP 18
345 #define TGSI_OPCODE_FMA 19
346 #define TGSI_OPCODE_SQRT 20
347 #define TGSI_OPCODE_DP2A 21
348 /* gap */
349 #define TGSI_OPCODE_FRC 24
350 #define TGSI_OPCODE_CLAMP 25
351 #define TGSI_OPCODE_FLR 26
352 #define TGSI_OPCODE_ROUND 27
353 #define TGSI_OPCODE_EX2 28
354 #define TGSI_OPCODE_LG2 29
355 #define TGSI_OPCODE_POW 30
356 #define TGSI_OPCODE_XPD 31
357 /* gap */
358 #define TGSI_OPCODE_ABS 33
359 /* gap */
360 #define TGSI_OPCODE_DPH 35
361 #define TGSI_OPCODE_COS 36
362 #define TGSI_OPCODE_DDX 37
363 #define TGSI_OPCODE_DDY 38
364 #define TGSI_OPCODE_KILL 39 /* unconditional */
365 #define TGSI_OPCODE_PK2H 40
366 #define TGSI_OPCODE_PK2US 41
367 #define TGSI_OPCODE_PK4B 42
368 #define TGSI_OPCODE_PK4UB 43
369 /* gap */
370 #define TGSI_OPCODE_SEQ 45
371 /* gap */
372 #define TGSI_OPCODE_SGT 47
373 #define TGSI_OPCODE_SIN 48
374 #define TGSI_OPCODE_SLE 49
375 #define TGSI_OPCODE_SNE 50
376 /* gap */
377 #define TGSI_OPCODE_TEX 52
378 #define TGSI_OPCODE_TXD 53
379 #define TGSI_OPCODE_TXP 54
380 #define TGSI_OPCODE_UP2H 55
381 #define TGSI_OPCODE_UP2US 56
382 #define TGSI_OPCODE_UP4B 57
383 #define TGSI_OPCODE_UP4UB 58
384 /* gap */
385 #define TGSI_OPCODE_ARR 61
386 /* gap */
387 #define TGSI_OPCODE_CAL 63
388 #define TGSI_OPCODE_RET 64
389 #define TGSI_OPCODE_SSG 65 /* SGN */
390 #define TGSI_OPCODE_CMP 66
391 #define TGSI_OPCODE_SCS 67
392 #define TGSI_OPCODE_TXB 68
393 /* gap */
394 #define TGSI_OPCODE_DIV 70
395 #define TGSI_OPCODE_DP2 71
396 #define TGSI_OPCODE_TXL 72
397 #define TGSI_OPCODE_BRK 73
398 #define TGSI_OPCODE_IF 74
399 #define TGSI_OPCODE_UIF 75
400 #define TGSI_OPCODE_ELSE 77
401 #define TGSI_OPCODE_ENDIF 78
402
403 #define TGSI_OPCODE_DDX_FINE 79
404 #define TGSI_OPCODE_DDY_FINE 80
405
406 #define TGSI_OPCODE_PUSHA 81
407 #define TGSI_OPCODE_POPA 82
408 #define TGSI_OPCODE_CEIL 83
409 #define TGSI_OPCODE_I2F 84
410 #define TGSI_OPCODE_NOT 85
411 #define TGSI_OPCODE_TRUNC 86
412 #define TGSI_OPCODE_SHL 87
413 /* gap */
414 #define TGSI_OPCODE_AND 89
415 #define TGSI_OPCODE_OR 90
416 #define TGSI_OPCODE_MOD 91
417 #define TGSI_OPCODE_XOR 92
418 #define TGSI_OPCODE_SAD 93
419 #define TGSI_OPCODE_TXF 94
420 #define TGSI_OPCODE_TXQ 95
421 #define TGSI_OPCODE_CONT 96
422 #define TGSI_OPCODE_EMIT 97
423 #define TGSI_OPCODE_ENDPRIM 98
424 #define TGSI_OPCODE_BGNLOOP 99
425 #define TGSI_OPCODE_BGNSUB 100
426 #define TGSI_OPCODE_ENDLOOP 101
427 #define TGSI_OPCODE_ENDSUB 102
428 #define TGSI_OPCODE_TXQ_LZ 103 /* TXQ for mipmap level 0 */
429 #define TGSI_OPCODE_TXQS 104
430 #define TGSI_OPCODE_RESQ 105
431 /* gap */
432 #define TGSI_OPCODE_NOP 107
433
434 #define TGSI_OPCODE_FSEQ 108
435 #define TGSI_OPCODE_FSGE 109
436 #define TGSI_OPCODE_FSLT 110
437 #define TGSI_OPCODE_FSNE 111
438
439 #define TGSI_OPCODE_MEMBAR 112
440 #define TGSI_OPCODE_CALLNZ 113
441 /* gap */
442 #define TGSI_OPCODE_BREAKC 115
443 #define TGSI_OPCODE_KILL_IF 116 /* conditional kill */
444 #define TGSI_OPCODE_END 117 /* aka HALT */
445 #define TGSI_OPCODE_DFMA 118
446 #define TGSI_OPCODE_F2I 119
447 #define TGSI_OPCODE_IDIV 120
448 #define TGSI_OPCODE_IMAX 121
449 #define TGSI_OPCODE_IMIN 122
450 #define TGSI_OPCODE_INEG 123
451 #define TGSI_OPCODE_ISGE 124
452 #define TGSI_OPCODE_ISHR 125
453 #define TGSI_OPCODE_ISLT 126
454 #define TGSI_OPCODE_F2U 127
455 #define TGSI_OPCODE_U2F 128
456 #define TGSI_OPCODE_UADD 129
457 #define TGSI_OPCODE_UDIV 130
458 #define TGSI_OPCODE_UMAD 131
459 #define TGSI_OPCODE_UMAX 132
460 #define TGSI_OPCODE_UMIN 133
461 #define TGSI_OPCODE_UMOD 134
462 #define TGSI_OPCODE_UMUL 135
463 #define TGSI_OPCODE_USEQ 136
464 #define TGSI_OPCODE_USGE 137
465 #define TGSI_OPCODE_USHR 138
466 #define TGSI_OPCODE_USLT 139
467 #define TGSI_OPCODE_USNE 140
468 #define TGSI_OPCODE_SWITCH 141
469 #define TGSI_OPCODE_CASE 142
470 #define TGSI_OPCODE_DEFAULT 143
471 #define TGSI_OPCODE_ENDSWITCH 144
472
473 /* resource related opcodes */
474 #define TGSI_OPCODE_SAMPLE 145
475 #define TGSI_OPCODE_SAMPLE_I 146
476 #define TGSI_OPCODE_SAMPLE_I_MS 147
477 #define TGSI_OPCODE_SAMPLE_B 148
478 #define TGSI_OPCODE_SAMPLE_C 149
479 #define TGSI_OPCODE_SAMPLE_C_LZ 150
480 #define TGSI_OPCODE_SAMPLE_D 151
481 #define TGSI_OPCODE_SAMPLE_L 152
482 #define TGSI_OPCODE_GATHER4 153
483 #define TGSI_OPCODE_SVIEWINFO 154
484 #define TGSI_OPCODE_SAMPLE_POS 155
485 #define TGSI_OPCODE_SAMPLE_INFO 156
486
487 #define TGSI_OPCODE_UARL 157
488 #define TGSI_OPCODE_UCMP 158
489 #define TGSI_OPCODE_IABS 159
490 #define TGSI_OPCODE_ISSG 160
491
492 #define TGSI_OPCODE_LOAD 161
493 #define TGSI_OPCODE_STORE 162
494
495 #define TGSI_OPCODE_MFENCE 163
496 #define TGSI_OPCODE_LFENCE 164
497 #define TGSI_OPCODE_SFENCE 165
498 #define TGSI_OPCODE_BARRIER 166
499
500 #define TGSI_OPCODE_ATOMUADD 167
501 #define TGSI_OPCODE_ATOMXCHG 168
502 #define TGSI_OPCODE_ATOMCAS 169
503 #define TGSI_OPCODE_ATOMAND 170
504 #define TGSI_OPCODE_ATOMOR 171
505 #define TGSI_OPCODE_ATOMXOR 172
506 #define TGSI_OPCODE_ATOMUMIN 173
507 #define TGSI_OPCODE_ATOMUMAX 174
508 #define TGSI_OPCODE_ATOMIMIN 175
509 #define TGSI_OPCODE_ATOMIMAX 176
510
511 /* to be used for shadow cube map compares */
512 #define TGSI_OPCODE_TEX2 177
513 #define TGSI_OPCODE_TXB2 178
514 #define TGSI_OPCODE_TXL2 179
515
516 #define TGSI_OPCODE_IMUL_HI 180
517 #define TGSI_OPCODE_UMUL_HI 181
518
519 #define TGSI_OPCODE_TG4 182
520
521 #define TGSI_OPCODE_LODQ 183
522
523 #define TGSI_OPCODE_IBFE 184
524 #define TGSI_OPCODE_UBFE 185
525 #define TGSI_OPCODE_BFI 186
526 #define TGSI_OPCODE_BREV 187
527 #define TGSI_OPCODE_POPC 188
528 #define TGSI_OPCODE_LSB 189
529 #define TGSI_OPCODE_IMSB 190
530 #define TGSI_OPCODE_UMSB 191
531
532 #define TGSI_OPCODE_INTERP_CENTROID 192
533 #define TGSI_OPCODE_INTERP_SAMPLE 193
534 #define TGSI_OPCODE_INTERP_OFFSET 194
535
536 /* sm5 marked opcodes are supported in D3D11 optionally - also DMOV, DMOVC */
537 #define TGSI_OPCODE_F2D 195 /* SM5 */
538 #define TGSI_OPCODE_D2F 196
539 #define TGSI_OPCODE_DABS 197
540 #define TGSI_OPCODE_DNEG 198 /* SM5 */
541 #define TGSI_OPCODE_DADD 199 /* SM5 */
542 #define TGSI_OPCODE_DMUL 200 /* SM5 */
543 #define TGSI_OPCODE_DMAX 201 /* SM5 */
544 #define TGSI_OPCODE_DMIN 202 /* SM5 */
545 #define TGSI_OPCODE_DSLT 203 /* SM5 */
546 #define TGSI_OPCODE_DSGE 204 /* SM5 */
547 #define TGSI_OPCODE_DSEQ 205 /* SM5 */
548 #define TGSI_OPCODE_DSNE 206 /* SM5 */
549 #define TGSI_OPCODE_DRCP 207 /* eg, cayman */
550 #define TGSI_OPCODE_DSQRT 208 /* eg, cayman also has DRSQ */
551 #define TGSI_OPCODE_DMAD 209
552 #define TGSI_OPCODE_DFRAC 210 /* eg, cayman */
553 #define TGSI_OPCODE_DLDEXP 211 /* eg, cayman */
554 #define TGSI_OPCODE_DFRACEXP 212 /* eg, cayman */
555 #define TGSI_OPCODE_D2I 213
556 #define TGSI_OPCODE_I2D 214
557 #define TGSI_OPCODE_D2U 215
558 #define TGSI_OPCODE_U2D 216
559 #define TGSI_OPCODE_DRSQ 217 /* eg, cayman also has DRSQ */
560 #define TGSI_OPCODE_DTRUNC 218 /* nvc0 */
561 #define TGSI_OPCODE_DCEIL 219 /* nvc0 */
562 #define TGSI_OPCODE_DFLR 220 /* nvc0 */
563 #define TGSI_OPCODE_DROUND 221 /* nvc0 */
564 #define TGSI_OPCODE_DSSG 222
565 #define TGSI_OPCODE_LAST 223
566
567 /**
568 * Opcode is the operation code to execute. A given operation defines the
569 * semantics how the source registers (if any) are interpreted and what is
570 * written to the destination registers (if any) as a result of execution.
571 *
572 * NumDstRegs and NumSrcRegs is the number of destination and source registers,
573 * respectively. For a given operation code, those numbers are fixed and are
574 * present here only for convenience.
575 *
576 * If Predicate is TRUE, tgsi_instruction_predicate token immediately follows.
577 *
578 * Saturate controls how are final results in destination registers modified.
579 */
580
581 struct tgsi_instruction
582 {
583 unsigned Type : 4; /* TGSI_TOKEN_TYPE_INSTRUCTION */
584 unsigned NrTokens : 8; /* UINT */
585 unsigned Opcode : 8; /* TGSI_OPCODE_ */
586 unsigned Saturate : 1; /* BOOL */
587 unsigned NumDstRegs : 2; /* UINT */
588 unsigned NumSrcRegs : 4; /* UINT */
589 unsigned Predicate : 1; /* BOOL */
590 unsigned Label : 1;
591 unsigned Texture : 1;
592 unsigned Memory : 1;
593 unsigned Padding : 1;
594 };
595
596 /*
597 * If tgsi_instruction::Label is TRUE, tgsi_instruction_label follows.
598 *
599 * If tgsi_instruction::Texture is TRUE, tgsi_instruction_texture follows.
600 * if texture instruction has a number of offsets,
601 * then tgsi_instruction::Texture::NumOffset of tgsi_texture_offset follow.
602 *
603 * Then, tgsi_instruction::NumDstRegs of tgsi_dst_register follow.
604 *
605 * Then, tgsi_instruction::NumSrcRegs of tgsi_src_register follow.
606 *
607 * tgsi_instruction::NrTokens contains the total number of words that make the
608 * instruction, including the instruction word.
609 */
610
611 enum tgsi_swizzle {
612 TGSI_SWIZZLE_X,
613 TGSI_SWIZZLE_Y,
614 TGSI_SWIZZLE_Z,
615 TGSI_SWIZZLE_W,
616 };
617
618 struct tgsi_instruction_label
619 {
620 unsigned Label : 24; /* UINT */
621 unsigned Padding : 8;
622 };
623
624 enum tgsi_texture_type {
625 TGSI_TEXTURE_BUFFER,
626 TGSI_TEXTURE_1D,
627 TGSI_TEXTURE_2D,
628 TGSI_TEXTURE_3D,
629 TGSI_TEXTURE_CUBE,
630 TGSI_TEXTURE_RECT,
631 TGSI_TEXTURE_SHADOW1D,
632 TGSI_TEXTURE_SHADOW2D,
633 TGSI_TEXTURE_SHADOWRECT,
634 TGSI_TEXTURE_1D_ARRAY,
635 TGSI_TEXTURE_2D_ARRAY,
636 TGSI_TEXTURE_SHADOW1D_ARRAY,
637 TGSI_TEXTURE_SHADOW2D_ARRAY,
638 TGSI_TEXTURE_SHADOWCUBE,
639 TGSI_TEXTURE_2D_MSAA,
640 TGSI_TEXTURE_2D_ARRAY_MSAA,
641 TGSI_TEXTURE_CUBE_ARRAY,
642 TGSI_TEXTURE_SHADOWCUBE_ARRAY,
643 TGSI_TEXTURE_UNKNOWN,
644 TGSI_TEXTURE_COUNT,
645 };
646
647 struct tgsi_instruction_texture
648 {
649 unsigned Texture : 8; /* TGSI_TEXTURE_ */
650 unsigned NumOffsets : 4;
651 unsigned Padding : 20;
652 };
653
654 /* for texture offsets in GLSL and DirectX.
655 * Generally these always come from TGSI_FILE_IMMEDIATE,
656 * however DX11 appears to have the capability to do
657 * non-constant texture offsets.
658 */
659 struct tgsi_texture_offset
660 {
661 int Index : 16;
662 unsigned File : 4; /**< one of TGSI_FILE_x */
663 unsigned SwizzleX : 2; /* TGSI_SWIZZLE_x */
664 unsigned SwizzleY : 2; /* TGSI_SWIZZLE_x */
665 unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_x */
666 unsigned Padding : 6;
667 };
668
669 /*
670 * For SM3, the following constraint applies.
671 * - Swizzle is either set to identity or replicate.
672 */
673 struct tgsi_instruction_predicate
674 {
675 int Index : 16; /* SINT */
676 unsigned SwizzleX : 2; /* TGSI_SWIZZLE_x */
677 unsigned SwizzleY : 2; /* TGSI_SWIZZLE_x */
678 unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_x */
679 unsigned SwizzleW : 2; /* TGSI_SWIZZLE_x */
680 unsigned Negate : 1; /* BOOL */
681 unsigned Padding : 7;
682 };
683
684 /**
685 * File specifies the register array to access.
686 *
687 * Index specifies the element number of a register in the register file.
688 *
689 * If Indirect is TRUE, Index should be offset by the X component of the indirect
690 * register that follows. The register can be now fetched into local storage
691 * for further processing.
692 *
693 * If Negate is TRUE, all components of the fetched register are negated.
694 *
695 * The fetched register components are swizzled according to SwizzleX, SwizzleY,
696 * SwizzleZ and SwizzleW.
697 *
698 */
699
700 struct tgsi_src_register
701 {
702 unsigned File : 4; /* TGSI_FILE_ */
703 unsigned Indirect : 1; /* BOOL */
704 unsigned Dimension : 1; /* BOOL */
705 int Index : 16; /* SINT */
706 unsigned SwizzleX : 2; /* TGSI_SWIZZLE_ */
707 unsigned SwizzleY : 2; /* TGSI_SWIZZLE_ */
708 unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_ */
709 unsigned SwizzleW : 2; /* TGSI_SWIZZLE_ */
710 unsigned Absolute : 1; /* BOOL */
711 unsigned Negate : 1; /* BOOL */
712 };
713
714 /**
715 * If tgsi_src_register::Indirect is TRUE, tgsi_ind_register follows.
716 *
717 * File, Index and Swizzle are handled the same as in tgsi_src_register.
718 *
719 * If ArrayID is zero the whole register file might be indirectly addressed,
720 * if not only the Declaration with this ArrayID is accessed by this operand.
721 *
722 */
723
724 struct tgsi_ind_register
725 {
726 unsigned File : 4; /* TGSI_FILE_ */
727 int Index : 16; /* SINT */
728 unsigned Swizzle : 2; /* TGSI_SWIZZLE_ */
729 unsigned ArrayID : 10; /* UINT */
730 };
731
732 /**
733 * If tgsi_src_register::Dimension is TRUE, tgsi_dimension follows.
734 */
735
736 struct tgsi_dimension
737 {
738 unsigned Indirect : 1; /* BOOL */
739 unsigned Dimension : 1; /* BOOL */
740 unsigned Padding : 14;
741 int Index : 16; /* SINT */
742 };
743
744 struct tgsi_dst_register
745 {
746 unsigned File : 4; /* TGSI_FILE_ */
747 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
748 unsigned Indirect : 1; /* BOOL */
749 unsigned Dimension : 1; /* BOOL */
750 int Index : 16; /* SINT */
751 unsigned Padding : 6;
752 };
753
754 #define TGSI_MEMORY_COHERENT (1 << 0)
755 #define TGSI_MEMORY_RESTRICT (1 << 1)
756 #define TGSI_MEMORY_VOLATILE (1 << 2)
757
758 /**
759 * Specifies the type of memory access to do for the LOAD/STORE instruction.
760 */
761 struct tgsi_instruction_memory
762 {
763 unsigned Qualifier : 3; /* TGSI_MEMORY_ */
764 unsigned Texture : 8; /* only for images: TGSI_TEXTURE_ */
765 unsigned Format : 10; /* only for images: PIPE_FORMAT_ */
766 unsigned Padding : 11;
767 };
768
769 #define TGSI_MEMBAR_SHADER_BUFFER (1 << 0)
770 #define TGSI_MEMBAR_ATOMIC_BUFFER (1 << 1)
771 #define TGSI_MEMBAR_SHADER_IMAGE (1 << 2)
772 #define TGSI_MEMBAR_SHARED (1 << 3)
773 #define TGSI_MEMBAR_THREAD_GROUP (1 << 4)
774
775 #ifdef __cplusplus
776 }
777 #endif
778
779 #endif /* P_SHADER_TOKENS_H */