2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "amdgpu_cs.h"
30 #include "util/hash_table.h"
31 #include "util/os_time.h"
32 #include "util/u_hash_table.h"
33 #include "state_tracker/drm_driver.h"
34 #include "drm-uapi/amdgpu_drm.h"
39 #ifndef AMDGPU_VA_RANGE_HIGH
40 #define AMDGPU_VA_RANGE_HIGH 0x2
43 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
44 #define DEBUG_SPARSE_COMMITS 0
46 struct amdgpu_sparse_backing_chunk
{
50 static void amdgpu_bo_unmap(struct pb_buffer
*buf
);
52 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
53 enum radeon_bo_usage usage
)
55 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
56 struct amdgpu_winsys
*ws
= bo
->ws
;
60 if (p_atomic_read(&bo
->num_active_ioctls
))
64 abs_timeout
= os_time_get_absolute_timeout(timeout
);
66 /* Wait if any ioctl is being submitted with this buffer. */
67 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
72 /* We can't use user fences for shared buffers, because user fences
73 * are local to this process only. If we want to wait for all buffer
74 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
76 bool buffer_busy
= true;
79 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
81 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
90 simple_mtx_lock(&ws
->bo_fence_lock
);
92 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
93 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
97 /* Release the idle fences to avoid checking them again later. */
98 for (unsigned i
= 0; i
< idle_fences
; ++i
)
99 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
101 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
102 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
103 bo
->num_fences
-= idle_fences
;
105 buffer_idle
= !bo
->num_fences
;
106 simple_mtx_unlock(&ws
->bo_fence_lock
);
110 bool buffer_idle
= true;
112 simple_mtx_lock(&ws
->bo_fence_lock
);
113 while (bo
->num_fences
&& buffer_idle
) {
114 struct pipe_fence_handle
*fence
= NULL
;
115 bool fence_idle
= false;
117 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
119 /* Wait for the fence. */
120 simple_mtx_unlock(&ws
->bo_fence_lock
);
121 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
125 simple_mtx_lock(&ws
->bo_fence_lock
);
127 /* Release an idle fence to avoid checking it again later, keeping in
128 * mind that the fence array may have been modified by other threads.
130 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
131 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
132 memmove(&bo
->fences
[0], &bo
->fences
[1],
133 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
137 amdgpu_fence_reference(&fence
, NULL
);
139 simple_mtx_unlock(&ws
->bo_fence_lock
);
145 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
146 struct pb_buffer
*buf
)
148 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
151 static enum radeon_bo_flag
amdgpu_bo_get_flags(
152 struct pb_buffer
*buf
)
154 return ((struct amdgpu_winsys_bo
*)buf
)->flags
;
157 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
159 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
160 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
167 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
169 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
170 struct amdgpu_screen_winsys
*sws_iter
;
171 struct amdgpu_winsys
*ws
= bo
->ws
;
173 assert(bo
->bo
&& "must not be called for slab entries");
175 if (!bo
->is_user_ptr
&& bo
->cpu_ptr
) {
177 amdgpu_bo_unmap(&bo
->base
);
179 assert(bo
->is_user_ptr
|| bo
->u
.real
.map_count
== 0);
181 if (ws
->debug_all_bos
) {
182 simple_mtx_lock(&ws
->global_bo_list_lock
);
183 list_del(&bo
->u
.real
.global_list_item
);
185 simple_mtx_unlock(&ws
->global_bo_list_lock
);
188 /* Close all KMS handles retrieved for other DRM file descriptions */
189 simple_mtx_lock(&ws
->sws_list_lock
);
190 for (sws_iter
= ws
->sws_list
; sws_iter
; sws_iter
= sws_iter
->next
) {
191 struct hash_entry
*entry
;
193 if (!sws_iter
->kms_handles
)
196 entry
= _mesa_hash_table_search(sws_iter
->kms_handles
, bo
);
198 struct drm_gem_close args
= { .handle
= (uintptr_t)entry
->data
};
200 drmIoctl(sws_iter
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
201 _mesa_hash_table_remove(sws_iter
->kms_handles
, entry
);
204 simple_mtx_unlock(&ws
->sws_list_lock
);
206 simple_mtx_lock(&ws
->bo_export_table_lock
);
207 _mesa_hash_table_remove_key(ws
->bo_export_table
, bo
->bo
);
208 simple_mtx_unlock(&ws
->bo_export_table_lock
);
210 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM_GTT
) {
211 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
212 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
214 amdgpu_bo_free(bo
->bo
);
216 amdgpu_bo_remove_fences(bo
);
218 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
219 ws
->allocated_vram
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
220 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
221 ws
->allocated_gtt
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
223 simple_mtx_destroy(&bo
->lock
);
227 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
229 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
231 assert(bo
->bo
); /* slab buffers have a separate vtbl */
233 if (bo
->u
.real
.use_reusable_pool
)
234 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
236 amdgpu_bo_destroy(_buf
);
239 static void amdgpu_clean_up_buffer_managers(struct amdgpu_winsys
*ws
)
241 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++)
242 pb_slabs_reclaim(&ws
->bo_slabs
[i
]);
244 pb_cache_release_all_buffers(&ws
->bo_cache
);
247 static bool amdgpu_bo_do_map(struct amdgpu_winsys_bo
*bo
, void **cpu
)
249 assert(!bo
->sparse
&& bo
->bo
&& !bo
->is_user_ptr
);
250 int r
= amdgpu_bo_cpu_map(bo
->bo
, cpu
);
252 /* Clean up buffer managers and try again. */
253 amdgpu_clean_up_buffer_managers(bo
->ws
);
254 r
= amdgpu_bo_cpu_map(bo
->bo
, cpu
);
259 if (p_atomic_inc_return(&bo
->u
.real
.map_count
) == 1) {
260 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
261 bo
->ws
->mapped_vram
+= bo
->base
.size
;
262 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
263 bo
->ws
->mapped_gtt
+= bo
->base
.size
;
264 bo
->ws
->num_mapped_buffers
++;
270 void *amdgpu_bo_map(struct pb_buffer
*buf
,
271 struct radeon_cmdbuf
*rcs
,
272 enum pipe_transfer_usage usage
)
274 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
275 struct amdgpu_winsys_bo
*real
;
276 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
280 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
281 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
282 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
283 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
284 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
287 * Since we are mapping for read, we don't need to wait
288 * if the GPU is using the buffer for read too
289 * (neither one is changing it).
291 * Only check whether the buffer is being used for write. */
292 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
293 RADEON_USAGE_WRITE
)) {
294 cs
->flush_cs(cs
->flush_data
,
295 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
299 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
300 RADEON_USAGE_WRITE
)) {
304 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
305 cs
->flush_cs(cs
->flush_data
,
306 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
310 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
311 RADEON_USAGE_READWRITE
)) {
316 uint64_t time
= os_time_get_nano();
318 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
321 * Since we are mapping for read, we don't need to wait
322 * if the GPU is using the buffer for read too
323 * (neither one is changing it).
325 * Only check whether the buffer is being used for write. */
327 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
328 RADEON_USAGE_WRITE
)) {
329 cs
->flush_cs(cs
->flush_data
,
330 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
332 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
333 if (p_atomic_read(&bo
->num_active_ioctls
))
334 amdgpu_cs_sync_flush(rcs
);
338 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
341 /* Mapping for write. */
343 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
344 cs
->flush_cs(cs
->flush_data
,
345 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
347 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
348 if (p_atomic_read(&bo
->num_active_ioctls
))
349 amdgpu_cs_sync_flush(rcs
);
353 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
354 RADEON_USAGE_READWRITE
);
357 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
361 /* Buffer synchronization has been checked, now actually map the buffer. */
368 real
= bo
->u
.slab
.real
;
369 offset
= bo
->va
- real
->va
;
372 if (usage
& RADEON_TRANSFER_TEMPORARY
) {
373 if (real
->is_user_ptr
) {
376 if (!amdgpu_bo_do_map(real
, &cpu
))
380 cpu
= p_atomic_read(&real
->cpu_ptr
);
382 simple_mtx_lock(&real
->lock
);
383 /* Must re-check due to the possibility of a race. Re-check need not
384 * be atomic thanks to the lock. */
387 if (!amdgpu_bo_do_map(real
, &cpu
)) {
388 simple_mtx_unlock(&real
->lock
);
391 p_atomic_set(&real
->cpu_ptr
, cpu
);
393 simple_mtx_unlock(&real
->lock
);
397 return (uint8_t*)cpu
+ offset
;
400 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
402 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
403 struct amdgpu_winsys_bo
*real
;
410 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
411 assert(real
->u
.real
.map_count
!= 0 && "too many unmaps");
412 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
413 assert(!real
->cpu_ptr
&&
414 "too many unmaps or forgot RADEON_TRANSFER_TEMPORARY flag");
416 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
417 real
->ws
->mapped_vram
-= real
->base
.size
;
418 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
419 real
->ws
->mapped_gtt
-= real
->base
.size
;
420 real
->ws
->num_mapped_buffers
--;
423 amdgpu_bo_cpu_unmap(real
->bo
);
426 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
427 amdgpu_bo_destroy_or_cache
428 /* other functions are never called */
431 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
433 struct amdgpu_winsys
*ws
= bo
->ws
;
437 if (ws
->debug_all_bos
) {
438 simple_mtx_lock(&ws
->global_bo_list_lock
);
439 list_addtail(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
441 simple_mtx_unlock(&ws
->global_bo_list_lock
);
445 static uint64_t amdgpu_get_optimal_vm_alignment(struct amdgpu_winsys
*ws
,
446 uint64_t size
, unsigned alignment
)
448 uint64_t vm_alignment
= alignment
;
450 /* Increase the VM alignment for faster address translation. */
451 if (size
>= ws
->info
.pte_fragment_size
)
452 vm_alignment
= MAX2(vm_alignment
, ws
->info
.pte_fragment_size
);
454 /* Gfx9: Increase the VM alignment to the most significant bit set
455 * in the size for faster address translation.
457 if (ws
->info
.chip_class
>= GFX9
) {
458 unsigned msb
= util_last_bit64(size
); /* 0 = no bit is set */
459 uint64_t msb_alignment
= msb
? 1ull << (msb
- 1) : 0;
461 vm_alignment
= MAX2(vm_alignment
, msb_alignment
);
466 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
469 enum radeon_bo_domain initial_domain
,
473 struct amdgpu_bo_alloc_request request
= {0};
474 amdgpu_bo_handle buf_handle
;
476 struct amdgpu_winsys_bo
*bo
;
477 amdgpu_va_handle va_handle
;
480 /* VRAM or GTT must be specified, but not both at the same time. */
481 assert(util_bitcount(initial_domain
& (RADEON_DOMAIN_VRAM_GTT
|
483 RADEON_DOMAIN_OA
)) == 1);
485 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
491 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
494 request
.alloc_size
= size
;
495 request
.phys_alignment
= alignment
;
497 if (initial_domain
& RADEON_DOMAIN_VRAM
) {
498 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
500 /* Since VRAM and GTT have almost the same performance on APUs, we could
501 * just set GTT. However, in order to decrease GTT(RAM) usage, which is
502 * shared with the OS, allow VRAM placements too. The idea is not to use
503 * VRAM usefully, but to use it so that it's not unused and wasted.
505 if (!ws
->info
.has_dedicated_vram
)
506 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
509 if (initial_domain
& RADEON_DOMAIN_GTT
)
510 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
511 if (initial_domain
& RADEON_DOMAIN_GDS
)
512 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GDS
;
513 if (initial_domain
& RADEON_DOMAIN_OA
)
514 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_OA
;
516 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
517 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
518 if (flags
& RADEON_FLAG_GTT_WC
)
519 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
520 if (ws
->zero_all_vram_allocs
&&
521 (request
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
))
522 request
.flags
|= AMDGPU_GEM_CREATE_VRAM_CLEARED
;
524 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
526 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
527 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
528 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
529 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
533 if (initial_domain
& RADEON_DOMAIN_VRAM_GTT
) {
534 unsigned va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
536 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
538 amdgpu_get_optimal_vm_alignment(ws
, size
, alignment
),
540 (flags
& RADEON_FLAG_32BIT
? AMDGPU_VA_RANGE_32_BIT
: 0) |
541 AMDGPU_VA_RANGE_HIGH
);
545 unsigned vm_flags
= AMDGPU_VM_PAGE_READABLE
|
546 AMDGPU_VM_PAGE_EXECUTABLE
;
548 if (!(flags
& RADEON_FLAG_READ_ONLY
))
549 vm_flags
|= AMDGPU_VM_PAGE_WRITEABLE
;
551 r
= amdgpu_bo_va_op_raw(ws
->dev
, buf_handle
, 0, size
, va
, vm_flags
,
557 simple_mtx_init(&bo
->lock
, mtx_plain
);
558 pipe_reference_init(&bo
->base
.reference
, 1);
559 bo
->base
.alignment
= alignment
;
561 bo
->base
.size
= size
;
562 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
566 bo
->u
.real
.va_handle
= va_handle
;
567 bo
->initial_domain
= initial_domain
;
569 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
571 if (initial_domain
& RADEON_DOMAIN_VRAM
)
572 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
573 else if (initial_domain
& RADEON_DOMAIN_GTT
)
574 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
576 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
578 amdgpu_add_buffer_to_global_list(bo
);
583 amdgpu_va_range_free(va_handle
);
586 amdgpu_bo_free(buf_handle
);
593 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
595 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
597 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
601 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
604 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
606 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
607 bo
= container_of(entry
, bo
, u
.slab
.entry
);
609 return amdgpu_bo_can_reclaim(&bo
->base
);
612 static struct pb_slabs
*get_slabs(struct amdgpu_winsys
*ws
, uint64_t size
)
614 /* Find the correct slab allocator for the given size. */
615 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
616 struct pb_slabs
*slabs
= &ws
->bo_slabs
[i
];
618 if (size
<= 1 << (slabs
->min_order
+ slabs
->num_orders
- 1))
626 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
628 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
632 pb_slab_free(get_slabs(bo
->ws
, bo
->base
.size
), &bo
->u
.slab
.entry
);
635 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
636 amdgpu_bo_slab_destroy
637 /* other functions are never called */
640 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
642 unsigned group_index
)
644 struct amdgpu_winsys
*ws
= priv
;
645 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
646 enum radeon_bo_domain domains
= radeon_domain_from_heap(heap
);
647 enum radeon_bo_flag flags
= radeon_flags_from_heap(heap
);
649 unsigned slab_size
= 0;
654 /* Determine the slab buffer size. */
655 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
656 struct pb_slabs
*slabs
= &ws
->bo_slabs
[i
];
657 unsigned max_entry_size
= 1 << (slabs
->min_order
+ slabs
->num_orders
- 1);
659 if (entry_size
<= max_entry_size
) {
660 /* The slab size is twice the size of the largest possible entry. */
661 slab_size
= max_entry_size
* 2;
663 /* The largest slab should have the same size as the PTE fragment
664 * size to get faster address translation.
666 if (i
== NUM_SLAB_ALLOCATORS
- 1 &&
667 slab_size
< ws
->info
.pte_fragment_size
)
668 slab_size
= ws
->info
.pte_fragment_size
;
672 assert(slab_size
!= 0);
674 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(ws
,
675 slab_size
, slab_size
,
680 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
681 slab
->base
.num_free
= slab
->base
.num_entries
;
682 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
686 list_inithead(&slab
->base
.free
);
688 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
690 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
691 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
693 simple_mtx_init(&bo
->lock
, mtx_plain
);
694 bo
->base
.alignment
= entry_size
;
695 bo
->base
.usage
= slab
->buffer
->base
.usage
;
696 bo
->base
.size
= entry_size
;
697 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
699 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
700 bo
->initial_domain
= domains
;
701 bo
->unique_id
= base_id
+ i
;
702 bo
->u
.slab
.entry
.slab
= &slab
->base
;
703 bo
->u
.slab
.entry
.group_index
= group_index
;
705 if (slab
->buffer
->bo
) {
706 /* The slab is not suballocated. */
707 bo
->u
.slab
.real
= slab
->buffer
;
709 /* The slab is allocated out of a bigger slab. */
710 bo
->u
.slab
.real
= slab
->buffer
->u
.slab
.real
;
711 assert(bo
->u
.slab
.real
->bo
);
714 list_addtail(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
720 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
726 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
728 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
730 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
731 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
732 simple_mtx_destroy(&slab
->entries
[i
].lock
);
736 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
740 #if DEBUG_SPARSE_COMMITS
742 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
744 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
746 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
748 struct amdgpu_sparse_backing
*span_backing
= NULL
;
749 uint32_t span_first_backing_page
= 0;
750 uint32_t span_first_va_page
= 0;
751 uint32_t va_page
= 0;
754 struct amdgpu_sparse_backing
*backing
= 0;
755 uint32_t backing_page
= 0;
757 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
758 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
759 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
763 (backing
!= span_backing
||
764 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
765 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
766 span_first_va_page
, va_page
- 1, span_backing
,
767 span_first_backing_page
,
768 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
773 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
776 if (backing
&& !span_backing
) {
777 span_backing
= backing
;
778 span_first_backing_page
= backing_page
;
779 span_first_va_page
= va_page
;
785 fprintf(stderr
, "Backing:\n");
787 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
788 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
789 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
790 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
796 * Attempt to allocate the given number of backing pages. Fewer pages may be
797 * allocated (depending on the fragmentation of existing backing buffers),
798 * which will be reflected by a change to *pnum_pages.
800 static struct amdgpu_sparse_backing
*
801 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
803 struct amdgpu_sparse_backing
*best_backing
;
805 uint32_t best_num_pages
;
811 /* This is a very simple and inefficient best-fit algorithm. */
812 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
813 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
814 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
815 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
816 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
817 best_backing
= backing
;
819 best_num_pages
= cur_num_pages
;
824 /* Allocate a new backing buffer if necessary. */
826 struct pb_buffer
*buf
;
830 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
834 best_backing
->max_chunks
= 4;
835 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
836 sizeof(*best_backing
->chunks
));
837 if (!best_backing
->chunks
) {
842 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
844 size
= MIN3(bo
->base
.size
/ 16,
846 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
847 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
849 buf
= amdgpu_bo_create(bo
->ws
, size
, RADEON_SPARSE_PAGE_SIZE
,
851 bo
->u
.sparse
.flags
| RADEON_FLAG_NO_SUBALLOC
);
853 FREE(best_backing
->chunks
);
858 /* We might have gotten a bigger buffer than requested via caching. */
859 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
861 best_backing
->bo
= amdgpu_winsys_bo(buf
);
862 best_backing
->num_chunks
= 1;
863 best_backing
->chunks
[0].begin
= 0;
864 best_backing
->chunks
[0].end
= pages
;
866 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
867 bo
->u
.sparse
.num_backing_pages
+= pages
;
870 best_num_pages
= pages
;
873 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
874 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
875 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
877 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
878 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
879 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
880 best_backing
->num_chunks
--;
887 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
888 struct amdgpu_sparse_backing
*backing
)
890 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
892 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
894 simple_mtx_lock(&ws
->bo_fence_lock
);
895 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
896 simple_mtx_unlock(&ws
->bo_fence_lock
);
898 list_del(&backing
->list
);
899 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
900 FREE(backing
->chunks
);
905 * Return a range of pages from the given backing buffer back into the
909 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
910 struct amdgpu_sparse_backing
*backing
,
911 uint32_t start_page
, uint32_t num_pages
)
913 uint32_t end_page
= start_page
+ num_pages
;
915 unsigned high
= backing
->num_chunks
;
917 /* Find the first chunk with begin >= start_page. */
919 unsigned mid
= low
+ (high
- low
) / 2;
921 if (backing
->chunks
[mid
].begin
>= start_page
)
927 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
928 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
930 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
931 backing
->chunks
[low
- 1].end
= end_page
;
933 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
934 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
935 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
936 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
937 backing
->num_chunks
--;
939 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
940 backing
->chunks
[low
].begin
= start_page
;
942 if (backing
->num_chunks
>= backing
->max_chunks
) {
943 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
944 struct amdgpu_sparse_backing_chunk
*new_chunks
=
945 REALLOC(backing
->chunks
,
946 sizeof(*backing
->chunks
) * backing
->max_chunks
,
947 sizeof(*backing
->chunks
) * new_max_chunks
);
951 backing
->max_chunks
= new_max_chunks
;
952 backing
->chunks
= new_chunks
;
955 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
956 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
957 backing
->chunks
[low
].begin
= start_page
;
958 backing
->chunks
[low
].end
= end_page
;
959 backing
->num_chunks
++;
962 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
963 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
964 sparse_free_backing_buffer(bo
, backing
);
969 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
971 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
974 assert(!bo
->bo
&& bo
->sparse
);
976 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
977 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
978 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
980 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
983 while (!list_is_empty(&bo
->u
.sparse
.backing
)) {
984 struct amdgpu_sparse_backing
*dummy
= NULL
;
985 sparse_free_backing_buffer(bo
,
986 container_of(bo
->u
.sparse
.backing
.next
,
990 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
991 FREE(bo
->u
.sparse
.commitments
);
992 simple_mtx_destroy(&bo
->lock
);
996 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
997 amdgpu_bo_sparse_destroy
998 /* other functions are never called */
1001 static struct pb_buffer
*
1002 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
1003 enum radeon_bo_domain domain
,
1004 enum radeon_bo_flag flags
)
1006 struct amdgpu_winsys_bo
*bo
;
1008 uint64_t va_gap_size
;
1011 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
1012 * that exceed this limit. This is not really a restriction: we don't have
1013 * that much virtual address space anyway.
1015 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
1018 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1022 simple_mtx_init(&bo
->lock
, mtx_plain
);
1023 pipe_reference_init(&bo
->base
.reference
, 1);
1024 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
1025 bo
->base
.size
= size
;
1026 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
1028 bo
->initial_domain
= domain
;
1029 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1031 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
1033 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
1034 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
1035 sizeof(*bo
->u
.sparse
.commitments
));
1036 if (!bo
->u
.sparse
.commitments
)
1037 goto error_alloc_commitments
;
1039 list_inithead(&bo
->u
.sparse
.backing
);
1041 /* For simplicity, we always map a multiple of the page size. */
1042 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
1043 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
1044 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1045 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
1046 0, &bo
->va
, &bo
->u
.sparse
.va_handle
,
1047 AMDGPU_VA_RANGE_HIGH
);
1049 goto error_va_alloc
;
1051 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
1052 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
1059 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
1061 FREE(bo
->u
.sparse
.commitments
);
1062 error_alloc_commitments
:
1063 simple_mtx_destroy(&bo
->lock
);
1069 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
1072 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
1073 struct amdgpu_sparse_commitment
*comm
;
1074 uint32_t va_page
, end_va_page
;
1079 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
1080 assert(offset
<= bo
->base
.size
);
1081 assert(size
<= bo
->base
.size
- offset
);
1082 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
1084 comm
= bo
->u
.sparse
.commitments
;
1085 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
1086 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
1088 simple_mtx_lock(&bo
->lock
);
1090 #if DEBUG_SPARSE_COMMITS
1091 sparse_dump(bo
, __func__
);
1095 while (va_page
< end_va_page
) {
1096 uint32_t span_va_page
;
1098 /* Skip pages that are already committed. */
1099 if (comm
[va_page
].backing
) {
1104 /* Determine length of uncommitted span. */
1105 span_va_page
= va_page
;
1106 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
1109 /* Fill the uncommitted span with chunks of backing memory. */
1110 while (span_va_page
< va_page
) {
1111 struct amdgpu_sparse_backing
*backing
;
1112 uint32_t backing_start
, backing_size
;
1114 backing_size
= va_page
- span_va_page
;
1115 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
1121 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
1122 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
1123 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
1124 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
1125 AMDGPU_VM_PAGE_READABLE
|
1126 AMDGPU_VM_PAGE_WRITEABLE
|
1127 AMDGPU_VM_PAGE_EXECUTABLE
,
1128 AMDGPU_VA_OP_REPLACE
);
1130 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
1131 assert(ok
&& "sufficient memory should already be allocated");
1137 while (backing_size
) {
1138 comm
[span_va_page
].backing
= backing
;
1139 comm
[span_va_page
].page
= backing_start
;
1147 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
1148 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
1149 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
1150 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
1156 while (va_page
< end_va_page
) {
1157 struct amdgpu_sparse_backing
*backing
;
1158 uint32_t backing_start
;
1159 uint32_t span_pages
;
1161 /* Skip pages that are already uncommitted. */
1162 if (!comm
[va_page
].backing
) {
1167 /* Group contiguous spans of pages. */
1168 backing
= comm
[va_page
].backing
;
1169 backing_start
= comm
[va_page
].page
;
1170 comm
[va_page
].backing
= NULL
;
1175 while (va_page
< end_va_page
&&
1176 comm
[va_page
].backing
== backing
&&
1177 comm
[va_page
].page
== backing_start
+ span_pages
) {
1178 comm
[va_page
].backing
= NULL
;
1183 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1184 /* Couldn't allocate tracking data structures, so we have to leak */
1185 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1192 simple_mtx_unlock(&bo
->lock
);
1197 static unsigned eg_tile_split(unsigned tile_split
)
1199 switch (tile_split
) {
1200 case 0: tile_split
= 64; break;
1201 case 1: tile_split
= 128; break;
1202 case 2: tile_split
= 256; break;
1203 case 3: tile_split
= 512; break;
1205 case 4: tile_split
= 1024; break;
1206 case 5: tile_split
= 2048; break;
1207 case 6: tile_split
= 4096; break;
1212 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1214 switch (eg_tile_split
) {
1220 case 1024: return 4;
1221 case 2048: return 5;
1222 case 4096: return 6;
1226 #define AMDGPU_TILING_DCC_MAX_COMPRESSED_BLOCK_SIZE_SHIFT 45
1227 #define AMDGPU_TILING_DCC_MAX_COMPRESSED_BLOCK_SIZE_MASK 0x3
1229 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1230 struct radeon_bo_metadata
*md
)
1232 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1233 struct amdgpu_bo_info info
= {0};
1234 uint64_t tiling_flags
;
1237 assert(bo
->bo
&& "must not be called for slab entries");
1239 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1243 tiling_flags
= info
.metadata
.tiling_info
;
1245 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1246 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1248 md
->u
.gfx9
.dcc_offset_256B
= AMDGPU_TILING_GET(tiling_flags
, DCC_OFFSET_256B
);
1249 md
->u
.gfx9
.dcc_pitch_max
= AMDGPU_TILING_GET(tiling_flags
, DCC_PITCH_MAX
);
1250 md
->u
.gfx9
.dcc_independent_64B
= AMDGPU_TILING_GET(tiling_flags
, DCC_INDEPENDENT_64B
);
1251 md
->u
.gfx9
.dcc_independent_128B
= AMDGPU_TILING_GET(tiling_flags
, DCC_INDEPENDENT_128B
);
1252 md
->u
.gfx9
.dcc_max_compressed_block_size
= AMDGPU_TILING_GET(tiling_flags
, DCC_MAX_COMPRESSED_BLOCK_SIZE
);
1253 md
->u
.gfx9
.scanout
= AMDGPU_TILING_GET(tiling_flags
, SCANOUT
);
1255 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1256 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1258 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1259 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1260 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1261 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1263 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1264 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1265 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1266 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1267 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1268 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1269 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1272 md
->size_metadata
= info
.metadata
.size_metadata
;
1273 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1276 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1277 struct radeon_bo_metadata
*md
)
1279 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1280 struct amdgpu_bo_metadata metadata
= {0};
1281 uint64_t tiling_flags
= 0;
1283 assert(bo
->bo
&& "must not be called for slab entries");
1285 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1286 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1288 tiling_flags
|= AMDGPU_TILING_SET(DCC_OFFSET_256B
, md
->u
.gfx9
.dcc_offset_256B
);
1289 tiling_flags
|= AMDGPU_TILING_SET(DCC_PITCH_MAX
, md
->u
.gfx9
.dcc_pitch_max
);
1290 tiling_flags
|= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B
, md
->u
.gfx9
.dcc_independent_64B
);
1291 tiling_flags
|= AMDGPU_TILING_SET(DCC_INDEPENDENT_128B
, md
->u
.gfx9
.dcc_independent_128B
);
1292 tiling_flags
|= AMDGPU_TILING_SET(DCC_MAX_COMPRESSED_BLOCK_SIZE
, md
->u
.gfx9
.dcc_max_compressed_block_size
);
1293 tiling_flags
|= AMDGPU_TILING_SET(SCANOUT
, md
->u
.gfx9
.scanout
);
1295 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1296 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1297 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1298 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1300 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1302 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1303 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1304 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1305 if (md
->u
.legacy
.tile_split
)
1306 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1307 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1308 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1310 if (md
->u
.legacy
.scanout
)
1311 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1313 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1316 metadata
.tiling_info
= tiling_flags
;
1317 metadata
.size_metadata
= md
->size_metadata
;
1318 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1320 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1324 amdgpu_bo_create(struct amdgpu_winsys
*ws
,
1327 enum radeon_bo_domain domain
,
1328 enum radeon_bo_flag flags
)
1330 struct amdgpu_winsys_bo
*bo
;
1333 if (domain
& (RADEON_DOMAIN_GDS
| RADEON_DOMAIN_OA
))
1334 flags
|= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_SUBALLOC
;
1336 /* VRAM implies WC. This is not optional. */
1337 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
1339 /* NO_CPU_ACCESS is not valid with GTT. */
1340 assert(!(domain
& RADEON_DOMAIN_GTT
) || !(flags
& RADEON_FLAG_NO_CPU_ACCESS
));
1342 /* Sparse buffers must have NO_CPU_ACCESS set. */
1343 assert(!(flags
& RADEON_FLAG_SPARSE
) || flags
& RADEON_FLAG_NO_CPU_ACCESS
);
1345 struct pb_slabs
*last_slab
= &ws
->bo_slabs
[NUM_SLAB_ALLOCATORS
- 1];
1346 unsigned max_slab_entry_size
= 1 << (last_slab
->min_order
+ last_slab
->num_orders
- 1);
1348 /* Sub-allocate small buffers from slabs. */
1349 if (!(flags
& (RADEON_FLAG_NO_SUBALLOC
| RADEON_FLAG_SPARSE
)) &&
1350 size
<= max_slab_entry_size
&&
1351 /* The alignment must be at most the size of the smallest slab entry or
1352 * the next power of two. */
1353 alignment
<= MAX2(1 << ws
->bo_slabs
[0].min_order
, util_next_power_of_two(size
))) {
1354 struct pb_slab_entry
*entry
;
1355 int heap
= radeon_get_heap_index(domain
, flags
);
1357 if (heap
< 0 || heap
>= RADEON_MAX_SLAB_HEAPS
)
1360 struct pb_slabs
*slabs
= get_slabs(ws
, size
);
1361 entry
= pb_slab_alloc(slabs
, size
, heap
);
1363 /* Clean up buffer managers and try again. */
1364 amdgpu_clean_up_buffer_managers(ws
);
1366 entry
= pb_slab_alloc(slabs
, size
, heap
);
1372 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1374 pipe_reference_init(&bo
->base
.reference
, 1);
1380 if (flags
& RADEON_FLAG_SPARSE
) {
1381 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1383 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1386 /* This flag is irrelevant for the cache. */
1387 flags
&= ~RADEON_FLAG_NO_SUBALLOC
;
1389 /* Align size to page size. This is the minimum alignment for normal
1390 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1391 * like constant/uniform buffers, can benefit from better and more reuse.
1393 if (domain
& RADEON_DOMAIN_VRAM_GTT
) {
1394 size
= align64(size
, ws
->info
.gart_page_size
);
1395 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1398 bool use_reusable_pool
= flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1400 if (use_reusable_pool
) {
1401 heap
= radeon_get_heap_index(domain
, flags
);
1402 assert(heap
>= 0 && heap
< RADEON_MAX_CACHED_HEAPS
);
1404 /* Get a buffer from the cache. */
1405 bo
= (struct amdgpu_winsys_bo
*)
1406 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, 0, heap
);
1411 /* Create a new one. */
1412 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1414 /* Clean up buffer managers and try again. */
1415 amdgpu_clean_up_buffer_managers(ws
);
1417 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1422 bo
->u
.real
.use_reusable_pool
= use_reusable_pool
;
1426 static struct pb_buffer
*
1427 amdgpu_buffer_create(struct radeon_winsys
*ws
,
1430 enum radeon_bo_domain domain
,
1431 enum radeon_bo_flag flags
)
1433 return amdgpu_bo_create(amdgpu_winsys(ws
), size
, alignment
, domain
,
1437 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1438 struct winsys_handle
*whandle
,
1439 unsigned vm_alignment
)
1441 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1442 struct amdgpu_winsys_bo
*bo
= NULL
;
1443 enum amdgpu_bo_handle_type type
;
1444 struct amdgpu_bo_import_result result
= {0};
1446 amdgpu_va_handle va_handle
= NULL
;
1447 struct amdgpu_bo_info info
= {0};
1448 enum radeon_bo_domain initial
= 0;
1449 enum radeon_bo_flag flags
= 0;
1452 switch (whandle
->type
) {
1453 case WINSYS_HANDLE_TYPE_SHARED
:
1454 type
= amdgpu_bo_handle_type_gem_flink_name
;
1456 case WINSYS_HANDLE_TYPE_FD
:
1457 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1463 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1467 simple_mtx_lock(&ws
->bo_export_table_lock
);
1468 bo
= util_hash_table_get(ws
->bo_export_table
, result
.buf_handle
);
1470 /* If the amdgpu_winsys_bo instance already exists, bump the reference
1471 * counter and return it.
1474 p_atomic_inc(&bo
->base
.reference
.count
);
1475 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1477 /* Release the buffer handle, because we don't need it anymore.
1478 * This function is returning an existing buffer, which has its own
1481 amdgpu_bo_free(result
.buf_handle
);
1485 /* Get initial domains. */
1486 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1490 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1492 amdgpu_get_optimal_vm_alignment(ws
, result
.alloc_size
,
1494 0, &va
, &va_handle
, AMDGPU_VA_RANGE_HIGH
);
1498 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1502 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1506 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1507 initial
|= RADEON_DOMAIN_VRAM
;
1508 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1509 initial
|= RADEON_DOMAIN_GTT
;
1510 if (info
.alloc_flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
)
1511 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
1512 if (info
.alloc_flags
& AMDGPU_GEM_CREATE_CPU_GTT_USWC
)
1513 flags
|= RADEON_FLAG_GTT_WC
;
1515 /* Initialize the structure. */
1516 simple_mtx_init(&bo
->lock
, mtx_plain
);
1517 pipe_reference_init(&bo
->base
.reference
, 1);
1518 bo
->base
.alignment
= info
.phys_alignment
;
1519 bo
->bo
= result
.buf_handle
;
1520 bo
->base
.size
= result
.alloc_size
;
1521 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1524 bo
->u
.real
.va_handle
= va_handle
;
1525 bo
->initial_domain
= initial
;
1527 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1528 bo
->is_shared
= true;
1530 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1531 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1532 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1533 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1535 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1537 amdgpu_add_buffer_to_global_list(bo
);
1539 _mesa_hash_table_insert(ws
->bo_export_table
, bo
->bo
, bo
);
1540 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1545 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1549 amdgpu_va_range_free(va_handle
);
1550 amdgpu_bo_free(result
.buf_handle
);
1554 static bool amdgpu_bo_get_handle(struct radeon_winsys
*rws
,
1555 struct pb_buffer
*buffer
,
1556 struct winsys_handle
*whandle
)
1558 struct amdgpu_screen_winsys
*sws
= amdgpu_screen_winsys(rws
);
1559 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1560 struct amdgpu_winsys
*ws
= bo
->ws
;
1561 enum amdgpu_bo_handle_type type
;
1562 struct hash_entry
*entry
;
1565 /* Don't allow exports of slab entries and sparse buffers. */
1569 bo
->u
.real
.use_reusable_pool
= false;
1571 switch (whandle
->type
) {
1572 case WINSYS_HANDLE_TYPE_SHARED
:
1573 type
= amdgpu_bo_handle_type_gem_flink_name
;
1575 case WINSYS_HANDLE_TYPE_KMS
:
1576 if (sws
->fd
== ws
->fd
) {
1577 whandle
->handle
= bo
->u
.real
.kms_handle
;
1582 goto hash_table_set
;
1585 simple_mtx_lock(&ws
->sws_list_lock
);
1586 entry
= _mesa_hash_table_search(sws
->kms_handles
, bo
);
1587 simple_mtx_unlock(&ws
->sws_list_lock
);
1589 whandle
->handle
= (uintptr_t)entry
->data
;
1593 case WINSYS_HANDLE_TYPE_FD
:
1594 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1600 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1604 if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
1605 int dma_fd
= whandle
->handle
;
1607 r
= drmPrimeFDToHandle(sws
->fd
, dma_fd
, &whandle
->handle
);
1613 simple_mtx_lock(&ws
->sws_list_lock
);
1614 _mesa_hash_table_insert_pre_hashed(sws
->kms_handles
,
1615 bo
->u
.real
.kms_handle
, bo
,
1616 (void*)(uintptr_t)whandle
->handle
);
1617 simple_mtx_unlock(&ws
->sws_list_lock
);
1621 simple_mtx_lock(&ws
->bo_export_table_lock
);
1622 _mesa_hash_table_insert(ws
->bo_export_table
, bo
->bo
, bo
);
1623 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1625 bo
->is_shared
= true;
1629 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1630 void *pointer
, uint64_t size
)
1632 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1633 amdgpu_bo_handle buf_handle
;
1634 struct amdgpu_winsys_bo
*bo
;
1636 amdgpu_va_handle va_handle
;
1637 /* Avoid failure when the size is not page aligned */
1638 uint64_t aligned_size
= align64(size
, ws
->info
.gart_page_size
);
1640 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1644 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
,
1645 aligned_size
, &buf_handle
))
1648 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1650 amdgpu_get_optimal_vm_alignment(ws
, aligned_size
,
1651 ws
->info
.gart_page_size
),
1652 0, &va
, &va_handle
, AMDGPU_VA_RANGE_HIGH
))
1653 goto error_va_alloc
;
1655 if (amdgpu_bo_va_op(buf_handle
, 0, aligned_size
, va
, 0, AMDGPU_VA_OP_MAP
))
1658 /* Initialize it. */
1659 bo
->is_user_ptr
= true;
1660 pipe_reference_init(&bo
->base
.reference
, 1);
1661 simple_mtx_init(&bo
->lock
, mtx_plain
);
1662 bo
->bo
= buf_handle
;
1663 bo
->base
.alignment
= 0;
1664 bo
->base
.size
= size
;
1665 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1667 bo
->cpu_ptr
= pointer
;
1669 bo
->u
.real
.va_handle
= va_handle
;
1670 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1671 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1673 ws
->allocated_gtt
+= aligned_size
;
1675 amdgpu_add_buffer_to_global_list(bo
);
1677 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1679 return (struct pb_buffer
*)bo
;
1682 amdgpu_va_range_free(va_handle
);
1685 amdgpu_bo_free(buf_handle
);
1692 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1694 return ((struct amdgpu_winsys_bo
*)buf
)->is_user_ptr
;
1697 static bool amdgpu_bo_is_suballocated(struct pb_buffer
*buf
)
1699 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
1701 return !bo
->bo
&& !bo
->sparse
;
1704 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1706 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1709 void amdgpu_bo_init_functions(struct amdgpu_screen_winsys
*ws
)
1711 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1712 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1713 ws
->base
.buffer_map
= amdgpu_bo_map
;
1714 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1715 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1716 ws
->base
.buffer_create
= amdgpu_buffer_create
;
1717 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1718 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1719 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1720 ws
->base
.buffer_is_suballocated
= amdgpu_bo_is_suballocated
;
1721 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1722 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1723 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1724 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;
1725 ws
->base
.buffer_get_flags
= amdgpu_bo_get_flags
;