2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
32 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
35 #include "state_tracker/drm_driver.h"
36 #include <amdgpu_drm.h>
41 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
42 enum radeon_bo_usage usage
)
44 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
45 struct amdgpu_winsys
*ws
= bo
->ws
;
49 if (p_atomic_read(&bo
->num_active_ioctls
))
53 abs_timeout
= os_time_get_absolute_timeout(timeout
);
55 /* Wait if any ioctl is being submitted with this buffer. */
56 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
61 /* We can't use user fences for shared buffers, because user fences
62 * are local to this process only. If we want to wait for all buffer
63 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
65 bool buffer_busy
= true;
68 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
70 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
79 pipe_mutex_lock(ws
->bo_fence_lock
);
81 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
82 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
86 /* Release the idle fences to avoid checking them again later. */
87 for (unsigned i
= 0; i
< idle_fences
; ++i
)
88 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
90 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
91 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
92 bo
->num_fences
-= idle_fences
;
94 buffer_idle
= !bo
->num_fences
;
95 pipe_mutex_unlock(ws
->bo_fence_lock
);
99 bool buffer_idle
= true;
101 pipe_mutex_lock(ws
->bo_fence_lock
);
102 while (bo
->num_fences
&& buffer_idle
) {
103 struct pipe_fence_handle
*fence
= NULL
;
104 bool fence_idle
= false;
106 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
108 /* Wait for the fence. */
109 pipe_mutex_unlock(ws
->bo_fence_lock
);
110 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
114 pipe_mutex_lock(ws
->bo_fence_lock
);
116 /* Release an idle fence to avoid checking it again later, keeping in
117 * mind that the fence array may have been modified by other threads.
119 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
120 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
121 memmove(&bo
->fences
[0], &bo
->fences
[1],
122 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
126 amdgpu_fence_reference(&fence
, NULL
);
128 pipe_mutex_unlock(ws
->bo_fence_lock
);
134 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
135 struct pb_buffer
*buf
)
137 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
140 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
142 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
143 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
150 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
152 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
154 pipe_mutex_lock(bo
->ws
->global_bo_list_lock
);
155 LIST_DEL(&bo
->global_list_item
);
156 bo
->ws
->num_buffers
--;
157 pipe_mutex_unlock(bo
->ws
->global_bo_list_lock
);
159 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
160 amdgpu_va_range_free(bo
->va_handle
);
161 amdgpu_bo_free(bo
->bo
);
163 amdgpu_bo_remove_fences(bo
);
165 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
166 bo
->ws
->allocated_vram
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
167 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
168 bo
->ws
->allocated_gtt
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
170 if (bo
->map_count
>= 1) {
171 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
172 bo
->ws
->mapped_vram
-= bo
->base
.size
;
173 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
174 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
180 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
182 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
184 if (bo
->use_reusable_pool
)
185 pb_cache_add_buffer(&bo
->cache_entry
);
187 amdgpu_bo_destroy(_buf
);
190 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
191 struct radeon_winsys_cs
*rcs
,
192 enum pipe_transfer_usage usage
)
194 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
195 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
199 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
200 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
201 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
202 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
203 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
206 * Since we are mapping for read, we don't need to wait
207 * if the GPU is using the buffer for read too
208 * (neither one is changing it).
210 * Only check whether the buffer is being used for write. */
211 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
212 RADEON_USAGE_WRITE
)) {
213 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
217 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
218 RADEON_USAGE_WRITE
)) {
222 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
223 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
227 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
228 RADEON_USAGE_READWRITE
)) {
233 uint64_t time
= os_time_get_nano();
235 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
238 * Since we are mapping for read, we don't need to wait
239 * if the GPU is using the buffer for read too
240 * (neither one is changing it).
242 * Only check whether the buffer is being used for write. */
243 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
244 RADEON_USAGE_WRITE
)) {
245 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
247 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
248 if (p_atomic_read(&bo
->num_active_ioctls
))
249 amdgpu_cs_sync_flush(rcs
);
251 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
254 /* Mapping for write. */
256 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
257 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
259 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
260 if (p_atomic_read(&bo
->num_active_ioctls
))
261 amdgpu_cs_sync_flush(rcs
);
265 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
266 RADEON_USAGE_READWRITE
);
269 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
273 /* If the buffer is created from user memory, return the user pointer. */
277 r
= amdgpu_bo_cpu_map(bo
->bo
, &cpu
);
279 /* Clear the cache and try again. */
280 pb_cache_release_all_buffers(&bo
->ws
->bo_cache
);
281 r
= amdgpu_bo_cpu_map(bo
->bo
, &cpu
);
286 if (p_atomic_inc_return(&bo
->map_count
) == 1) {
287 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
288 bo
->ws
->mapped_vram
+= bo
->base
.size
;
289 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
290 bo
->ws
->mapped_gtt
+= bo
->base
.size
;
295 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
297 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
302 if (p_atomic_dec_zero(&bo
->map_count
)) {
303 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
304 bo
->ws
->mapped_vram
-= bo
->base
.size
;
305 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
306 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
309 amdgpu_bo_cpu_unmap(bo
->bo
);
312 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
313 amdgpu_bo_destroy_or_cache
314 /* other functions are never called */
317 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
319 struct amdgpu_winsys
*ws
= bo
->ws
;
321 pipe_mutex_lock(ws
->global_bo_list_lock
);
322 LIST_ADDTAIL(&bo
->global_list_item
, &ws
->global_bo_list
);
324 pipe_mutex_unlock(ws
->global_bo_list_lock
);
327 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
331 enum radeon_bo_domain initial_domain
,
333 unsigned pb_cache_bucket
)
335 struct amdgpu_bo_alloc_request request
= {0};
336 amdgpu_bo_handle buf_handle
;
338 struct amdgpu_winsys_bo
*bo
;
339 amdgpu_va_handle va_handle
;
340 unsigned va_gap_size
;
343 assert(initial_domain
& RADEON_DOMAIN_VRAM_GTT
);
344 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
349 pb_cache_init_entry(&ws
->bo_cache
, &bo
->cache_entry
, &bo
->base
,
351 request
.alloc_size
= size
;
352 request
.phys_alignment
= alignment
;
354 if (initial_domain
& RADEON_DOMAIN_VRAM
)
355 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
356 if (initial_domain
& RADEON_DOMAIN_GTT
)
357 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
359 if (flags
& RADEON_FLAG_CPU_ACCESS
)
360 request
.flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
361 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
362 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
363 if (flags
& RADEON_FLAG_GTT_WC
)
364 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
366 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
368 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
369 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
370 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
371 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
375 va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
376 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
377 size
+ va_gap_size
, alignment
, 0, &va
, &va_handle
, 0);
381 r
= amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
);
385 pipe_reference_init(&bo
->base
.reference
, 1);
386 bo
->base
.alignment
= alignment
;
387 bo
->base
.usage
= usage
;
388 bo
->base
.size
= size
;
389 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
393 bo
->va_handle
= va_handle
;
394 bo
->initial_domain
= initial_domain
;
395 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
397 if (initial_domain
& RADEON_DOMAIN_VRAM
)
398 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
399 else if (initial_domain
& RADEON_DOMAIN_GTT
)
400 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
402 amdgpu_add_buffer_to_global_list(bo
);
407 amdgpu_va_range_free(va_handle
);
410 amdgpu_bo_free(buf_handle
);
417 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
419 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
421 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
425 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
428 static unsigned eg_tile_split(unsigned tile_split
)
430 switch (tile_split
) {
431 case 0: tile_split
= 64; break;
432 case 1: tile_split
= 128; break;
433 case 2: tile_split
= 256; break;
434 case 3: tile_split
= 512; break;
436 case 4: tile_split
= 1024; break;
437 case 5: tile_split
= 2048; break;
438 case 6: tile_split
= 4096; break;
443 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
445 switch (eg_tile_split
) {
457 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
458 struct radeon_bo_metadata
*md
)
460 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
461 struct amdgpu_bo_info info
= {0};
462 uint32_t tiling_flags
;
465 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
469 tiling_flags
= info
.metadata
.tiling_info
;
471 md
->microtile
= RADEON_LAYOUT_LINEAR
;
472 md
->macrotile
= RADEON_LAYOUT_LINEAR
;
474 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
475 md
->macrotile
= RADEON_LAYOUT_TILED
;
476 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
477 md
->microtile
= RADEON_LAYOUT_TILED
;
479 md
->pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
480 md
->bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
481 md
->bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
482 md
->tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
483 md
->mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
484 md
->num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
485 md
->scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
487 md
->size_metadata
= info
.metadata
.size_metadata
;
488 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
491 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
492 struct radeon_bo_metadata
*md
)
494 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
495 struct amdgpu_bo_metadata metadata
= {0};
496 uint32_t tiling_flags
= 0;
498 if (md
->macrotile
== RADEON_LAYOUT_TILED
)
499 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
500 else if (md
->microtile
== RADEON_LAYOUT_TILED
)
501 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
503 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
505 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->pipe_config
);
506 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->bankw
));
507 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->bankh
));
509 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->tile_split
));
510 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->mtilea
));
511 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->num_banks
)-1);
514 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
516 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
518 metadata
.tiling_info
= tiling_flags
;
519 metadata
.size_metadata
= md
->size_metadata
;
520 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
522 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
525 static struct pb_buffer
*
526 amdgpu_bo_create(struct radeon_winsys
*rws
,
529 enum radeon_bo_domain domain
,
530 enum radeon_bo_flag flags
)
532 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
533 struct amdgpu_winsys_bo
*bo
;
534 unsigned usage
= 0, pb_cache_bucket
;
536 /* This flag is irrelevant for the cache. */
537 flags
&= ~RADEON_FLAG_HANDLE
;
539 /* Align size to page size. This is the minimum alignment for normal
540 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
541 * like constant/uniform buffers, can benefit from better and more reuse.
543 size
= align64(size
, ws
->info
.gart_page_size
);
544 alignment
= align(alignment
, ws
->info
.gart_page_size
);
546 /* Only set one usage bit each for domains and flags, or the cache manager
547 * might consider different sets of domains / flags compatible
549 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
553 assert(flags
< sizeof(usage
) * 8 - 3);
554 usage
|= 1 << (flags
+ 3);
556 /* Determine the pb_cache bucket for minimizing pb_cache misses. */
558 if (size
<= 4096) /* small buffers */
559 pb_cache_bucket
+= 1;
560 if (domain
& RADEON_DOMAIN_VRAM
) /* VRAM or VRAM+GTT */
561 pb_cache_bucket
+= 2;
562 if (flags
== RADEON_FLAG_GTT_WC
) /* WC */
563 pb_cache_bucket
+= 4;
564 assert(pb_cache_bucket
< ARRAY_SIZE(ws
->bo_cache
.buckets
));
566 /* Get a buffer from the cache. */
567 bo
= (struct amdgpu_winsys_bo
*)
568 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, usage
,
573 /* Create a new one. */
574 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
577 /* Clear the cache and try again. */
578 pb_cache_release_all_buffers(&ws
->bo_cache
);
579 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
585 bo
->use_reusable_pool
= true;
589 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
590 struct winsys_handle
*whandle
,
594 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
595 struct amdgpu_winsys_bo
*bo
;
596 enum amdgpu_bo_handle_type type
;
597 struct amdgpu_bo_import_result result
= {0};
599 amdgpu_va_handle va_handle
;
600 struct amdgpu_bo_info info
= {0};
601 enum radeon_bo_domain initial
= 0;
604 /* Initialize the structure. */
605 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
610 switch (whandle
->type
) {
611 case DRM_API_HANDLE_TYPE_SHARED
:
612 type
= amdgpu_bo_handle_type_gem_flink_name
;
614 case DRM_API_HANDLE_TYPE_FD
:
615 type
= amdgpu_bo_handle_type_dma_buf_fd
;
621 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
625 /* Get initial domains. */
626 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
630 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
631 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
, 0);
635 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
639 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
640 initial
|= RADEON_DOMAIN_VRAM
;
641 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
642 initial
|= RADEON_DOMAIN_GTT
;
645 pipe_reference_init(&bo
->base
.reference
, 1);
646 bo
->base
.alignment
= info
.phys_alignment
;
647 bo
->bo
= result
.buf_handle
;
648 bo
->base
.size
= result
.alloc_size
;
649 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
652 bo
->va_handle
= va_handle
;
653 bo
->initial_domain
= initial
;
654 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
655 bo
->is_shared
= true;
658 *stride
= whandle
->stride
;
660 *offset
= whandle
->offset
;
662 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
663 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
664 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
665 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
667 amdgpu_add_buffer_to_global_list(bo
);
672 amdgpu_va_range_free(va_handle
);
675 amdgpu_bo_free(result
.buf_handle
);
682 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
683 unsigned stride
, unsigned offset
,
685 struct winsys_handle
*whandle
)
687 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
688 enum amdgpu_bo_handle_type type
;
691 bo
->use_reusable_pool
= false;
693 switch (whandle
->type
) {
694 case DRM_API_HANDLE_TYPE_SHARED
:
695 type
= amdgpu_bo_handle_type_gem_flink_name
;
697 case DRM_API_HANDLE_TYPE_FD
:
698 type
= amdgpu_bo_handle_type_dma_buf_fd
;
700 case DRM_API_HANDLE_TYPE_KMS
:
701 type
= amdgpu_bo_handle_type_kms
;
707 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
711 whandle
->stride
= stride
;
712 whandle
->offset
= offset
;
713 whandle
->offset
+= slice_size
* whandle
->layer
;
714 bo
->is_shared
= true;
718 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
719 void *pointer
, uint64_t size
)
721 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
722 amdgpu_bo_handle buf_handle
;
723 struct amdgpu_winsys_bo
*bo
;
725 amdgpu_va_handle va_handle
;
727 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
731 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
734 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
735 size
, 1 << 12, 0, &va
, &va_handle
, 0))
738 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
742 pipe_reference_init(&bo
->base
.reference
, 1);
744 bo
->base
.alignment
= 0;
745 bo
->base
.size
= size
;
746 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
748 bo
->user_ptr
= pointer
;
750 bo
->va_handle
= va_handle
;
751 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
752 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
754 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
756 amdgpu_add_buffer_to_global_list(bo
);
758 return (struct pb_buffer
*)bo
;
761 amdgpu_va_range_free(va_handle
);
764 amdgpu_bo_free(buf_handle
);
771 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
773 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
776 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
778 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
781 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
783 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
784 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
785 ws
->base
.buffer_map
= amdgpu_bo_map
;
786 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
787 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
788 ws
->base
.buffer_create
= amdgpu_bo_create
;
789 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
790 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
791 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
792 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
793 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
794 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;