2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
32 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
35 #include "state_tracker/drm_driver.h"
36 #include <amdgpu_drm.h>
41 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
42 enum radeon_bo_usage usage
)
44 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
45 struct amdgpu_winsys
*ws
= bo
->ws
;
49 if (p_atomic_read(&bo
->num_active_ioctls
))
53 abs_timeout
= os_time_get_absolute_timeout(timeout
);
55 /* Wait if any ioctl is being submitted with this buffer. */
56 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
61 /* We can't use user fences for shared buffers, because user fences
62 * are local to this process only. If we want to wait for all buffer
63 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
65 bool buffer_busy
= true;
68 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
70 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
76 pipe_mutex_lock(ws
->bo_fence_lock
);
78 if (amdgpu_fence_wait(bo
->fence
, 0, false)) {
79 /* Release the idle fence to avoid checking it again later. */
80 amdgpu_fence_reference(&bo
->fence
, NULL
);
82 pipe_mutex_unlock(ws
->bo_fence_lock
);
86 pipe_mutex_unlock(ws
->bo_fence_lock
);
90 struct pipe_fence_handle
*fence
= NULL
;
91 bool fence_idle
= false;
92 bool buffer_idle
= true;
94 /* Take a reference to the fences, so that we can wait for it
95 * without the lock. */
96 pipe_mutex_lock(ws
->bo_fence_lock
);
97 amdgpu_fence_reference(&fence
, bo
->fence
);
98 pipe_mutex_unlock(ws
->bo_fence_lock
);
100 /* Now wait for the fence. */
102 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
108 /* Release idle fences to avoid checking them again later. */
109 pipe_mutex_lock(ws
->bo_fence_lock
);
110 if (fence
== bo
->fence
&& fence_idle
)
111 amdgpu_fence_reference(&bo
->fence
, NULL
);
112 amdgpu_fence_reference(&fence
, NULL
);
113 pipe_mutex_unlock(ws
->bo_fence_lock
);
119 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
120 struct pb_buffer
*buf
)
122 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
125 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
127 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
129 pipe_mutex_lock(bo
->ws
->global_bo_list_lock
);
130 LIST_DEL(&bo
->global_list_item
);
131 bo
->ws
->num_buffers
--;
132 pipe_mutex_unlock(bo
->ws
->global_bo_list_lock
);
134 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
135 amdgpu_va_range_free(bo
->va_handle
);
136 amdgpu_bo_free(bo
->bo
);
138 amdgpu_fence_reference(&bo
->fence
, NULL
);
140 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
141 bo
->ws
->allocated_vram
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
142 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
143 bo
->ws
->allocated_gtt
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
145 if (bo
->map_count
>= 1) {
146 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
147 bo
->ws
->mapped_vram
-= bo
->base
.size
;
148 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
149 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
155 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
157 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
159 if (bo
->use_reusable_pool
)
160 pb_cache_add_buffer(&bo
->cache_entry
);
162 amdgpu_bo_destroy(_buf
);
165 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
166 struct radeon_winsys_cs
*rcs
,
167 enum pipe_transfer_usage usage
)
169 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
170 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
174 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
175 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
176 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
177 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
178 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
181 * Since we are mapping for read, we don't need to wait
182 * if the GPU is using the buffer for read too
183 * (neither one is changing it).
185 * Only check whether the buffer is being used for write. */
186 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
187 RADEON_USAGE_WRITE
)) {
188 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
192 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
193 RADEON_USAGE_WRITE
)) {
197 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
198 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
202 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
203 RADEON_USAGE_READWRITE
)) {
208 uint64_t time
= os_time_get_nano();
210 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
213 * Since we are mapping for read, we don't need to wait
214 * if the GPU is using the buffer for read too
215 * (neither one is changing it).
217 * Only check whether the buffer is being used for write. */
218 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
219 RADEON_USAGE_WRITE
)) {
220 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
222 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
223 if (p_atomic_read(&bo
->num_active_ioctls
))
224 amdgpu_cs_sync_flush(rcs
);
226 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
229 /* Mapping for write. */
231 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
232 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
234 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
235 if (p_atomic_read(&bo
->num_active_ioctls
))
236 amdgpu_cs_sync_flush(rcs
);
240 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
241 RADEON_USAGE_READWRITE
);
244 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
248 /* If the buffer is created from user memory, return the user pointer. */
252 r
= amdgpu_bo_cpu_map(bo
->bo
, &cpu
);
254 /* Clear the cache and try again. */
255 pb_cache_release_all_buffers(&bo
->ws
->bo_cache
);
256 r
= amdgpu_bo_cpu_map(bo
->bo
, &cpu
);
261 if (p_atomic_inc_return(&bo
->map_count
) == 1) {
262 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
263 bo
->ws
->mapped_vram
+= bo
->base
.size
;
264 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
265 bo
->ws
->mapped_gtt
+= bo
->base
.size
;
270 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
272 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
277 if (p_atomic_dec_zero(&bo
->map_count
)) {
278 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
279 bo
->ws
->mapped_vram
-= bo
->base
.size
;
280 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
281 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
284 amdgpu_bo_cpu_unmap(bo
->bo
);
287 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
288 amdgpu_bo_destroy_or_cache
289 /* other functions are never called */
292 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
294 struct amdgpu_winsys
*ws
= bo
->ws
;
296 pipe_mutex_lock(ws
->global_bo_list_lock
);
297 LIST_ADDTAIL(&bo
->global_list_item
, &ws
->global_bo_list
);
299 pipe_mutex_unlock(ws
->global_bo_list_lock
);
302 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
306 enum radeon_bo_domain initial_domain
,
308 unsigned pb_cache_bucket
)
310 struct amdgpu_bo_alloc_request request
= {0};
311 amdgpu_bo_handle buf_handle
;
313 struct amdgpu_winsys_bo
*bo
;
314 amdgpu_va_handle va_handle
;
315 unsigned va_gap_size
;
318 assert(initial_domain
& RADEON_DOMAIN_VRAM_GTT
);
319 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
324 pb_cache_init_entry(&ws
->bo_cache
, &bo
->cache_entry
, &bo
->base
,
326 request
.alloc_size
= size
;
327 request
.phys_alignment
= alignment
;
329 if (initial_domain
& RADEON_DOMAIN_VRAM
)
330 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
331 if (initial_domain
& RADEON_DOMAIN_GTT
)
332 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
334 if (flags
& RADEON_FLAG_CPU_ACCESS
)
335 request
.flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
336 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
337 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
338 if (flags
& RADEON_FLAG_GTT_WC
)
339 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
341 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
343 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
344 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
345 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
346 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
350 va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
351 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
352 size
+ va_gap_size
, alignment
, 0, &va
, &va_handle
, 0);
356 r
= amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
);
360 pipe_reference_init(&bo
->base
.reference
, 1);
361 bo
->base
.alignment
= alignment
;
362 bo
->base
.usage
= usage
;
363 bo
->base
.size
= size
;
364 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
368 bo
->va_handle
= va_handle
;
369 bo
->initial_domain
= initial_domain
;
370 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
372 if (initial_domain
& RADEON_DOMAIN_VRAM
)
373 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
374 else if (initial_domain
& RADEON_DOMAIN_GTT
)
375 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
377 amdgpu_add_buffer_to_global_list(bo
);
382 amdgpu_va_range_free(va_handle
);
385 amdgpu_bo_free(buf_handle
);
392 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
394 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
396 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
400 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
403 static unsigned eg_tile_split(unsigned tile_split
)
405 switch (tile_split
) {
406 case 0: tile_split
= 64; break;
407 case 1: tile_split
= 128; break;
408 case 2: tile_split
= 256; break;
409 case 3: tile_split
= 512; break;
411 case 4: tile_split
= 1024; break;
412 case 5: tile_split
= 2048; break;
413 case 6: tile_split
= 4096; break;
418 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
420 switch (eg_tile_split
) {
432 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
433 struct radeon_bo_metadata
*md
)
435 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
436 struct amdgpu_bo_info info
= {0};
437 uint32_t tiling_flags
;
440 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
444 tiling_flags
= info
.metadata
.tiling_info
;
446 md
->microtile
= RADEON_LAYOUT_LINEAR
;
447 md
->macrotile
= RADEON_LAYOUT_LINEAR
;
449 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
450 md
->macrotile
= RADEON_LAYOUT_TILED
;
451 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
452 md
->microtile
= RADEON_LAYOUT_TILED
;
454 md
->pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
455 md
->bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
456 md
->bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
457 md
->tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
458 md
->mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
459 md
->num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
460 md
->scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
462 md
->size_metadata
= info
.metadata
.size_metadata
;
463 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
466 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
467 struct radeon_bo_metadata
*md
)
469 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
470 struct amdgpu_bo_metadata metadata
= {0};
471 uint32_t tiling_flags
= 0;
473 if (md
->macrotile
== RADEON_LAYOUT_TILED
)
474 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
475 else if (md
->microtile
== RADEON_LAYOUT_TILED
)
476 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
478 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
480 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->pipe_config
);
481 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->bankw
));
482 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->bankh
));
484 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->tile_split
));
485 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->mtilea
));
486 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->num_banks
)-1);
489 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
491 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
493 metadata
.tiling_info
= tiling_flags
;
494 metadata
.size_metadata
= md
->size_metadata
;
495 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
497 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
500 static struct pb_buffer
*
501 amdgpu_bo_create(struct radeon_winsys
*rws
,
504 enum radeon_bo_domain domain
,
505 enum radeon_bo_flag flags
)
507 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
508 struct amdgpu_winsys_bo
*bo
;
509 unsigned usage
= 0, pb_cache_bucket
;
511 /* This flag is irrelevant for the cache. */
512 flags
&= ~RADEON_FLAG_HANDLE
;
514 /* Align size to page size. This is the minimum alignment for normal
515 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
516 * like constant/uniform buffers, can benefit from better and more reuse.
518 size
= align64(size
, ws
->info
.gart_page_size
);
519 alignment
= align(alignment
, ws
->info
.gart_page_size
);
521 /* Only set one usage bit each for domains and flags, or the cache manager
522 * might consider different sets of domains / flags compatible
524 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
528 assert(flags
< sizeof(usage
) * 8 - 3);
529 usage
|= 1 << (flags
+ 3);
531 /* Determine the pb_cache bucket for minimizing pb_cache misses. */
533 if (size
<= 4096) /* small buffers */
534 pb_cache_bucket
+= 1;
535 if (domain
& RADEON_DOMAIN_VRAM
) /* VRAM or VRAM+GTT */
536 pb_cache_bucket
+= 2;
537 if (flags
== RADEON_FLAG_GTT_WC
) /* WC */
538 pb_cache_bucket
+= 4;
539 assert(pb_cache_bucket
< ARRAY_SIZE(ws
->bo_cache
.buckets
));
541 /* Get a buffer from the cache. */
542 bo
= (struct amdgpu_winsys_bo
*)
543 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, usage
,
548 /* Create a new one. */
549 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
552 /* Clear the cache and try again. */
553 pb_cache_release_all_buffers(&ws
->bo_cache
);
554 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
560 bo
->use_reusable_pool
= true;
564 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
565 struct winsys_handle
*whandle
,
569 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
570 struct amdgpu_winsys_bo
*bo
;
571 enum amdgpu_bo_handle_type type
;
572 struct amdgpu_bo_import_result result
= {0};
574 amdgpu_va_handle va_handle
;
575 struct amdgpu_bo_info info
= {0};
576 enum radeon_bo_domain initial
= 0;
579 /* Initialize the structure. */
580 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
585 switch (whandle
->type
) {
586 case DRM_API_HANDLE_TYPE_SHARED
:
587 type
= amdgpu_bo_handle_type_gem_flink_name
;
589 case DRM_API_HANDLE_TYPE_FD
:
590 type
= amdgpu_bo_handle_type_dma_buf_fd
;
596 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
600 /* Get initial domains. */
601 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
605 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
606 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
, 0);
610 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
614 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
615 initial
|= RADEON_DOMAIN_VRAM
;
616 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
617 initial
|= RADEON_DOMAIN_GTT
;
620 pipe_reference_init(&bo
->base
.reference
, 1);
621 bo
->base
.alignment
= info
.phys_alignment
;
622 bo
->bo
= result
.buf_handle
;
623 bo
->base
.size
= result
.alloc_size
;
624 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
627 bo
->va_handle
= va_handle
;
628 bo
->initial_domain
= initial
;
629 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
630 bo
->is_shared
= true;
633 *stride
= whandle
->stride
;
635 *offset
= whandle
->offset
;
637 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
638 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
639 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
640 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
642 amdgpu_add_buffer_to_global_list(bo
);
647 amdgpu_va_range_free(va_handle
);
650 amdgpu_bo_free(result
.buf_handle
);
657 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
658 unsigned stride
, unsigned offset
,
660 struct winsys_handle
*whandle
)
662 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
663 enum amdgpu_bo_handle_type type
;
666 bo
->use_reusable_pool
= false;
668 switch (whandle
->type
) {
669 case DRM_API_HANDLE_TYPE_SHARED
:
670 type
= amdgpu_bo_handle_type_gem_flink_name
;
672 case DRM_API_HANDLE_TYPE_FD
:
673 type
= amdgpu_bo_handle_type_dma_buf_fd
;
675 case DRM_API_HANDLE_TYPE_KMS
:
676 type
= amdgpu_bo_handle_type_kms
;
682 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
686 whandle
->stride
= stride
;
687 whandle
->offset
= offset
;
688 whandle
->offset
+= slice_size
* whandle
->layer
;
689 bo
->is_shared
= true;
693 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
694 void *pointer
, uint64_t size
)
696 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
697 amdgpu_bo_handle buf_handle
;
698 struct amdgpu_winsys_bo
*bo
;
700 amdgpu_va_handle va_handle
;
702 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
706 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
709 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
710 size
, 1 << 12, 0, &va
, &va_handle
, 0))
713 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
717 pipe_reference_init(&bo
->base
.reference
, 1);
719 bo
->base
.alignment
= 0;
720 bo
->base
.size
= size
;
721 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
723 bo
->user_ptr
= pointer
;
725 bo
->va_handle
= va_handle
;
726 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
727 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
729 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
731 amdgpu_add_buffer_to_global_list(bo
);
733 return (struct pb_buffer
*)bo
;
736 amdgpu_va_range_free(va_handle
);
739 amdgpu_bo_free(buf_handle
);
746 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
748 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
751 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
753 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
756 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
758 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
759 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
760 ws
->base
.buffer_map
= amdgpu_bo_map
;
761 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
762 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
763 ws
->base
.buffer_create
= amdgpu_bo_create
;
764 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
765 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
766 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
767 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
768 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
769 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;