2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "amdgpu_cs.h"
30 #include "util/hash_table.h"
31 #include "util/os_time.h"
32 #include "util/u_hash_table.h"
33 #include "state_tracker/drm_driver.h"
34 #include <amdgpu_drm.h>
39 #ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
40 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
43 #ifndef AMDGPU_VA_RANGE_HIGH
44 #define AMDGPU_VA_RANGE_HIGH 0x2
47 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
48 #define DEBUG_SPARSE_COMMITS 0
50 struct amdgpu_sparse_backing_chunk
{
54 static void amdgpu_bo_unmap(struct pb_buffer
*buf
);
56 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
57 enum radeon_bo_usage usage
)
59 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
60 struct amdgpu_winsys
*ws
= bo
->ws
;
64 if (p_atomic_read(&bo
->num_active_ioctls
))
68 abs_timeout
= os_time_get_absolute_timeout(timeout
);
70 /* Wait if any ioctl is being submitted with this buffer. */
71 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
76 /* We can't use user fences for shared buffers, because user fences
77 * are local to this process only. If we want to wait for all buffer
78 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
80 bool buffer_busy
= true;
83 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
85 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
94 simple_mtx_lock(&ws
->bo_fence_lock
);
96 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
97 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
101 /* Release the idle fences to avoid checking them again later. */
102 for (unsigned i
= 0; i
< idle_fences
; ++i
)
103 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
105 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
106 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
107 bo
->num_fences
-= idle_fences
;
109 buffer_idle
= !bo
->num_fences
;
110 simple_mtx_unlock(&ws
->bo_fence_lock
);
114 bool buffer_idle
= true;
116 simple_mtx_lock(&ws
->bo_fence_lock
);
117 while (bo
->num_fences
&& buffer_idle
) {
118 struct pipe_fence_handle
*fence
= NULL
;
119 bool fence_idle
= false;
121 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
123 /* Wait for the fence. */
124 simple_mtx_unlock(&ws
->bo_fence_lock
);
125 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
129 simple_mtx_lock(&ws
->bo_fence_lock
);
131 /* Release an idle fence to avoid checking it again later, keeping in
132 * mind that the fence array may have been modified by other threads.
134 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
135 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
136 memmove(&bo
->fences
[0], &bo
->fences
[1],
137 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
141 amdgpu_fence_reference(&fence
, NULL
);
143 simple_mtx_unlock(&ws
->bo_fence_lock
);
149 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
150 struct pb_buffer
*buf
)
152 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
155 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
157 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
158 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
165 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
167 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
168 struct amdgpu_screen_winsys
*sws_iter
;
169 struct amdgpu_winsys
*ws
= bo
->ws
;
171 assert(bo
->bo
&& "must not be called for slab entries");
173 if (!bo
->is_user_ptr
&& bo
->cpu_ptr
) {
175 amdgpu_bo_unmap(&bo
->base
);
177 assert(bo
->is_user_ptr
|| bo
->u
.real
.map_count
== 0);
179 if (ws
->debug_all_bos
) {
180 simple_mtx_lock(&ws
->global_bo_list_lock
);
181 list_del(&bo
->u
.real
.global_list_item
);
183 simple_mtx_unlock(&ws
->global_bo_list_lock
);
186 simple_mtx_lock(&ws
->sws_list_lock
);
187 for (sws_iter
= ws
->sws_list
; sws_iter
; sws_iter
= sws_iter
->next
) {
188 if (sws_iter
->kms_handles
)
189 _mesa_hash_table_remove_key(sws_iter
->kms_handles
, bo
);
191 simple_mtx_unlock(&ws
->sws_list_lock
);
193 simple_mtx_lock(&ws
->bo_export_table_lock
);
194 util_hash_table_remove(ws
->bo_export_table
, bo
->bo
);
195 simple_mtx_unlock(&ws
->bo_export_table_lock
);
197 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM_GTT
) {
198 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
199 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
201 amdgpu_bo_free(bo
->bo
);
203 amdgpu_bo_remove_fences(bo
);
205 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
206 ws
->allocated_vram
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
207 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
208 ws
->allocated_gtt
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
210 simple_mtx_destroy(&bo
->lock
);
214 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
216 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
218 assert(bo
->bo
); /* slab buffers have a separate vtbl */
220 if (bo
->u
.real
.use_reusable_pool
)
221 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
223 amdgpu_bo_destroy(_buf
);
226 static void amdgpu_clean_up_buffer_managers(struct amdgpu_winsys
*ws
)
228 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++)
229 pb_slabs_reclaim(&ws
->bo_slabs
[i
]);
231 pb_cache_release_all_buffers(&ws
->bo_cache
);
234 static bool amdgpu_bo_do_map(struct amdgpu_winsys_bo
*bo
, void **cpu
)
236 assert(!bo
->sparse
&& bo
->bo
&& !bo
->is_user_ptr
);
237 int r
= amdgpu_bo_cpu_map(bo
->bo
, cpu
);
239 /* Clean up buffer managers and try again. */
240 amdgpu_clean_up_buffer_managers(bo
->ws
);
241 r
= amdgpu_bo_cpu_map(bo
->bo
, cpu
);
246 if (p_atomic_inc_return(&bo
->u
.real
.map_count
) == 1) {
247 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
248 bo
->ws
->mapped_vram
+= bo
->base
.size
;
249 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
250 bo
->ws
->mapped_gtt
+= bo
->base
.size
;
251 bo
->ws
->num_mapped_buffers
++;
257 void *amdgpu_bo_map(struct pb_buffer
*buf
,
258 struct radeon_cmdbuf
*rcs
,
259 enum pipe_transfer_usage usage
)
261 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
262 struct amdgpu_winsys_bo
*real
;
263 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
267 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
268 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
269 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
270 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
271 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
274 * Since we are mapping for read, we don't need to wait
275 * if the GPU is using the buffer for read too
276 * (neither one is changing it).
278 * Only check whether the buffer is being used for write. */
279 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
280 RADEON_USAGE_WRITE
)) {
281 cs
->flush_cs(cs
->flush_data
,
282 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
286 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
287 RADEON_USAGE_WRITE
)) {
291 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
292 cs
->flush_cs(cs
->flush_data
,
293 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
297 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
298 RADEON_USAGE_READWRITE
)) {
303 uint64_t time
= os_time_get_nano();
305 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
308 * Since we are mapping for read, we don't need to wait
309 * if the GPU is using the buffer for read too
310 * (neither one is changing it).
312 * Only check whether the buffer is being used for write. */
314 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
315 RADEON_USAGE_WRITE
)) {
316 cs
->flush_cs(cs
->flush_data
,
317 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
319 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
320 if (p_atomic_read(&bo
->num_active_ioctls
))
321 amdgpu_cs_sync_flush(rcs
);
325 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
328 /* Mapping for write. */
330 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
331 cs
->flush_cs(cs
->flush_data
,
332 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
334 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
335 if (p_atomic_read(&bo
->num_active_ioctls
))
336 amdgpu_cs_sync_flush(rcs
);
340 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
341 RADEON_USAGE_READWRITE
);
344 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
348 /* Buffer synchronization has been checked, now actually map the buffer. */
355 real
= bo
->u
.slab
.real
;
356 offset
= bo
->va
- real
->va
;
359 if (usage
& RADEON_TRANSFER_TEMPORARY
) {
360 if (real
->is_user_ptr
) {
363 if (!amdgpu_bo_do_map(real
, &cpu
))
367 cpu
= p_atomic_read(&real
->cpu_ptr
);
369 simple_mtx_lock(&real
->lock
);
370 /* Must re-check due to the possibility of a race. Re-check need not
371 * be atomic thanks to the lock. */
374 if (!amdgpu_bo_do_map(real
, &cpu
)) {
375 simple_mtx_unlock(&real
->lock
);
378 p_atomic_set(&real
->cpu_ptr
, cpu
);
380 simple_mtx_unlock(&real
->lock
);
384 return (uint8_t*)cpu
+ offset
;
387 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
389 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
390 struct amdgpu_winsys_bo
*real
;
397 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
398 assert(real
->u
.real
.map_count
!= 0 && "too many unmaps");
399 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
400 assert(!real
->cpu_ptr
&&
401 "too many unmaps or forgot RADEON_TRANSFER_TEMPORARY flag");
403 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
404 real
->ws
->mapped_vram
-= real
->base
.size
;
405 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
406 real
->ws
->mapped_gtt
-= real
->base
.size
;
407 real
->ws
->num_mapped_buffers
--;
410 amdgpu_bo_cpu_unmap(real
->bo
);
413 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
414 amdgpu_bo_destroy_or_cache
415 /* other functions are never called */
418 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
420 struct amdgpu_winsys
*ws
= bo
->ws
;
424 if (ws
->debug_all_bos
) {
425 simple_mtx_lock(&ws
->global_bo_list_lock
);
426 list_addtail(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
428 simple_mtx_unlock(&ws
->global_bo_list_lock
);
432 static uint64_t amdgpu_get_optimal_vm_alignment(struct amdgpu_winsys
*ws
,
433 uint64_t size
, unsigned alignment
)
435 uint64_t vm_alignment
= alignment
;
437 /* Increase the VM alignment for faster address translation. */
438 if (size
>= ws
->info
.pte_fragment_size
)
439 vm_alignment
= MAX2(vm_alignment
, ws
->info
.pte_fragment_size
);
441 /* Gfx9: Increase the VM alignment to the most significant bit set
442 * in the size for faster address translation.
444 if (ws
->info
.chip_class
>= GFX9
) {
445 unsigned msb
= util_last_bit64(size
); /* 0 = no bit is set */
446 uint64_t msb_alignment
= msb
? 1ull << (msb
- 1) : 0;
448 vm_alignment
= MAX2(vm_alignment
, msb_alignment
);
453 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
456 enum radeon_bo_domain initial_domain
,
460 struct amdgpu_bo_alloc_request request
= {0};
461 amdgpu_bo_handle buf_handle
;
463 struct amdgpu_winsys_bo
*bo
;
464 amdgpu_va_handle va_handle
;
467 /* VRAM or GTT must be specified, but not both at the same time. */
468 assert(util_bitcount(initial_domain
& (RADEON_DOMAIN_VRAM_GTT
|
470 RADEON_DOMAIN_OA
)) == 1);
472 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
478 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
481 request
.alloc_size
= size
;
482 request
.phys_alignment
= alignment
;
484 if (initial_domain
& RADEON_DOMAIN_VRAM
) {
485 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
487 /* Since VRAM and GTT have almost the same performance on APUs, we could
488 * just set GTT. However, in order to decrease GTT(RAM) usage, which is
489 * shared with the OS, allow VRAM placements too. The idea is not to use
490 * VRAM usefully, but to use it so that it's not unused and wasted.
492 if (!ws
->info
.has_dedicated_vram
)
493 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
496 if (initial_domain
& RADEON_DOMAIN_GTT
)
497 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
498 if (initial_domain
& RADEON_DOMAIN_GDS
)
499 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GDS
;
500 if (initial_domain
& RADEON_DOMAIN_OA
)
501 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_OA
;
503 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
504 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
505 if (flags
& RADEON_FLAG_GTT_WC
)
506 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
507 if (flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
508 ws
->info
.has_local_buffers
)
509 request
.flags
|= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
;
510 if (ws
->zero_all_vram_allocs
&&
511 (request
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
))
512 request
.flags
|= AMDGPU_GEM_CREATE_VRAM_CLEARED
;
514 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
516 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
517 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
518 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
519 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
523 if (initial_domain
& RADEON_DOMAIN_VRAM_GTT
) {
524 unsigned va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
526 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
528 amdgpu_get_optimal_vm_alignment(ws
, size
, alignment
),
530 (flags
& RADEON_FLAG_32BIT
? AMDGPU_VA_RANGE_32_BIT
: 0) |
531 AMDGPU_VA_RANGE_HIGH
);
535 unsigned vm_flags
= AMDGPU_VM_PAGE_READABLE
|
536 AMDGPU_VM_PAGE_EXECUTABLE
;
538 if (!(flags
& RADEON_FLAG_READ_ONLY
))
539 vm_flags
|= AMDGPU_VM_PAGE_WRITEABLE
;
541 r
= amdgpu_bo_va_op_raw(ws
->dev
, buf_handle
, 0, size
, va
, vm_flags
,
547 simple_mtx_init(&bo
->lock
, mtx_plain
);
548 pipe_reference_init(&bo
->base
.reference
, 1);
549 bo
->base
.alignment
= alignment
;
551 bo
->base
.size
= size
;
552 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
556 bo
->u
.real
.va_handle
= va_handle
;
557 bo
->initial_domain
= initial_domain
;
558 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
559 bo
->is_local
= !!(request
.flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
);
561 if (initial_domain
& RADEON_DOMAIN_VRAM
)
562 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
563 else if (initial_domain
& RADEON_DOMAIN_GTT
)
564 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
566 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
568 amdgpu_add_buffer_to_global_list(bo
);
573 amdgpu_va_range_free(va_handle
);
576 amdgpu_bo_free(buf_handle
);
583 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
585 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
587 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
591 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
594 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
596 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
597 bo
= container_of(entry
, bo
, u
.slab
.entry
);
599 return amdgpu_bo_can_reclaim(&bo
->base
);
602 static struct pb_slabs
*get_slabs(struct amdgpu_winsys
*ws
, uint64_t size
)
604 /* Find the correct slab allocator for the given size. */
605 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
606 struct pb_slabs
*slabs
= &ws
->bo_slabs
[i
];
608 if (size
<= 1 << (slabs
->min_order
+ slabs
->num_orders
- 1))
616 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
618 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
622 pb_slab_free(get_slabs(bo
->ws
, bo
->base
.size
), &bo
->u
.slab
.entry
);
625 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
626 amdgpu_bo_slab_destroy
627 /* other functions are never called */
630 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
632 unsigned group_index
)
634 struct amdgpu_winsys
*ws
= priv
;
635 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
636 enum radeon_bo_domain domains
= radeon_domain_from_heap(heap
);
637 enum radeon_bo_flag flags
= radeon_flags_from_heap(heap
);
639 unsigned slab_size
= 0;
644 /* Determine the slab buffer size. */
645 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
646 struct pb_slabs
*slabs
= &ws
->bo_slabs
[i
];
647 unsigned max_entry_size
= 1 << (slabs
->min_order
+ slabs
->num_orders
- 1);
649 if (entry_size
<= max_entry_size
) {
650 /* The slab size is twice the size of the largest possible entry. */
651 slab_size
= max_entry_size
* 2;
653 /* The largest slab should have the same size as the PTE fragment
654 * size to get faster address translation.
656 if (i
== NUM_SLAB_ALLOCATORS
- 1 &&
657 slab_size
< ws
->info
.pte_fragment_size
)
658 slab_size
= ws
->info
.pte_fragment_size
;
662 assert(slab_size
!= 0);
664 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(ws
,
665 slab_size
, slab_size
,
670 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
671 slab
->base
.num_free
= slab
->base
.num_entries
;
672 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
676 list_inithead(&slab
->base
.free
);
678 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
680 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
681 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
683 simple_mtx_init(&bo
->lock
, mtx_plain
);
684 bo
->base
.alignment
= entry_size
;
685 bo
->base
.usage
= slab
->buffer
->base
.usage
;
686 bo
->base
.size
= entry_size
;
687 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
689 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
690 bo
->initial_domain
= domains
;
691 bo
->unique_id
= base_id
+ i
;
692 bo
->u
.slab
.entry
.slab
= &slab
->base
;
693 bo
->u
.slab
.entry
.group_index
= group_index
;
695 if (slab
->buffer
->bo
) {
696 /* The slab is not suballocated. */
697 bo
->u
.slab
.real
= slab
->buffer
;
699 /* The slab is allocated out of a bigger slab. */
700 bo
->u
.slab
.real
= slab
->buffer
->u
.slab
.real
;
701 assert(bo
->u
.slab
.real
->bo
);
704 list_addtail(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
710 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
716 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
718 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
720 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
721 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
722 simple_mtx_destroy(&slab
->entries
[i
].lock
);
726 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
730 #if DEBUG_SPARSE_COMMITS
732 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
734 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
736 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
738 struct amdgpu_sparse_backing
*span_backing
= NULL
;
739 uint32_t span_first_backing_page
= 0;
740 uint32_t span_first_va_page
= 0;
741 uint32_t va_page
= 0;
744 struct amdgpu_sparse_backing
*backing
= 0;
745 uint32_t backing_page
= 0;
747 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
748 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
749 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
753 (backing
!= span_backing
||
754 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
755 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
756 span_first_va_page
, va_page
- 1, span_backing
,
757 span_first_backing_page
,
758 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
763 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
766 if (backing
&& !span_backing
) {
767 span_backing
= backing
;
768 span_first_backing_page
= backing_page
;
769 span_first_va_page
= va_page
;
775 fprintf(stderr
, "Backing:\n");
777 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
778 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
779 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
780 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
786 * Attempt to allocate the given number of backing pages. Fewer pages may be
787 * allocated (depending on the fragmentation of existing backing buffers),
788 * which will be reflected by a change to *pnum_pages.
790 static struct amdgpu_sparse_backing
*
791 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
793 struct amdgpu_sparse_backing
*best_backing
;
795 uint32_t best_num_pages
;
801 /* This is a very simple and inefficient best-fit algorithm. */
802 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
803 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
804 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
805 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
806 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
807 best_backing
= backing
;
809 best_num_pages
= cur_num_pages
;
814 /* Allocate a new backing buffer if necessary. */
816 struct pb_buffer
*buf
;
820 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
824 best_backing
->max_chunks
= 4;
825 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
826 sizeof(*best_backing
->chunks
));
827 if (!best_backing
->chunks
) {
832 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
834 size
= MIN3(bo
->base
.size
/ 16,
836 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
837 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
839 buf
= amdgpu_bo_create(bo
->ws
, size
, RADEON_SPARSE_PAGE_SIZE
,
841 bo
->u
.sparse
.flags
| RADEON_FLAG_NO_SUBALLOC
);
843 FREE(best_backing
->chunks
);
848 /* We might have gotten a bigger buffer than requested via caching. */
849 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
851 best_backing
->bo
= amdgpu_winsys_bo(buf
);
852 best_backing
->num_chunks
= 1;
853 best_backing
->chunks
[0].begin
= 0;
854 best_backing
->chunks
[0].end
= pages
;
856 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
857 bo
->u
.sparse
.num_backing_pages
+= pages
;
860 best_num_pages
= pages
;
863 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
864 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
865 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
867 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
868 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
869 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
870 best_backing
->num_chunks
--;
877 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
878 struct amdgpu_sparse_backing
*backing
)
880 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
882 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
884 simple_mtx_lock(&ws
->bo_fence_lock
);
885 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
886 simple_mtx_unlock(&ws
->bo_fence_lock
);
888 list_del(&backing
->list
);
889 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
890 FREE(backing
->chunks
);
895 * Return a range of pages from the given backing buffer back into the
899 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
900 struct amdgpu_sparse_backing
*backing
,
901 uint32_t start_page
, uint32_t num_pages
)
903 uint32_t end_page
= start_page
+ num_pages
;
905 unsigned high
= backing
->num_chunks
;
907 /* Find the first chunk with begin >= start_page. */
909 unsigned mid
= low
+ (high
- low
) / 2;
911 if (backing
->chunks
[mid
].begin
>= start_page
)
917 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
918 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
920 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
921 backing
->chunks
[low
- 1].end
= end_page
;
923 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
924 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
925 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
926 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
927 backing
->num_chunks
--;
929 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
930 backing
->chunks
[low
].begin
= start_page
;
932 if (backing
->num_chunks
>= backing
->max_chunks
) {
933 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
934 struct amdgpu_sparse_backing_chunk
*new_chunks
=
935 REALLOC(backing
->chunks
,
936 sizeof(*backing
->chunks
) * backing
->max_chunks
,
937 sizeof(*backing
->chunks
) * new_max_chunks
);
941 backing
->max_chunks
= new_max_chunks
;
942 backing
->chunks
= new_chunks
;
945 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
946 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
947 backing
->chunks
[low
].begin
= start_page
;
948 backing
->chunks
[low
].end
= end_page
;
949 backing
->num_chunks
++;
952 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
953 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
954 sparse_free_backing_buffer(bo
, backing
);
959 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
961 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
964 assert(!bo
->bo
&& bo
->sparse
);
966 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
967 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
968 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
970 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
973 while (!list_is_empty(&bo
->u
.sparse
.backing
)) {
974 struct amdgpu_sparse_backing
*dummy
= NULL
;
975 sparse_free_backing_buffer(bo
,
976 container_of(bo
->u
.sparse
.backing
.next
,
980 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
981 FREE(bo
->u
.sparse
.commitments
);
982 simple_mtx_destroy(&bo
->lock
);
986 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
987 amdgpu_bo_sparse_destroy
988 /* other functions are never called */
991 static struct pb_buffer
*
992 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
993 enum radeon_bo_domain domain
,
994 enum radeon_bo_flag flags
)
996 struct amdgpu_winsys_bo
*bo
;
998 uint64_t va_gap_size
;
1001 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
1002 * that exceed this limit. This is not really a restriction: we don't have
1003 * that much virtual address space anyway.
1005 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
1008 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1012 simple_mtx_init(&bo
->lock
, mtx_plain
);
1013 pipe_reference_init(&bo
->base
.reference
, 1);
1014 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
1015 bo
->base
.size
= size
;
1016 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
1018 bo
->initial_domain
= domain
;
1019 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1021 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
1023 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
1024 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
1025 sizeof(*bo
->u
.sparse
.commitments
));
1026 if (!bo
->u
.sparse
.commitments
)
1027 goto error_alloc_commitments
;
1029 list_inithead(&bo
->u
.sparse
.backing
);
1031 /* For simplicity, we always map a multiple of the page size. */
1032 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
1033 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
1034 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1035 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
1036 0, &bo
->va
, &bo
->u
.sparse
.va_handle
,
1037 AMDGPU_VA_RANGE_HIGH
);
1039 goto error_va_alloc
;
1041 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
1042 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
1049 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
1051 FREE(bo
->u
.sparse
.commitments
);
1052 error_alloc_commitments
:
1053 simple_mtx_destroy(&bo
->lock
);
1059 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
1062 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
1063 struct amdgpu_sparse_commitment
*comm
;
1064 uint32_t va_page
, end_va_page
;
1069 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
1070 assert(offset
<= bo
->base
.size
);
1071 assert(size
<= bo
->base
.size
- offset
);
1072 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
1074 comm
= bo
->u
.sparse
.commitments
;
1075 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
1076 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
1078 simple_mtx_lock(&bo
->lock
);
1080 #if DEBUG_SPARSE_COMMITS
1081 sparse_dump(bo
, __func__
);
1085 while (va_page
< end_va_page
) {
1086 uint32_t span_va_page
;
1088 /* Skip pages that are already committed. */
1089 if (comm
[va_page
].backing
) {
1094 /* Determine length of uncommitted span. */
1095 span_va_page
= va_page
;
1096 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
1099 /* Fill the uncommitted span with chunks of backing memory. */
1100 while (span_va_page
< va_page
) {
1101 struct amdgpu_sparse_backing
*backing
;
1102 uint32_t backing_start
, backing_size
;
1104 backing_size
= va_page
- span_va_page
;
1105 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
1111 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
1112 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
1113 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
1114 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
1115 AMDGPU_VM_PAGE_READABLE
|
1116 AMDGPU_VM_PAGE_WRITEABLE
|
1117 AMDGPU_VM_PAGE_EXECUTABLE
,
1118 AMDGPU_VA_OP_REPLACE
);
1120 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
1121 assert(ok
&& "sufficient memory should already be allocated");
1127 while (backing_size
) {
1128 comm
[span_va_page
].backing
= backing
;
1129 comm
[span_va_page
].page
= backing_start
;
1137 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
1138 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
1139 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
1140 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
1146 while (va_page
< end_va_page
) {
1147 struct amdgpu_sparse_backing
*backing
;
1148 uint32_t backing_start
;
1149 uint32_t span_pages
;
1151 /* Skip pages that are already uncommitted. */
1152 if (!comm
[va_page
].backing
) {
1157 /* Group contiguous spans of pages. */
1158 backing
= comm
[va_page
].backing
;
1159 backing_start
= comm
[va_page
].page
;
1160 comm
[va_page
].backing
= NULL
;
1165 while (va_page
< end_va_page
&&
1166 comm
[va_page
].backing
== backing
&&
1167 comm
[va_page
].page
== backing_start
+ span_pages
) {
1168 comm
[va_page
].backing
= NULL
;
1173 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1174 /* Couldn't allocate tracking data structures, so we have to leak */
1175 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1182 simple_mtx_unlock(&bo
->lock
);
1187 static unsigned eg_tile_split(unsigned tile_split
)
1189 switch (tile_split
) {
1190 case 0: tile_split
= 64; break;
1191 case 1: tile_split
= 128; break;
1192 case 2: tile_split
= 256; break;
1193 case 3: tile_split
= 512; break;
1195 case 4: tile_split
= 1024; break;
1196 case 5: tile_split
= 2048; break;
1197 case 6: tile_split
= 4096; break;
1202 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1204 switch (eg_tile_split
) {
1210 case 1024: return 4;
1211 case 2048: return 5;
1212 case 4096: return 6;
1216 #define AMDGPU_TILING_SCANOUT_SHIFT 63
1217 #define AMDGPU_TILING_SCANOUT_MASK 0x1
1219 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1220 struct radeon_bo_metadata
*md
)
1222 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1223 struct amdgpu_bo_info info
= {0};
1224 uint64_t tiling_flags
;
1227 assert(bo
->bo
&& "must not be called for slab entries");
1229 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1233 tiling_flags
= info
.metadata
.tiling_info
;
1235 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1236 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1238 md
->u
.gfx9
.dcc_offset_256B
= AMDGPU_TILING_GET(tiling_flags
, DCC_OFFSET_256B
);
1239 md
->u
.gfx9
.dcc_pitch_max
= AMDGPU_TILING_GET(tiling_flags
, DCC_PITCH_MAX
);
1240 md
->u
.gfx9
.dcc_independent_64B
= AMDGPU_TILING_GET(tiling_flags
, DCC_INDEPENDENT_64B
);
1241 md
->u
.gfx9
.scanout
= AMDGPU_TILING_GET(tiling_flags
, SCANOUT
);
1243 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1244 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1246 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1247 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1248 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1249 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1251 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1252 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1253 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1254 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1255 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1256 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1257 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1260 md
->size_metadata
= info
.metadata
.size_metadata
;
1261 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1264 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1265 struct radeon_bo_metadata
*md
)
1267 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1268 struct amdgpu_bo_metadata metadata
= {0};
1269 uint64_t tiling_flags
= 0;
1271 assert(bo
->bo
&& "must not be called for slab entries");
1273 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1274 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1276 tiling_flags
|= AMDGPU_TILING_SET(DCC_OFFSET_256B
, md
->u
.gfx9
.dcc_offset_256B
);
1277 tiling_flags
|= AMDGPU_TILING_SET(DCC_PITCH_MAX
, md
->u
.gfx9
.dcc_pitch_max
);
1278 tiling_flags
|= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B
, md
->u
.gfx9
.dcc_independent_64B
);
1279 tiling_flags
|= AMDGPU_TILING_SET(SCANOUT
, md
->u
.gfx9
.scanout
);
1281 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1282 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1283 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1284 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1286 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1288 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1289 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1290 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1291 if (md
->u
.legacy
.tile_split
)
1292 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1293 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1294 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1296 if (md
->u
.legacy
.scanout
)
1297 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1299 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1302 metadata
.tiling_info
= tiling_flags
;
1303 metadata
.size_metadata
= md
->size_metadata
;
1304 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1306 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1310 amdgpu_bo_create(struct amdgpu_winsys
*ws
,
1313 enum radeon_bo_domain domain
,
1314 enum radeon_bo_flag flags
)
1316 struct amdgpu_winsys_bo
*bo
;
1319 if (domain
& (RADEON_DOMAIN_GDS
| RADEON_DOMAIN_OA
))
1320 flags
|= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_SUBALLOC
;
1322 /* VRAM implies WC. This is not optional. */
1323 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
1325 /* NO_CPU_ACCESS is not valid with GTT. */
1326 assert(!(domain
& RADEON_DOMAIN_GTT
) || !(flags
& RADEON_FLAG_NO_CPU_ACCESS
));
1328 /* Sparse buffers must have NO_CPU_ACCESS set. */
1329 assert(!(flags
& RADEON_FLAG_SPARSE
) || flags
& RADEON_FLAG_NO_CPU_ACCESS
);
1331 struct pb_slabs
*last_slab
= &ws
->bo_slabs
[NUM_SLAB_ALLOCATORS
- 1];
1332 unsigned max_slab_entry_size
= 1 << (last_slab
->min_order
+ last_slab
->num_orders
- 1);
1334 /* Sub-allocate small buffers from slabs. */
1335 if (!(flags
& (RADEON_FLAG_NO_SUBALLOC
| RADEON_FLAG_SPARSE
)) &&
1336 size
<= max_slab_entry_size
&&
1337 /* The alignment must be at most the size of the smallest slab entry or
1338 * the next power of two. */
1339 alignment
<= MAX2(1 << ws
->bo_slabs
[0].min_order
, util_next_power_of_two(size
))) {
1340 struct pb_slab_entry
*entry
;
1341 int heap
= radeon_get_heap_index(domain
, flags
);
1343 if (heap
< 0 || heap
>= RADEON_MAX_SLAB_HEAPS
)
1346 struct pb_slabs
*slabs
= get_slabs(ws
, size
);
1347 entry
= pb_slab_alloc(slabs
, size
, heap
);
1349 /* Clean up buffer managers and try again. */
1350 amdgpu_clean_up_buffer_managers(ws
);
1352 entry
= pb_slab_alloc(slabs
, size
, heap
);
1358 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1360 pipe_reference_init(&bo
->base
.reference
, 1);
1366 if (flags
& RADEON_FLAG_SPARSE
) {
1367 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1369 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1372 /* This flag is irrelevant for the cache. */
1373 flags
&= ~RADEON_FLAG_NO_SUBALLOC
;
1375 /* Align size to page size. This is the minimum alignment for normal
1376 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1377 * like constant/uniform buffers, can benefit from better and more reuse.
1379 if (domain
& RADEON_DOMAIN_VRAM_GTT
) {
1380 size
= align64(size
, ws
->info
.gart_page_size
);
1381 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1384 bool use_reusable_pool
= flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1386 if (use_reusable_pool
) {
1387 heap
= radeon_get_heap_index(domain
, flags
);
1388 assert(heap
>= 0 && heap
< RADEON_MAX_CACHED_HEAPS
);
1390 /* Get a buffer from the cache. */
1391 bo
= (struct amdgpu_winsys_bo
*)
1392 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, 0, heap
);
1397 /* Create a new one. */
1398 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1400 /* Clean up buffer managers and try again. */
1401 amdgpu_clean_up_buffer_managers(ws
);
1403 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1408 bo
->u
.real
.use_reusable_pool
= use_reusable_pool
;
1412 static struct pb_buffer
*
1413 amdgpu_buffer_create(struct radeon_winsys
*ws
,
1416 enum radeon_bo_domain domain
,
1417 enum radeon_bo_flag flags
)
1419 return amdgpu_bo_create(amdgpu_winsys(ws
), size
, alignment
, domain
,
1423 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1424 struct winsys_handle
*whandle
,
1425 unsigned vm_alignment
)
1427 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1428 struct amdgpu_winsys_bo
*bo
= NULL
;
1429 enum amdgpu_bo_handle_type type
;
1430 struct amdgpu_bo_import_result result
= {0};
1432 amdgpu_va_handle va_handle
= NULL
;
1433 struct amdgpu_bo_info info
= {0};
1434 enum radeon_bo_domain initial
= 0;
1437 switch (whandle
->type
) {
1438 case WINSYS_HANDLE_TYPE_SHARED
:
1439 type
= amdgpu_bo_handle_type_gem_flink_name
;
1441 case WINSYS_HANDLE_TYPE_FD
:
1442 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1448 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1452 simple_mtx_lock(&ws
->bo_export_table_lock
);
1453 bo
= util_hash_table_get(ws
->bo_export_table
, result
.buf_handle
);
1455 /* If the amdgpu_winsys_bo instance already exists, bump the reference
1456 * counter and return it.
1459 p_atomic_inc(&bo
->base
.reference
.count
);
1460 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1462 /* Release the buffer handle, because we don't need it anymore.
1463 * This function is returning an existing buffer, which has its own
1466 amdgpu_bo_free(result
.buf_handle
);
1470 /* Get initial domains. */
1471 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1475 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1477 amdgpu_get_optimal_vm_alignment(ws
, result
.alloc_size
,
1479 0, &va
, &va_handle
, AMDGPU_VA_RANGE_HIGH
);
1483 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1487 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1491 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1492 initial
|= RADEON_DOMAIN_VRAM
;
1493 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1494 initial
|= RADEON_DOMAIN_GTT
;
1496 /* Initialize the structure. */
1497 simple_mtx_init(&bo
->lock
, mtx_plain
);
1498 pipe_reference_init(&bo
->base
.reference
, 1);
1499 bo
->base
.alignment
= info
.phys_alignment
;
1500 bo
->bo
= result
.buf_handle
;
1501 bo
->base
.size
= result
.alloc_size
;
1502 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1505 bo
->u
.real
.va_handle
= va_handle
;
1506 bo
->initial_domain
= initial
;
1507 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1508 bo
->is_shared
= true;
1510 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1511 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1512 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1513 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1515 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1517 amdgpu_add_buffer_to_global_list(bo
);
1519 util_hash_table_set(ws
->bo_export_table
, bo
->bo
, bo
);
1520 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1525 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1529 amdgpu_va_range_free(va_handle
);
1530 amdgpu_bo_free(result
.buf_handle
);
1534 static bool amdgpu_bo_get_handle(struct radeon_winsys
*rws
,
1535 struct pb_buffer
*buffer
,
1536 struct winsys_handle
*whandle
)
1538 struct amdgpu_screen_winsys
*sws
= amdgpu_screen_winsys(rws
);
1539 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1540 struct amdgpu_winsys
*ws
= bo
->ws
;
1541 enum amdgpu_bo_handle_type type
;
1542 struct hash_entry
*entry
;
1545 /* Don't allow exports of slab entries and sparse buffers. */
1549 bo
->u
.real
.use_reusable_pool
= false;
1551 switch (whandle
->type
) {
1552 case WINSYS_HANDLE_TYPE_SHARED
:
1553 type
= amdgpu_bo_handle_type_gem_flink_name
;
1555 case WINSYS_HANDLE_TYPE_KMS
:
1556 if (sws
->fd
== ws
->fd
) {
1557 whandle
->handle
= bo
->u
.real
.kms_handle
;
1562 goto hash_table_set
;
1565 simple_mtx_lock(&ws
->sws_list_lock
);
1566 entry
= _mesa_hash_table_search(sws
->kms_handles
, bo
);
1567 simple_mtx_unlock(&ws
->sws_list_lock
);
1569 whandle
->handle
= (uintptr_t)entry
->data
;
1573 case WINSYS_HANDLE_TYPE_FD
:
1574 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1580 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1584 if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
1585 int dma_fd
= whandle
->handle
;
1587 r
= drmPrimeFDToHandle(sws
->fd
, dma_fd
, &whandle
->handle
);
1593 simple_mtx_lock(&ws
->sws_list_lock
);
1594 _mesa_hash_table_insert_pre_hashed(sws
->kms_handles
,
1595 bo
->u
.real
.kms_handle
, bo
,
1596 (void*)(uintptr_t)whandle
->handle
);
1597 simple_mtx_unlock(&ws
->sws_list_lock
);
1601 simple_mtx_lock(&ws
->bo_export_table_lock
);
1602 util_hash_table_set(ws
->bo_export_table
, bo
->bo
, bo
);
1603 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1605 bo
->is_shared
= true;
1609 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1610 void *pointer
, uint64_t size
)
1612 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1613 amdgpu_bo_handle buf_handle
;
1614 struct amdgpu_winsys_bo
*bo
;
1616 amdgpu_va_handle va_handle
;
1617 /* Avoid failure when the size is not page aligned */
1618 uint64_t aligned_size
= align64(size
, ws
->info
.gart_page_size
);
1620 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1624 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
,
1625 aligned_size
, &buf_handle
))
1628 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1630 amdgpu_get_optimal_vm_alignment(ws
, aligned_size
,
1631 ws
->info
.gart_page_size
),
1632 0, &va
, &va_handle
, AMDGPU_VA_RANGE_HIGH
))
1633 goto error_va_alloc
;
1635 if (amdgpu_bo_va_op(buf_handle
, 0, aligned_size
, va
, 0, AMDGPU_VA_OP_MAP
))
1638 /* Initialize it. */
1639 bo
->is_user_ptr
= true;
1640 pipe_reference_init(&bo
->base
.reference
, 1);
1641 simple_mtx_init(&bo
->lock
, mtx_plain
);
1642 bo
->bo
= buf_handle
;
1643 bo
->base
.alignment
= 0;
1644 bo
->base
.size
= size
;
1645 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1647 bo
->cpu_ptr
= pointer
;
1649 bo
->u
.real
.va_handle
= va_handle
;
1650 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1651 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1653 ws
->allocated_gtt
+= aligned_size
;
1655 amdgpu_add_buffer_to_global_list(bo
);
1657 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1659 return (struct pb_buffer
*)bo
;
1662 amdgpu_va_range_free(va_handle
);
1665 amdgpu_bo_free(buf_handle
);
1672 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1674 return ((struct amdgpu_winsys_bo
*)buf
)->is_user_ptr
;
1677 static bool amdgpu_bo_is_suballocated(struct pb_buffer
*buf
)
1679 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
1681 return !bo
->bo
&& !bo
->sparse
;
1684 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1686 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1689 void amdgpu_bo_init_functions(struct amdgpu_screen_winsys
*ws
)
1691 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1692 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1693 ws
->base
.buffer_map
= amdgpu_bo_map
;
1694 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1695 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1696 ws
->base
.buffer_create
= amdgpu_buffer_create
;
1697 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1698 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1699 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1700 ws
->base
.buffer_is_suballocated
= amdgpu_bo_is_suballocated
;
1701 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1702 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1703 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1704 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;