2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
31 #include "state_tracker/drm_driver.h"
32 #include <amdgpu_drm.h>
37 #ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
38 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
41 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
42 #define DEBUG_SPARSE_COMMITS 0
44 struct amdgpu_sparse_backing_chunk
{
48 static struct pb_buffer
*
49 amdgpu_bo_create(struct radeon_winsys
*rws
,
52 enum radeon_bo_domain domain
,
53 enum radeon_bo_flag flags
);
55 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
56 enum radeon_bo_usage usage
)
58 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
59 struct amdgpu_winsys
*ws
= bo
->ws
;
63 if (p_atomic_read(&bo
->num_active_ioctls
))
67 abs_timeout
= os_time_get_absolute_timeout(timeout
);
69 /* Wait if any ioctl is being submitted with this buffer. */
70 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
75 /* We can't use user fences for shared buffers, because user fences
76 * are local to this process only. If we want to wait for all buffer
77 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
79 bool buffer_busy
= true;
82 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
84 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
93 simple_mtx_lock(&ws
->bo_fence_lock
);
95 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
96 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
100 /* Release the idle fences to avoid checking them again later. */
101 for (unsigned i
= 0; i
< idle_fences
; ++i
)
102 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
104 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
105 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
106 bo
->num_fences
-= idle_fences
;
108 buffer_idle
= !bo
->num_fences
;
109 simple_mtx_unlock(&ws
->bo_fence_lock
);
113 bool buffer_idle
= true;
115 simple_mtx_lock(&ws
->bo_fence_lock
);
116 while (bo
->num_fences
&& buffer_idle
) {
117 struct pipe_fence_handle
*fence
= NULL
;
118 bool fence_idle
= false;
120 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
122 /* Wait for the fence. */
123 simple_mtx_unlock(&ws
->bo_fence_lock
);
124 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
128 simple_mtx_lock(&ws
->bo_fence_lock
);
130 /* Release an idle fence to avoid checking it again later, keeping in
131 * mind that the fence array may have been modified by other threads.
133 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
134 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
135 memmove(&bo
->fences
[0], &bo
->fences
[1],
136 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
140 amdgpu_fence_reference(&fence
, NULL
);
142 simple_mtx_unlock(&ws
->bo_fence_lock
);
148 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
149 struct pb_buffer
*buf
)
151 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
154 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
156 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
157 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
164 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
166 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
168 assert(bo
->bo
&& "must not be called for slab entries");
170 if (bo
->ws
->debug_all_bos
) {
171 simple_mtx_lock(&bo
->ws
->global_bo_list_lock
);
172 LIST_DEL(&bo
->u
.real
.global_list_item
);
173 bo
->ws
->num_buffers
--;
174 simple_mtx_unlock(&bo
->ws
->global_bo_list_lock
);
177 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
178 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
179 amdgpu_bo_free(bo
->bo
);
181 amdgpu_bo_remove_fences(bo
);
183 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
184 bo
->ws
->allocated_vram
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
185 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
186 bo
->ws
->allocated_gtt
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
188 if (bo
->u
.real
.map_count
>= 1) {
189 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
190 bo
->ws
->mapped_vram
-= bo
->base
.size
;
191 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
192 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
193 bo
->ws
->num_mapped_buffers
--;
199 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
201 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
203 assert(bo
->bo
); /* slab buffers have a separate vtbl */
205 if (bo
->u
.real
.use_reusable_pool
)
206 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
208 amdgpu_bo_destroy(_buf
);
211 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
212 struct radeon_winsys_cs
*rcs
,
213 enum pipe_transfer_usage usage
)
215 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
216 struct amdgpu_winsys_bo
*real
;
217 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
224 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
225 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
226 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
227 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
228 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
231 * Since we are mapping for read, we don't need to wait
232 * if the GPU is using the buffer for read too
233 * (neither one is changing it).
235 * Only check whether the buffer is being used for write. */
236 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
237 RADEON_USAGE_WRITE
)) {
238 cs
->flush_cs(cs
->flush_data
, PIPE_FLUSH_ASYNC
, NULL
);
242 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
243 RADEON_USAGE_WRITE
)) {
247 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
248 cs
->flush_cs(cs
->flush_data
, PIPE_FLUSH_ASYNC
, NULL
);
252 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
253 RADEON_USAGE_READWRITE
)) {
258 uint64_t time
= os_time_get_nano();
260 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
263 * Since we are mapping for read, we don't need to wait
264 * if the GPU is using the buffer for read too
265 * (neither one is changing it).
267 * Only check whether the buffer is being used for write. */
269 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
270 RADEON_USAGE_WRITE
)) {
271 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
273 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
274 if (p_atomic_read(&bo
->num_active_ioctls
))
275 amdgpu_cs_sync_flush(rcs
);
279 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
282 /* Mapping for write. */
284 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
285 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
287 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
288 if (p_atomic_read(&bo
->num_active_ioctls
))
289 amdgpu_cs_sync_flush(rcs
);
293 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
294 RADEON_USAGE_READWRITE
);
297 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
301 /* If the buffer is created from user memory, return the user pointer. */
308 real
= bo
->u
.slab
.real
;
309 offset
= bo
->va
- real
->va
;
312 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
314 /* Clear the cache and try again. */
315 pb_cache_release_all_buffers(&real
->ws
->bo_cache
);
316 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
321 if (p_atomic_inc_return(&real
->u
.real
.map_count
) == 1) {
322 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
323 real
->ws
->mapped_vram
+= real
->base
.size
;
324 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
325 real
->ws
->mapped_gtt
+= real
->base
.size
;
326 real
->ws
->num_mapped_buffers
++;
328 return (uint8_t*)cpu
+ offset
;
331 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
333 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
334 struct amdgpu_winsys_bo
*real
;
341 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
343 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
344 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
345 real
->ws
->mapped_vram
-= real
->base
.size
;
346 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
347 real
->ws
->mapped_gtt
-= real
->base
.size
;
348 real
->ws
->num_mapped_buffers
--;
351 amdgpu_bo_cpu_unmap(real
->bo
);
354 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
355 amdgpu_bo_destroy_or_cache
356 /* other functions are never called */
359 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
361 struct amdgpu_winsys
*ws
= bo
->ws
;
365 if (ws
->debug_all_bos
) {
366 simple_mtx_lock(&ws
->global_bo_list_lock
);
367 LIST_ADDTAIL(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
369 simple_mtx_unlock(&ws
->global_bo_list_lock
);
373 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
377 enum radeon_bo_domain initial_domain
,
379 unsigned pb_cache_bucket
)
381 struct amdgpu_bo_alloc_request request
= {0};
382 amdgpu_bo_handle buf_handle
;
384 struct amdgpu_winsys_bo
*bo
;
385 amdgpu_va_handle va_handle
;
386 unsigned va_gap_size
;
389 /* VRAM or GTT must be specified, but not both at the same time. */
390 assert(util_bitcount(initial_domain
& RADEON_DOMAIN_VRAM_GTT
) == 1);
392 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
397 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
399 request
.alloc_size
= size
;
400 request
.phys_alignment
= alignment
;
402 if (initial_domain
& RADEON_DOMAIN_VRAM
)
403 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
404 if (initial_domain
& RADEON_DOMAIN_GTT
)
405 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
407 /* If VRAM is just stolen system memory, allow both VRAM and
408 * GTT, whichever has free space. If a buffer is evicted from
409 * VRAM to GTT, it will stay there.
411 * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
412 * placements even with a low amount of stolen VRAM.
414 if (!ws
->info
.has_dedicated_vram
&& ws
->info
.drm_minor
< 6)
415 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
417 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
418 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
419 if (flags
& RADEON_FLAG_GTT_WC
)
420 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
421 if (flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
422 ws
->info
.drm_minor
>= 20)
423 request
.flags
|= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
;
425 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
427 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
428 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
429 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
430 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
434 va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
435 if (size
> ws
->info
.pte_fragment_size
)
436 alignment
= MAX2(alignment
, ws
->info
.pte_fragment_size
);
437 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
438 size
+ va_gap_size
, alignment
, 0, &va
, &va_handle
, 0);
442 unsigned vm_flags
= AMDGPU_VM_PAGE_READABLE
|
443 AMDGPU_VM_PAGE_EXECUTABLE
;
445 if (!(flags
& RADEON_FLAG_READ_ONLY
))
446 vm_flags
|= AMDGPU_VM_PAGE_WRITEABLE
;
448 r
= amdgpu_bo_va_op_raw(ws
->dev
, buf_handle
, 0, size
, va
, vm_flags
,
453 pipe_reference_init(&bo
->base
.reference
, 1);
454 bo
->base
.alignment
= alignment
;
455 bo
->base
.usage
= usage
;
456 bo
->base
.size
= size
;
457 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
461 bo
->u
.real
.va_handle
= va_handle
;
462 bo
->initial_domain
= initial_domain
;
463 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
464 bo
->is_local
= !!(request
.flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
);
466 if (initial_domain
& RADEON_DOMAIN_VRAM
)
467 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
468 else if (initial_domain
& RADEON_DOMAIN_GTT
)
469 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
471 amdgpu_add_buffer_to_global_list(bo
);
476 amdgpu_va_range_free(va_handle
);
479 amdgpu_bo_free(buf_handle
);
486 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
488 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
490 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
494 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
497 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
499 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
500 bo
= container_of(entry
, bo
, u
.slab
.entry
);
502 return amdgpu_bo_can_reclaim(&bo
->base
);
505 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
507 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
511 pb_slab_free(&bo
->ws
->bo_slabs
, &bo
->u
.slab
.entry
);
514 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
515 amdgpu_bo_slab_destroy
516 /* other functions are never called */
519 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
521 unsigned group_index
)
523 struct amdgpu_winsys
*ws
= priv
;
524 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
525 enum radeon_bo_domain domains
= radeon_domain_from_heap(heap
);
526 enum radeon_bo_flag flags
= radeon_flags_from_heap(heap
);
532 unsigned slab_size
= 1 << AMDGPU_SLAB_BO_SIZE_LOG2
;
533 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(&ws
->base
,
534 slab_size
, slab_size
,
539 assert(slab
->buffer
->bo
);
541 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
542 slab
->base
.num_free
= slab
->base
.num_entries
;
543 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
547 LIST_INITHEAD(&slab
->base
.free
);
549 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
551 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
552 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
554 bo
->base
.alignment
= entry_size
;
555 bo
->base
.usage
= slab
->buffer
->base
.usage
;
556 bo
->base
.size
= entry_size
;
557 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
559 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
560 bo
->initial_domain
= domains
;
561 bo
->unique_id
= base_id
+ i
;
562 bo
->u
.slab
.entry
.slab
= &slab
->base
;
563 bo
->u
.slab
.entry
.group_index
= group_index
;
564 bo
->u
.slab
.real
= slab
->buffer
;
566 LIST_ADDTAIL(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
572 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
578 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
580 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
582 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
)
583 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
586 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
590 #if DEBUG_SPARSE_COMMITS
592 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
594 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
596 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
598 struct amdgpu_sparse_backing
*span_backing
= NULL
;
599 uint32_t span_first_backing_page
= 0;
600 uint32_t span_first_va_page
= 0;
601 uint32_t va_page
= 0;
604 struct amdgpu_sparse_backing
*backing
= 0;
605 uint32_t backing_page
= 0;
607 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
608 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
609 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
613 (backing
!= span_backing
||
614 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
615 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
616 span_first_va_page
, va_page
- 1, span_backing
,
617 span_first_backing_page
,
618 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
623 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
626 if (backing
&& !span_backing
) {
627 span_backing
= backing
;
628 span_first_backing_page
= backing_page
;
629 span_first_va_page
= va_page
;
635 fprintf(stderr
, "Backing:\n");
637 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
638 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
639 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
640 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
646 * Attempt to allocate the given number of backing pages. Fewer pages may be
647 * allocated (depending on the fragmentation of existing backing buffers),
648 * which will be reflected by a change to *pnum_pages.
650 static struct amdgpu_sparse_backing
*
651 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
653 struct amdgpu_sparse_backing
*best_backing
;
655 uint32_t best_num_pages
;
661 /* This is a very simple and inefficient best-fit algorithm. */
662 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
663 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
664 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
665 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
666 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
667 best_backing
= backing
;
669 best_num_pages
= cur_num_pages
;
674 /* Allocate a new backing buffer if necessary. */
676 struct pb_buffer
*buf
;
680 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
684 best_backing
->max_chunks
= 4;
685 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
686 sizeof(*best_backing
->chunks
));
687 if (!best_backing
->chunks
) {
692 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
694 size
= MIN3(bo
->base
.size
/ 16,
696 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
697 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
699 buf
= amdgpu_bo_create(&bo
->ws
->base
, size
, RADEON_SPARSE_PAGE_SIZE
,
701 bo
->u
.sparse
.flags
| RADEON_FLAG_NO_SUBALLOC
);
703 FREE(best_backing
->chunks
);
708 /* We might have gotten a bigger buffer than requested via caching. */
709 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
711 best_backing
->bo
= amdgpu_winsys_bo(buf
);
712 best_backing
->num_chunks
= 1;
713 best_backing
->chunks
[0].begin
= 0;
714 best_backing
->chunks
[0].end
= pages
;
716 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
717 bo
->u
.sparse
.num_backing_pages
+= pages
;
720 best_num_pages
= pages
;
723 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
724 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
725 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
727 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
728 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
729 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
730 best_backing
->num_chunks
--;
737 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
738 struct amdgpu_sparse_backing
*backing
)
740 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
742 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
744 simple_mtx_lock(&ws
->bo_fence_lock
);
745 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
746 simple_mtx_unlock(&ws
->bo_fence_lock
);
748 list_del(&backing
->list
);
749 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
750 FREE(backing
->chunks
);
755 * Return a range of pages from the given backing buffer back into the
759 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
760 struct amdgpu_sparse_backing
*backing
,
761 uint32_t start_page
, uint32_t num_pages
)
763 uint32_t end_page
= start_page
+ num_pages
;
765 unsigned high
= backing
->num_chunks
;
767 /* Find the first chunk with begin >= start_page. */
769 unsigned mid
= low
+ (high
- low
) / 2;
771 if (backing
->chunks
[mid
].begin
>= start_page
)
777 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
778 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
780 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
781 backing
->chunks
[low
- 1].end
= end_page
;
783 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
784 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
785 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
786 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
787 backing
->num_chunks
--;
789 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
790 backing
->chunks
[low
].begin
= start_page
;
792 if (backing
->num_chunks
>= backing
->max_chunks
) {
793 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
794 struct amdgpu_sparse_backing_chunk
*new_chunks
=
795 REALLOC(backing
->chunks
,
796 sizeof(*backing
->chunks
) * backing
->max_chunks
,
797 sizeof(*backing
->chunks
) * new_max_chunks
);
801 backing
->max_chunks
= new_max_chunks
;
802 backing
->chunks
= new_chunks
;
805 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
806 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
807 backing
->chunks
[low
].begin
= start_page
;
808 backing
->chunks
[low
].end
= end_page
;
809 backing
->num_chunks
++;
812 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
813 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
814 sparse_free_backing_buffer(bo
, backing
);
819 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
821 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
824 assert(!bo
->bo
&& bo
->sparse
);
826 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
827 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
828 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
830 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
833 while (!list_empty(&bo
->u
.sparse
.backing
)) {
834 struct amdgpu_sparse_backing
*dummy
= NULL
;
835 sparse_free_backing_buffer(bo
,
836 container_of(bo
->u
.sparse
.backing
.next
,
840 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
841 simple_mtx_destroy(&bo
->u
.sparse
.commit_lock
);
842 FREE(bo
->u
.sparse
.commitments
);
846 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
847 amdgpu_bo_sparse_destroy
848 /* other functions are never called */
851 static struct pb_buffer
*
852 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
853 enum radeon_bo_domain domain
,
854 enum radeon_bo_flag flags
)
856 struct amdgpu_winsys_bo
*bo
;
858 uint64_t va_gap_size
;
861 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
862 * that exceed this limit. This is not really a restriction: we don't have
863 * that much virtual address space anyway.
865 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
868 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
872 pipe_reference_init(&bo
->base
.reference
, 1);
873 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
874 bo
->base
.size
= size
;
875 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
877 bo
->initial_domain
= domain
;
878 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
880 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
882 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
883 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
884 sizeof(*bo
->u
.sparse
.commitments
));
885 if (!bo
->u
.sparse
.commitments
)
886 goto error_alloc_commitments
;
888 simple_mtx_init(&bo
->u
.sparse
.commit_lock
, mtx_plain
);
889 LIST_INITHEAD(&bo
->u
.sparse
.backing
);
891 /* For simplicity, we always map a multiple of the page size. */
892 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
893 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
894 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
895 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
896 0, &bo
->va
, &bo
->u
.sparse
.va_handle
, 0);
900 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
901 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
908 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
910 simple_mtx_destroy(&bo
->u
.sparse
.commit_lock
);
911 FREE(bo
->u
.sparse
.commitments
);
912 error_alloc_commitments
:
918 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
921 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
922 struct amdgpu_sparse_commitment
*comm
;
923 uint32_t va_page
, end_va_page
;
928 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
929 assert(offset
<= bo
->base
.size
);
930 assert(size
<= bo
->base
.size
- offset
);
931 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
933 comm
= bo
->u
.sparse
.commitments
;
934 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
935 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
937 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
939 #if DEBUG_SPARSE_COMMITS
940 sparse_dump(bo
, __func__
);
944 while (va_page
< end_va_page
) {
945 uint32_t span_va_page
;
947 /* Skip pages that are already committed. */
948 if (comm
[va_page
].backing
) {
953 /* Determine length of uncommitted span. */
954 span_va_page
= va_page
;
955 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
958 /* Fill the uncommitted span with chunks of backing memory. */
959 while (span_va_page
< va_page
) {
960 struct amdgpu_sparse_backing
*backing
;
961 uint32_t backing_start
, backing_size
;
963 backing_size
= va_page
- span_va_page
;
964 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
970 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
971 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
972 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
973 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
974 AMDGPU_VM_PAGE_READABLE
|
975 AMDGPU_VM_PAGE_WRITEABLE
|
976 AMDGPU_VM_PAGE_EXECUTABLE
,
977 AMDGPU_VA_OP_REPLACE
);
979 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
980 assert(ok
&& "sufficient memory should already be allocated");
986 while (backing_size
) {
987 comm
[span_va_page
].backing
= backing
;
988 comm
[span_va_page
].page
= backing_start
;
996 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
997 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
998 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
999 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
1005 while (va_page
< end_va_page
) {
1006 struct amdgpu_sparse_backing
*backing
;
1007 uint32_t backing_start
;
1008 uint32_t span_pages
;
1010 /* Skip pages that are already uncommitted. */
1011 if (!comm
[va_page
].backing
) {
1016 /* Group contiguous spans of pages. */
1017 backing
= comm
[va_page
].backing
;
1018 backing_start
= comm
[va_page
].page
;
1019 comm
[va_page
].backing
= NULL
;
1024 while (va_page
< end_va_page
&&
1025 comm
[va_page
].backing
== backing
&&
1026 comm
[va_page
].page
== backing_start
+ span_pages
) {
1027 comm
[va_page
].backing
= NULL
;
1032 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1033 /* Couldn't allocate tracking data structures, so we have to leak */
1034 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1041 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1046 static unsigned eg_tile_split(unsigned tile_split
)
1048 switch (tile_split
) {
1049 case 0: tile_split
= 64; break;
1050 case 1: tile_split
= 128; break;
1051 case 2: tile_split
= 256; break;
1052 case 3: tile_split
= 512; break;
1054 case 4: tile_split
= 1024; break;
1055 case 5: tile_split
= 2048; break;
1056 case 6: tile_split
= 4096; break;
1061 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1063 switch (eg_tile_split
) {
1069 case 1024: return 4;
1070 case 2048: return 5;
1071 case 4096: return 6;
1075 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1076 struct radeon_bo_metadata
*md
)
1078 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1079 struct amdgpu_bo_info info
= {0};
1080 uint64_t tiling_flags
;
1083 assert(bo
->bo
&& "must not be called for slab entries");
1085 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1089 tiling_flags
= info
.metadata
.tiling_info
;
1091 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1092 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1094 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1095 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1097 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1098 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1099 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1100 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1102 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1103 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1104 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1105 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1106 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1107 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1108 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1111 md
->size_metadata
= info
.metadata
.size_metadata
;
1112 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1115 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1116 struct radeon_bo_metadata
*md
)
1118 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1119 struct amdgpu_bo_metadata metadata
= {0};
1120 uint64_t tiling_flags
= 0;
1122 assert(bo
->bo
&& "must not be called for slab entries");
1124 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1125 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1127 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1128 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1129 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1130 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1132 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1134 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1135 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1136 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1137 if (md
->u
.legacy
.tile_split
)
1138 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1139 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1140 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1142 if (md
->u
.legacy
.scanout
)
1143 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1145 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1148 metadata
.tiling_info
= tiling_flags
;
1149 metadata
.size_metadata
= md
->size_metadata
;
1150 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1152 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1155 static struct pb_buffer
*
1156 amdgpu_bo_create(struct radeon_winsys
*rws
,
1159 enum radeon_bo_domain domain
,
1160 enum radeon_bo_flag flags
)
1162 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1163 struct amdgpu_winsys_bo
*bo
;
1164 unsigned usage
= 0, pb_cache_bucket
= 0;
1166 /* VRAM implies WC. This is not optional. */
1167 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
1169 /* NO_CPU_ACCESS is valid with VRAM only. */
1170 assert(domain
== RADEON_DOMAIN_VRAM
|| !(flags
& RADEON_FLAG_NO_CPU_ACCESS
));
1172 /* Sub-allocate small buffers from slabs. */
1173 if (!(flags
& (RADEON_FLAG_NO_SUBALLOC
| RADEON_FLAG_SPARSE
)) &&
1174 size
<= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2
) &&
1175 alignment
<= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2
, util_next_power_of_two(size
))) {
1176 struct pb_slab_entry
*entry
;
1177 int heap
= radeon_get_heap_index(domain
, flags
);
1179 if (heap
< 0 || heap
>= RADEON_MAX_SLAB_HEAPS
)
1182 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1184 /* Clear the cache and try again. */
1185 pb_cache_release_all_buffers(&ws
->bo_cache
);
1187 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1193 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1195 pipe_reference_init(&bo
->base
.reference
, 1);
1201 if (flags
& RADEON_FLAG_SPARSE
) {
1202 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1204 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
1206 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1209 /* This flag is irrelevant for the cache. */
1210 flags
&= ~RADEON_FLAG_NO_SUBALLOC
;
1212 /* Align size to page size. This is the minimum alignment for normal
1213 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1214 * like constant/uniform buffers, can benefit from better and more reuse.
1216 size
= align64(size
, ws
->info
.gart_page_size
);
1217 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1219 bool use_reusable_pool
= flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1221 if (use_reusable_pool
) {
1222 int heap
= radeon_get_heap_index(domain
, flags
);
1223 assert(heap
>= 0 && heap
< RADEON_MAX_CACHED_HEAPS
);
1224 usage
= 1 << heap
; /* Only set one usage bit for each heap. */
1226 pb_cache_bucket
= radeon_get_pb_cache_bucket_index(heap
);
1227 assert(pb_cache_bucket
< ARRAY_SIZE(ws
->bo_cache
.buckets
));
1229 /* Get a buffer from the cache. */
1230 bo
= (struct amdgpu_winsys_bo
*)
1231 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, usage
,
1237 /* Create a new one. */
1238 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1241 /* Clear the cache and try again. */
1242 pb_slabs_reclaim(&ws
->bo_slabs
);
1243 pb_cache_release_all_buffers(&ws
->bo_cache
);
1244 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1250 bo
->u
.real
.use_reusable_pool
= use_reusable_pool
;
1254 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1255 struct winsys_handle
*whandle
,
1259 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1260 struct amdgpu_winsys_bo
*bo
;
1261 enum amdgpu_bo_handle_type type
;
1262 struct amdgpu_bo_import_result result
= {0};
1264 amdgpu_va_handle va_handle
;
1265 struct amdgpu_bo_info info
= {0};
1266 enum radeon_bo_domain initial
= 0;
1269 /* Initialize the structure. */
1270 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1275 switch (whandle
->type
) {
1276 case DRM_API_HANDLE_TYPE_SHARED
:
1277 type
= amdgpu_bo_handle_type_gem_flink_name
;
1279 case DRM_API_HANDLE_TYPE_FD
:
1280 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1286 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1290 /* Get initial domains. */
1291 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1295 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1296 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
, 0);
1300 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1304 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1305 initial
|= RADEON_DOMAIN_VRAM
;
1306 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1307 initial
|= RADEON_DOMAIN_GTT
;
1310 pipe_reference_init(&bo
->base
.reference
, 1);
1311 bo
->base
.alignment
= info
.phys_alignment
;
1312 bo
->bo
= result
.buf_handle
;
1313 bo
->base
.size
= result
.alloc_size
;
1314 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1317 bo
->u
.real
.va_handle
= va_handle
;
1318 bo
->initial_domain
= initial
;
1319 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1320 bo
->is_shared
= true;
1323 *stride
= whandle
->stride
;
1325 *offset
= whandle
->offset
;
1327 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1328 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1329 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1330 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1332 amdgpu_add_buffer_to_global_list(bo
);
1337 amdgpu_va_range_free(va_handle
);
1340 amdgpu_bo_free(result
.buf_handle
);
1347 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
1348 unsigned stride
, unsigned offset
,
1349 unsigned slice_size
,
1350 struct winsys_handle
*whandle
)
1352 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1353 enum amdgpu_bo_handle_type type
;
1356 /* Don't allow exports of slab entries and sparse buffers. */
1360 bo
->u
.real
.use_reusable_pool
= false;
1362 switch (whandle
->type
) {
1363 case DRM_API_HANDLE_TYPE_SHARED
:
1364 type
= amdgpu_bo_handle_type_gem_flink_name
;
1366 case DRM_API_HANDLE_TYPE_FD
:
1367 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1369 case DRM_API_HANDLE_TYPE_KMS
:
1370 type
= amdgpu_bo_handle_type_kms
;
1376 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1380 whandle
->stride
= stride
;
1381 whandle
->offset
= offset
;
1382 whandle
->offset
+= slice_size
* whandle
->layer
;
1383 bo
->is_shared
= true;
1387 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1388 void *pointer
, uint64_t size
)
1390 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1391 amdgpu_bo_handle buf_handle
;
1392 struct amdgpu_winsys_bo
*bo
;
1394 amdgpu_va_handle va_handle
;
1396 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1400 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
1403 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1404 size
, 1 << 12, 0, &va
, &va_handle
, 0))
1405 goto error_va_alloc
;
1407 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
1410 /* Initialize it. */
1411 pipe_reference_init(&bo
->base
.reference
, 1);
1412 bo
->bo
= buf_handle
;
1413 bo
->base
.alignment
= 0;
1414 bo
->base
.size
= size
;
1415 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1417 bo
->user_ptr
= pointer
;
1419 bo
->u
.real
.va_handle
= va_handle
;
1420 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1421 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1423 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1425 amdgpu_add_buffer_to_global_list(bo
);
1427 return (struct pb_buffer
*)bo
;
1430 amdgpu_va_range_free(va_handle
);
1433 amdgpu_bo_free(buf_handle
);
1440 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1442 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
1445 static bool amdgpu_bo_is_suballocated(struct pb_buffer
*buf
)
1447 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
1449 return !bo
->bo
&& !bo
->sparse
;
1452 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1454 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1457 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
1459 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1460 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1461 ws
->base
.buffer_map
= amdgpu_bo_map
;
1462 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1463 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1464 ws
->base
.buffer_create
= amdgpu_bo_create
;
1465 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1466 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1467 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1468 ws
->base
.buffer_is_suballocated
= amdgpu_bo_is_suballocated
;
1469 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1470 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1471 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1472 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;