2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "amdgpu_cs.h"
30 #include "util/hash_table.h"
31 #include "util/os_time.h"
32 #include "util/u_hash_table.h"
33 #include "state_tracker/drm_driver.h"
34 #include <amdgpu_drm.h>
39 #ifndef AMDGPU_VA_RANGE_HIGH
40 #define AMDGPU_VA_RANGE_HIGH 0x2
43 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
44 #define DEBUG_SPARSE_COMMITS 0
46 struct amdgpu_sparse_backing_chunk
{
50 static void amdgpu_bo_unmap(struct pb_buffer
*buf
);
52 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
53 enum radeon_bo_usage usage
)
55 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
56 struct amdgpu_winsys
*ws
= bo
->ws
;
60 if (p_atomic_read(&bo
->num_active_ioctls
))
64 abs_timeout
= os_time_get_absolute_timeout(timeout
);
66 /* Wait if any ioctl is being submitted with this buffer. */
67 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
72 /* We can't use user fences for shared buffers, because user fences
73 * are local to this process only. If we want to wait for all buffer
74 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
76 bool buffer_busy
= true;
79 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
81 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
90 simple_mtx_lock(&ws
->bo_fence_lock
);
92 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
93 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
97 /* Release the idle fences to avoid checking them again later. */
98 for (unsigned i
= 0; i
< idle_fences
; ++i
)
99 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
101 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
102 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
103 bo
->num_fences
-= idle_fences
;
105 buffer_idle
= !bo
->num_fences
;
106 simple_mtx_unlock(&ws
->bo_fence_lock
);
110 bool buffer_idle
= true;
112 simple_mtx_lock(&ws
->bo_fence_lock
);
113 while (bo
->num_fences
&& buffer_idle
) {
114 struct pipe_fence_handle
*fence
= NULL
;
115 bool fence_idle
= false;
117 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
119 /* Wait for the fence. */
120 simple_mtx_unlock(&ws
->bo_fence_lock
);
121 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
125 simple_mtx_lock(&ws
->bo_fence_lock
);
127 /* Release an idle fence to avoid checking it again later, keeping in
128 * mind that the fence array may have been modified by other threads.
130 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
131 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
132 memmove(&bo
->fences
[0], &bo
->fences
[1],
133 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
137 amdgpu_fence_reference(&fence
, NULL
);
139 simple_mtx_unlock(&ws
->bo_fence_lock
);
145 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
146 struct pb_buffer
*buf
)
148 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
151 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
153 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
154 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
161 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
163 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
164 struct amdgpu_screen_winsys
*sws_iter
;
165 struct amdgpu_winsys
*ws
= bo
->ws
;
167 assert(bo
->bo
&& "must not be called for slab entries");
169 if (!bo
->is_user_ptr
&& bo
->cpu_ptr
) {
171 amdgpu_bo_unmap(&bo
->base
);
173 assert(bo
->is_user_ptr
|| bo
->u
.real
.map_count
== 0);
175 if (ws
->debug_all_bos
) {
176 simple_mtx_lock(&ws
->global_bo_list_lock
);
177 list_del(&bo
->u
.real
.global_list_item
);
179 simple_mtx_unlock(&ws
->global_bo_list_lock
);
182 /* Close all KMS handles retrieved for other DRM file descriptions */
183 simple_mtx_lock(&ws
->sws_list_lock
);
184 for (sws_iter
= ws
->sws_list
; sws_iter
; sws_iter
= sws_iter
->next
) {
185 struct hash_entry
*entry
;
187 if (!sws_iter
->kms_handles
)
190 entry
= _mesa_hash_table_search(sws_iter
->kms_handles
, bo
);
192 struct drm_gem_close args
= { .handle
= (uintptr_t)entry
->data
};
194 drmIoctl(sws_iter
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
195 _mesa_hash_table_remove(sws_iter
->kms_handles
, entry
);
198 simple_mtx_unlock(&ws
->sws_list_lock
);
200 simple_mtx_lock(&ws
->bo_export_table_lock
);
201 _mesa_hash_table_remove_key(ws
->bo_export_table
, bo
->bo
);
202 simple_mtx_unlock(&ws
->bo_export_table_lock
);
204 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM_GTT
) {
205 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
206 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
208 amdgpu_bo_free(bo
->bo
);
210 amdgpu_bo_remove_fences(bo
);
212 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
213 ws
->allocated_vram
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
214 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
215 ws
->allocated_gtt
-= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
217 simple_mtx_destroy(&bo
->lock
);
221 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
223 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
225 assert(bo
->bo
); /* slab buffers have a separate vtbl */
227 if (bo
->u
.real
.use_reusable_pool
)
228 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
230 amdgpu_bo_destroy(_buf
);
233 static void amdgpu_clean_up_buffer_managers(struct amdgpu_winsys
*ws
)
235 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++)
236 pb_slabs_reclaim(&ws
->bo_slabs
[i
]);
238 pb_cache_release_all_buffers(&ws
->bo_cache
);
241 static bool amdgpu_bo_do_map(struct amdgpu_winsys_bo
*bo
, void **cpu
)
243 assert(!bo
->sparse
&& bo
->bo
&& !bo
->is_user_ptr
);
244 int r
= amdgpu_bo_cpu_map(bo
->bo
, cpu
);
246 /* Clean up buffer managers and try again. */
247 amdgpu_clean_up_buffer_managers(bo
->ws
);
248 r
= amdgpu_bo_cpu_map(bo
->bo
, cpu
);
253 if (p_atomic_inc_return(&bo
->u
.real
.map_count
) == 1) {
254 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
255 bo
->ws
->mapped_vram
+= bo
->base
.size
;
256 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
257 bo
->ws
->mapped_gtt
+= bo
->base
.size
;
258 bo
->ws
->num_mapped_buffers
++;
264 void *amdgpu_bo_map(struct pb_buffer
*buf
,
265 struct radeon_cmdbuf
*rcs
,
266 enum pipe_transfer_usage usage
)
268 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
269 struct amdgpu_winsys_bo
*real
;
270 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
274 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
275 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
276 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
277 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
278 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
281 * Since we are mapping for read, we don't need to wait
282 * if the GPU is using the buffer for read too
283 * (neither one is changing it).
285 * Only check whether the buffer is being used for write. */
286 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
287 RADEON_USAGE_WRITE
)) {
288 cs
->flush_cs(cs
->flush_data
,
289 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
293 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
294 RADEON_USAGE_WRITE
)) {
298 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
299 cs
->flush_cs(cs
->flush_data
,
300 RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
304 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
305 RADEON_USAGE_READWRITE
)) {
310 uint64_t time
= os_time_get_nano();
312 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
315 * Since we are mapping for read, we don't need to wait
316 * if the GPU is using the buffer for read too
317 * (neither one is changing it).
319 * Only check whether the buffer is being used for write. */
321 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
322 RADEON_USAGE_WRITE
)) {
323 cs
->flush_cs(cs
->flush_data
,
324 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
326 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
327 if (p_atomic_read(&bo
->num_active_ioctls
))
328 amdgpu_cs_sync_flush(rcs
);
332 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
335 /* Mapping for write. */
337 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
338 cs
->flush_cs(cs
->flush_data
,
339 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
, NULL
);
341 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
342 if (p_atomic_read(&bo
->num_active_ioctls
))
343 amdgpu_cs_sync_flush(rcs
);
347 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
348 RADEON_USAGE_READWRITE
);
351 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
355 /* Buffer synchronization has been checked, now actually map the buffer. */
362 real
= bo
->u
.slab
.real
;
363 offset
= bo
->va
- real
->va
;
366 if (usage
& RADEON_TRANSFER_TEMPORARY
) {
367 if (real
->is_user_ptr
) {
370 if (!amdgpu_bo_do_map(real
, &cpu
))
374 cpu
= p_atomic_read(&real
->cpu_ptr
);
376 simple_mtx_lock(&real
->lock
);
377 /* Must re-check due to the possibility of a race. Re-check need not
378 * be atomic thanks to the lock. */
381 if (!amdgpu_bo_do_map(real
, &cpu
)) {
382 simple_mtx_unlock(&real
->lock
);
385 p_atomic_set(&real
->cpu_ptr
, cpu
);
387 simple_mtx_unlock(&real
->lock
);
391 return (uint8_t*)cpu
+ offset
;
394 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
396 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
397 struct amdgpu_winsys_bo
*real
;
404 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
405 assert(real
->u
.real
.map_count
!= 0 && "too many unmaps");
406 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
407 assert(!real
->cpu_ptr
&&
408 "too many unmaps or forgot RADEON_TRANSFER_TEMPORARY flag");
410 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
411 real
->ws
->mapped_vram
-= real
->base
.size
;
412 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
413 real
->ws
->mapped_gtt
-= real
->base
.size
;
414 real
->ws
->num_mapped_buffers
--;
417 amdgpu_bo_cpu_unmap(real
->bo
);
420 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
421 amdgpu_bo_destroy_or_cache
422 /* other functions are never called */
425 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
427 struct amdgpu_winsys
*ws
= bo
->ws
;
431 if (ws
->debug_all_bos
) {
432 simple_mtx_lock(&ws
->global_bo_list_lock
);
433 list_addtail(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
435 simple_mtx_unlock(&ws
->global_bo_list_lock
);
439 static uint64_t amdgpu_get_optimal_vm_alignment(struct amdgpu_winsys
*ws
,
440 uint64_t size
, unsigned alignment
)
442 uint64_t vm_alignment
= alignment
;
444 /* Increase the VM alignment for faster address translation. */
445 if (size
>= ws
->info
.pte_fragment_size
)
446 vm_alignment
= MAX2(vm_alignment
, ws
->info
.pte_fragment_size
);
448 /* Gfx9: Increase the VM alignment to the most significant bit set
449 * in the size for faster address translation.
451 if (ws
->info
.chip_class
>= GFX9
) {
452 unsigned msb
= util_last_bit64(size
); /* 0 = no bit is set */
453 uint64_t msb_alignment
= msb
? 1ull << (msb
- 1) : 0;
455 vm_alignment
= MAX2(vm_alignment
, msb_alignment
);
460 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
463 enum radeon_bo_domain initial_domain
,
467 struct amdgpu_bo_alloc_request request
= {0};
468 amdgpu_bo_handle buf_handle
;
470 struct amdgpu_winsys_bo
*bo
;
471 amdgpu_va_handle va_handle
;
474 /* VRAM or GTT must be specified, but not both at the same time. */
475 assert(util_bitcount(initial_domain
& (RADEON_DOMAIN_VRAM_GTT
|
477 RADEON_DOMAIN_OA
)) == 1);
479 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
485 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
488 request
.alloc_size
= size
;
489 request
.phys_alignment
= alignment
;
491 if (initial_domain
& RADEON_DOMAIN_VRAM
) {
492 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
494 /* Since VRAM and GTT have almost the same performance on APUs, we could
495 * just set GTT. However, in order to decrease GTT(RAM) usage, which is
496 * shared with the OS, allow VRAM placements too. The idea is not to use
497 * VRAM usefully, but to use it so that it's not unused and wasted.
499 if (!ws
->info
.has_dedicated_vram
)
500 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
503 if (initial_domain
& RADEON_DOMAIN_GTT
)
504 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
505 if (initial_domain
& RADEON_DOMAIN_GDS
)
506 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GDS
;
507 if (initial_domain
& RADEON_DOMAIN_OA
)
508 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_OA
;
510 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
511 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
512 if (flags
& RADEON_FLAG_GTT_WC
)
513 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
514 if (ws
->zero_all_vram_allocs
&&
515 (request
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
))
516 request
.flags
|= AMDGPU_GEM_CREATE_VRAM_CLEARED
;
518 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
520 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
521 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
522 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
523 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
527 if (initial_domain
& RADEON_DOMAIN_VRAM_GTT
) {
528 unsigned va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
530 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
532 amdgpu_get_optimal_vm_alignment(ws
, size
, alignment
),
534 (flags
& RADEON_FLAG_32BIT
? AMDGPU_VA_RANGE_32_BIT
: 0) |
535 AMDGPU_VA_RANGE_HIGH
);
539 unsigned vm_flags
= AMDGPU_VM_PAGE_READABLE
|
540 AMDGPU_VM_PAGE_EXECUTABLE
;
542 if (!(flags
& RADEON_FLAG_READ_ONLY
))
543 vm_flags
|= AMDGPU_VM_PAGE_WRITEABLE
;
545 r
= amdgpu_bo_va_op_raw(ws
->dev
, buf_handle
, 0, size
, va
, vm_flags
,
551 simple_mtx_init(&bo
->lock
, mtx_plain
);
552 pipe_reference_init(&bo
->base
.reference
, 1);
553 bo
->base
.alignment
= alignment
;
555 bo
->base
.size
= size
;
556 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
560 bo
->u
.real
.va_handle
= va_handle
;
561 bo
->initial_domain
= initial_domain
;
562 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
564 if (initial_domain
& RADEON_DOMAIN_VRAM
)
565 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
566 else if (initial_domain
& RADEON_DOMAIN_GTT
)
567 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
569 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
571 amdgpu_add_buffer_to_global_list(bo
);
576 amdgpu_va_range_free(va_handle
);
579 amdgpu_bo_free(buf_handle
);
586 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
588 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
590 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
594 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
597 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
599 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
600 bo
= container_of(entry
, bo
, u
.slab
.entry
);
602 return amdgpu_bo_can_reclaim(&bo
->base
);
605 static struct pb_slabs
*get_slabs(struct amdgpu_winsys
*ws
, uint64_t size
)
607 /* Find the correct slab allocator for the given size. */
608 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
609 struct pb_slabs
*slabs
= &ws
->bo_slabs
[i
];
611 if (size
<= 1 << (slabs
->min_order
+ slabs
->num_orders
- 1))
619 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
621 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
625 pb_slab_free(get_slabs(bo
->ws
, bo
->base
.size
), &bo
->u
.slab
.entry
);
628 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
629 amdgpu_bo_slab_destroy
630 /* other functions are never called */
633 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
635 unsigned group_index
)
637 struct amdgpu_winsys
*ws
= priv
;
638 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
639 enum radeon_bo_domain domains
= radeon_domain_from_heap(heap
);
640 enum radeon_bo_flag flags
= radeon_flags_from_heap(heap
);
642 unsigned slab_size
= 0;
647 /* Determine the slab buffer size. */
648 for (unsigned i
= 0; i
< NUM_SLAB_ALLOCATORS
; i
++) {
649 struct pb_slabs
*slabs
= &ws
->bo_slabs
[i
];
650 unsigned max_entry_size
= 1 << (slabs
->min_order
+ slabs
->num_orders
- 1);
652 if (entry_size
<= max_entry_size
) {
653 /* The slab size is twice the size of the largest possible entry. */
654 slab_size
= max_entry_size
* 2;
656 /* The largest slab should have the same size as the PTE fragment
657 * size to get faster address translation.
659 if (i
== NUM_SLAB_ALLOCATORS
- 1 &&
660 slab_size
< ws
->info
.pte_fragment_size
)
661 slab_size
= ws
->info
.pte_fragment_size
;
665 assert(slab_size
!= 0);
667 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(ws
,
668 slab_size
, slab_size
,
673 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
674 slab
->base
.num_free
= slab
->base
.num_entries
;
675 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
679 list_inithead(&slab
->base
.free
);
681 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
683 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
684 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
686 simple_mtx_init(&bo
->lock
, mtx_plain
);
687 bo
->base
.alignment
= entry_size
;
688 bo
->base
.usage
= slab
->buffer
->base
.usage
;
689 bo
->base
.size
= entry_size
;
690 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
692 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
693 bo
->initial_domain
= domains
;
694 bo
->unique_id
= base_id
+ i
;
695 bo
->u
.slab
.entry
.slab
= &slab
->base
;
696 bo
->u
.slab
.entry
.group_index
= group_index
;
698 if (slab
->buffer
->bo
) {
699 /* The slab is not suballocated. */
700 bo
->u
.slab
.real
= slab
->buffer
;
702 /* The slab is allocated out of a bigger slab. */
703 bo
->u
.slab
.real
= slab
->buffer
->u
.slab
.real
;
704 assert(bo
->u
.slab
.real
->bo
);
707 list_addtail(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
713 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
719 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
721 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
723 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
724 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
725 simple_mtx_destroy(&slab
->entries
[i
].lock
);
729 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
733 #if DEBUG_SPARSE_COMMITS
735 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
737 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
739 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
741 struct amdgpu_sparse_backing
*span_backing
= NULL
;
742 uint32_t span_first_backing_page
= 0;
743 uint32_t span_first_va_page
= 0;
744 uint32_t va_page
= 0;
747 struct amdgpu_sparse_backing
*backing
= 0;
748 uint32_t backing_page
= 0;
750 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
751 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
752 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
756 (backing
!= span_backing
||
757 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
758 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
759 span_first_va_page
, va_page
- 1, span_backing
,
760 span_first_backing_page
,
761 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
766 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
769 if (backing
&& !span_backing
) {
770 span_backing
= backing
;
771 span_first_backing_page
= backing_page
;
772 span_first_va_page
= va_page
;
778 fprintf(stderr
, "Backing:\n");
780 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
781 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
782 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
783 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
789 * Attempt to allocate the given number of backing pages. Fewer pages may be
790 * allocated (depending on the fragmentation of existing backing buffers),
791 * which will be reflected by a change to *pnum_pages.
793 static struct amdgpu_sparse_backing
*
794 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
796 struct amdgpu_sparse_backing
*best_backing
;
798 uint32_t best_num_pages
;
804 /* This is a very simple and inefficient best-fit algorithm. */
805 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
806 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
807 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
808 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
809 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
810 best_backing
= backing
;
812 best_num_pages
= cur_num_pages
;
817 /* Allocate a new backing buffer if necessary. */
819 struct pb_buffer
*buf
;
823 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
827 best_backing
->max_chunks
= 4;
828 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
829 sizeof(*best_backing
->chunks
));
830 if (!best_backing
->chunks
) {
835 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
837 size
= MIN3(bo
->base
.size
/ 16,
839 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
840 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
842 buf
= amdgpu_bo_create(bo
->ws
, size
, RADEON_SPARSE_PAGE_SIZE
,
844 bo
->u
.sparse
.flags
| RADEON_FLAG_NO_SUBALLOC
);
846 FREE(best_backing
->chunks
);
851 /* We might have gotten a bigger buffer than requested via caching. */
852 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
854 best_backing
->bo
= amdgpu_winsys_bo(buf
);
855 best_backing
->num_chunks
= 1;
856 best_backing
->chunks
[0].begin
= 0;
857 best_backing
->chunks
[0].end
= pages
;
859 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
860 bo
->u
.sparse
.num_backing_pages
+= pages
;
863 best_num_pages
= pages
;
866 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
867 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
868 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
870 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
871 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
872 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
873 best_backing
->num_chunks
--;
880 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
881 struct amdgpu_sparse_backing
*backing
)
883 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
885 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
887 simple_mtx_lock(&ws
->bo_fence_lock
);
888 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
889 simple_mtx_unlock(&ws
->bo_fence_lock
);
891 list_del(&backing
->list
);
892 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
893 FREE(backing
->chunks
);
898 * Return a range of pages from the given backing buffer back into the
902 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
903 struct amdgpu_sparse_backing
*backing
,
904 uint32_t start_page
, uint32_t num_pages
)
906 uint32_t end_page
= start_page
+ num_pages
;
908 unsigned high
= backing
->num_chunks
;
910 /* Find the first chunk with begin >= start_page. */
912 unsigned mid
= low
+ (high
- low
) / 2;
914 if (backing
->chunks
[mid
].begin
>= start_page
)
920 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
921 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
923 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
924 backing
->chunks
[low
- 1].end
= end_page
;
926 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
927 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
928 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
929 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
930 backing
->num_chunks
--;
932 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
933 backing
->chunks
[low
].begin
= start_page
;
935 if (backing
->num_chunks
>= backing
->max_chunks
) {
936 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
937 struct amdgpu_sparse_backing_chunk
*new_chunks
=
938 REALLOC(backing
->chunks
,
939 sizeof(*backing
->chunks
) * backing
->max_chunks
,
940 sizeof(*backing
->chunks
) * new_max_chunks
);
944 backing
->max_chunks
= new_max_chunks
;
945 backing
->chunks
= new_chunks
;
948 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
949 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
950 backing
->chunks
[low
].begin
= start_page
;
951 backing
->chunks
[low
].end
= end_page
;
952 backing
->num_chunks
++;
955 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
956 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
957 sparse_free_backing_buffer(bo
, backing
);
962 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
964 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
967 assert(!bo
->bo
&& bo
->sparse
);
969 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
970 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
971 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
973 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
976 while (!list_is_empty(&bo
->u
.sparse
.backing
)) {
977 struct amdgpu_sparse_backing
*dummy
= NULL
;
978 sparse_free_backing_buffer(bo
,
979 container_of(bo
->u
.sparse
.backing
.next
,
983 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
984 FREE(bo
->u
.sparse
.commitments
);
985 simple_mtx_destroy(&bo
->lock
);
989 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
990 amdgpu_bo_sparse_destroy
991 /* other functions are never called */
994 static struct pb_buffer
*
995 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
996 enum radeon_bo_domain domain
,
997 enum radeon_bo_flag flags
)
999 struct amdgpu_winsys_bo
*bo
;
1001 uint64_t va_gap_size
;
1004 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
1005 * that exceed this limit. This is not really a restriction: we don't have
1006 * that much virtual address space anyway.
1008 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
1011 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1015 simple_mtx_init(&bo
->lock
, mtx_plain
);
1016 pipe_reference_init(&bo
->base
.reference
, 1);
1017 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
1018 bo
->base
.size
= size
;
1019 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
1021 bo
->initial_domain
= domain
;
1022 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1024 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
1026 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
1027 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
1028 sizeof(*bo
->u
.sparse
.commitments
));
1029 if (!bo
->u
.sparse
.commitments
)
1030 goto error_alloc_commitments
;
1032 list_inithead(&bo
->u
.sparse
.backing
);
1034 /* For simplicity, we always map a multiple of the page size. */
1035 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
1036 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
1037 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1038 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
1039 0, &bo
->va
, &bo
->u
.sparse
.va_handle
,
1040 AMDGPU_VA_RANGE_HIGH
);
1042 goto error_va_alloc
;
1044 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
1045 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
1052 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
1054 FREE(bo
->u
.sparse
.commitments
);
1055 error_alloc_commitments
:
1056 simple_mtx_destroy(&bo
->lock
);
1062 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
1065 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
1066 struct amdgpu_sparse_commitment
*comm
;
1067 uint32_t va_page
, end_va_page
;
1072 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
1073 assert(offset
<= bo
->base
.size
);
1074 assert(size
<= bo
->base
.size
- offset
);
1075 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
1077 comm
= bo
->u
.sparse
.commitments
;
1078 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
1079 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
1081 simple_mtx_lock(&bo
->lock
);
1083 #if DEBUG_SPARSE_COMMITS
1084 sparse_dump(bo
, __func__
);
1088 while (va_page
< end_va_page
) {
1089 uint32_t span_va_page
;
1091 /* Skip pages that are already committed. */
1092 if (comm
[va_page
].backing
) {
1097 /* Determine length of uncommitted span. */
1098 span_va_page
= va_page
;
1099 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
1102 /* Fill the uncommitted span with chunks of backing memory. */
1103 while (span_va_page
< va_page
) {
1104 struct amdgpu_sparse_backing
*backing
;
1105 uint32_t backing_start
, backing_size
;
1107 backing_size
= va_page
- span_va_page
;
1108 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
1114 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
1115 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
1116 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
1117 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
1118 AMDGPU_VM_PAGE_READABLE
|
1119 AMDGPU_VM_PAGE_WRITEABLE
|
1120 AMDGPU_VM_PAGE_EXECUTABLE
,
1121 AMDGPU_VA_OP_REPLACE
);
1123 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
1124 assert(ok
&& "sufficient memory should already be allocated");
1130 while (backing_size
) {
1131 comm
[span_va_page
].backing
= backing
;
1132 comm
[span_va_page
].page
= backing_start
;
1140 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
1141 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
1142 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
1143 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
1149 while (va_page
< end_va_page
) {
1150 struct amdgpu_sparse_backing
*backing
;
1151 uint32_t backing_start
;
1152 uint32_t span_pages
;
1154 /* Skip pages that are already uncommitted. */
1155 if (!comm
[va_page
].backing
) {
1160 /* Group contiguous spans of pages. */
1161 backing
= comm
[va_page
].backing
;
1162 backing_start
= comm
[va_page
].page
;
1163 comm
[va_page
].backing
= NULL
;
1168 while (va_page
< end_va_page
&&
1169 comm
[va_page
].backing
== backing
&&
1170 comm
[va_page
].page
== backing_start
+ span_pages
) {
1171 comm
[va_page
].backing
= NULL
;
1176 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1177 /* Couldn't allocate tracking data structures, so we have to leak */
1178 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1185 simple_mtx_unlock(&bo
->lock
);
1190 static unsigned eg_tile_split(unsigned tile_split
)
1192 switch (tile_split
) {
1193 case 0: tile_split
= 64; break;
1194 case 1: tile_split
= 128; break;
1195 case 2: tile_split
= 256; break;
1196 case 3: tile_split
= 512; break;
1198 case 4: tile_split
= 1024; break;
1199 case 5: tile_split
= 2048; break;
1200 case 6: tile_split
= 4096; break;
1205 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1207 switch (eg_tile_split
) {
1213 case 1024: return 4;
1214 case 2048: return 5;
1215 case 4096: return 6;
1219 #define AMDGPU_TILING_SCANOUT_SHIFT 63
1220 #define AMDGPU_TILING_SCANOUT_MASK 0x1
1222 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1223 struct radeon_bo_metadata
*md
)
1225 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1226 struct amdgpu_bo_info info
= {0};
1227 uint64_t tiling_flags
;
1230 assert(bo
->bo
&& "must not be called for slab entries");
1232 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1236 tiling_flags
= info
.metadata
.tiling_info
;
1238 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1239 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1241 md
->u
.gfx9
.dcc_offset_256B
= AMDGPU_TILING_GET(tiling_flags
, DCC_OFFSET_256B
);
1242 md
->u
.gfx9
.dcc_pitch_max
= AMDGPU_TILING_GET(tiling_flags
, DCC_PITCH_MAX
);
1243 md
->u
.gfx9
.dcc_independent_64B
= AMDGPU_TILING_GET(tiling_flags
, DCC_INDEPENDENT_64B
);
1244 md
->u
.gfx9
.scanout
= AMDGPU_TILING_GET(tiling_flags
, SCANOUT
);
1246 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1247 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1249 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1250 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1251 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1252 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1254 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1255 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1256 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1257 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1258 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1259 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1260 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1263 md
->size_metadata
= info
.metadata
.size_metadata
;
1264 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1267 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1268 struct radeon_bo_metadata
*md
)
1270 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1271 struct amdgpu_bo_metadata metadata
= {0};
1272 uint64_t tiling_flags
= 0;
1274 assert(bo
->bo
&& "must not be called for slab entries");
1276 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1277 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1279 tiling_flags
|= AMDGPU_TILING_SET(DCC_OFFSET_256B
, md
->u
.gfx9
.dcc_offset_256B
);
1280 tiling_flags
|= AMDGPU_TILING_SET(DCC_PITCH_MAX
, md
->u
.gfx9
.dcc_pitch_max
);
1281 tiling_flags
|= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B
, md
->u
.gfx9
.dcc_independent_64B
);
1282 tiling_flags
|= AMDGPU_TILING_SET(SCANOUT
, md
->u
.gfx9
.scanout
);
1284 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1285 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1286 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1287 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1289 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1291 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1292 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1293 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1294 if (md
->u
.legacy
.tile_split
)
1295 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1296 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1297 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1299 if (md
->u
.legacy
.scanout
)
1300 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1302 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1305 metadata
.tiling_info
= tiling_flags
;
1306 metadata
.size_metadata
= md
->size_metadata
;
1307 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1309 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1313 amdgpu_bo_create(struct amdgpu_winsys
*ws
,
1316 enum radeon_bo_domain domain
,
1317 enum radeon_bo_flag flags
)
1319 struct amdgpu_winsys_bo
*bo
;
1322 if (domain
& (RADEON_DOMAIN_GDS
| RADEON_DOMAIN_OA
))
1323 flags
|= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_SUBALLOC
;
1325 /* VRAM implies WC. This is not optional. */
1326 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
1328 /* NO_CPU_ACCESS is not valid with GTT. */
1329 assert(!(domain
& RADEON_DOMAIN_GTT
) || !(flags
& RADEON_FLAG_NO_CPU_ACCESS
));
1331 /* Sparse buffers must have NO_CPU_ACCESS set. */
1332 assert(!(flags
& RADEON_FLAG_SPARSE
) || flags
& RADEON_FLAG_NO_CPU_ACCESS
);
1334 struct pb_slabs
*last_slab
= &ws
->bo_slabs
[NUM_SLAB_ALLOCATORS
- 1];
1335 unsigned max_slab_entry_size
= 1 << (last_slab
->min_order
+ last_slab
->num_orders
- 1);
1337 /* Sub-allocate small buffers from slabs. */
1338 if (!(flags
& (RADEON_FLAG_NO_SUBALLOC
| RADEON_FLAG_SPARSE
)) &&
1339 size
<= max_slab_entry_size
&&
1340 /* The alignment must be at most the size of the smallest slab entry or
1341 * the next power of two. */
1342 alignment
<= MAX2(1 << ws
->bo_slabs
[0].min_order
, util_next_power_of_two(size
))) {
1343 struct pb_slab_entry
*entry
;
1344 int heap
= radeon_get_heap_index(domain
, flags
);
1346 if (heap
< 0 || heap
>= RADEON_MAX_SLAB_HEAPS
)
1349 struct pb_slabs
*slabs
= get_slabs(ws
, size
);
1350 entry
= pb_slab_alloc(slabs
, size
, heap
);
1352 /* Clean up buffer managers and try again. */
1353 amdgpu_clean_up_buffer_managers(ws
);
1355 entry
= pb_slab_alloc(slabs
, size
, heap
);
1361 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1363 pipe_reference_init(&bo
->base
.reference
, 1);
1369 if (flags
& RADEON_FLAG_SPARSE
) {
1370 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1372 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1375 /* This flag is irrelevant for the cache. */
1376 flags
&= ~RADEON_FLAG_NO_SUBALLOC
;
1378 /* Align size to page size. This is the minimum alignment for normal
1379 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1380 * like constant/uniform buffers, can benefit from better and more reuse.
1382 if (domain
& RADEON_DOMAIN_VRAM_GTT
) {
1383 size
= align64(size
, ws
->info
.gart_page_size
);
1384 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1387 bool use_reusable_pool
= flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1389 if (use_reusable_pool
) {
1390 heap
= radeon_get_heap_index(domain
, flags
);
1391 assert(heap
>= 0 && heap
< RADEON_MAX_CACHED_HEAPS
);
1393 /* Get a buffer from the cache. */
1394 bo
= (struct amdgpu_winsys_bo
*)
1395 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, 0, heap
);
1400 /* Create a new one. */
1401 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1403 /* Clean up buffer managers and try again. */
1404 amdgpu_clean_up_buffer_managers(ws
);
1406 bo
= amdgpu_create_bo(ws
, size
, alignment
, domain
, flags
, heap
);
1411 bo
->u
.real
.use_reusable_pool
= use_reusable_pool
;
1415 static struct pb_buffer
*
1416 amdgpu_buffer_create(struct radeon_winsys
*ws
,
1419 enum radeon_bo_domain domain
,
1420 enum radeon_bo_flag flags
)
1422 return amdgpu_bo_create(amdgpu_winsys(ws
), size
, alignment
, domain
,
1426 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1427 struct winsys_handle
*whandle
,
1428 unsigned vm_alignment
)
1430 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1431 struct amdgpu_winsys_bo
*bo
= NULL
;
1432 enum amdgpu_bo_handle_type type
;
1433 struct amdgpu_bo_import_result result
= {0};
1435 amdgpu_va_handle va_handle
= NULL
;
1436 struct amdgpu_bo_info info
= {0};
1437 enum radeon_bo_domain initial
= 0;
1440 switch (whandle
->type
) {
1441 case WINSYS_HANDLE_TYPE_SHARED
:
1442 type
= amdgpu_bo_handle_type_gem_flink_name
;
1444 case WINSYS_HANDLE_TYPE_FD
:
1445 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1451 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1455 simple_mtx_lock(&ws
->bo_export_table_lock
);
1456 bo
= util_hash_table_get(ws
->bo_export_table
, result
.buf_handle
);
1458 /* If the amdgpu_winsys_bo instance already exists, bump the reference
1459 * counter and return it.
1462 p_atomic_inc(&bo
->base
.reference
.count
);
1463 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1465 /* Release the buffer handle, because we don't need it anymore.
1466 * This function is returning an existing buffer, which has its own
1469 amdgpu_bo_free(result
.buf_handle
);
1473 /* Get initial domains. */
1474 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1478 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1480 amdgpu_get_optimal_vm_alignment(ws
, result
.alloc_size
,
1482 0, &va
, &va_handle
, AMDGPU_VA_RANGE_HIGH
);
1486 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1490 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1494 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1495 initial
|= RADEON_DOMAIN_VRAM
;
1496 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1497 initial
|= RADEON_DOMAIN_GTT
;
1499 /* Initialize the structure. */
1500 simple_mtx_init(&bo
->lock
, mtx_plain
);
1501 pipe_reference_init(&bo
->base
.reference
, 1);
1502 bo
->base
.alignment
= info
.phys_alignment
;
1503 bo
->bo
= result
.buf_handle
;
1504 bo
->base
.size
= result
.alloc_size
;
1505 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1508 bo
->u
.real
.va_handle
= va_handle
;
1509 bo
->initial_domain
= initial
;
1510 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1511 bo
->is_shared
= true;
1513 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1514 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1515 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1516 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1518 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1520 amdgpu_add_buffer_to_global_list(bo
);
1522 _mesa_hash_table_insert(ws
->bo_export_table
, bo
->bo
, bo
);
1523 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1528 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1532 amdgpu_va_range_free(va_handle
);
1533 amdgpu_bo_free(result
.buf_handle
);
1537 static bool amdgpu_bo_get_handle(struct radeon_winsys
*rws
,
1538 struct pb_buffer
*buffer
,
1539 struct winsys_handle
*whandle
)
1541 struct amdgpu_screen_winsys
*sws
= amdgpu_screen_winsys(rws
);
1542 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1543 struct amdgpu_winsys
*ws
= bo
->ws
;
1544 enum amdgpu_bo_handle_type type
;
1545 struct hash_entry
*entry
;
1548 /* Don't allow exports of slab entries and sparse buffers. */
1552 bo
->u
.real
.use_reusable_pool
= false;
1554 switch (whandle
->type
) {
1555 case WINSYS_HANDLE_TYPE_SHARED
:
1556 type
= amdgpu_bo_handle_type_gem_flink_name
;
1558 case WINSYS_HANDLE_TYPE_KMS
:
1559 if (sws
->fd
== ws
->fd
) {
1560 whandle
->handle
= bo
->u
.real
.kms_handle
;
1565 goto hash_table_set
;
1568 simple_mtx_lock(&ws
->sws_list_lock
);
1569 entry
= _mesa_hash_table_search(sws
->kms_handles
, bo
);
1570 simple_mtx_unlock(&ws
->sws_list_lock
);
1572 whandle
->handle
= (uintptr_t)entry
->data
;
1576 case WINSYS_HANDLE_TYPE_FD
:
1577 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1583 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1587 if (whandle
->type
== WINSYS_HANDLE_TYPE_KMS
) {
1588 int dma_fd
= whandle
->handle
;
1590 r
= drmPrimeFDToHandle(sws
->fd
, dma_fd
, &whandle
->handle
);
1596 simple_mtx_lock(&ws
->sws_list_lock
);
1597 _mesa_hash_table_insert_pre_hashed(sws
->kms_handles
,
1598 bo
->u
.real
.kms_handle
, bo
,
1599 (void*)(uintptr_t)whandle
->handle
);
1600 simple_mtx_unlock(&ws
->sws_list_lock
);
1604 simple_mtx_lock(&ws
->bo_export_table_lock
);
1605 _mesa_hash_table_insert(ws
->bo_export_table
, bo
->bo
, bo
);
1606 simple_mtx_unlock(&ws
->bo_export_table_lock
);
1608 bo
->is_shared
= true;
1612 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1613 void *pointer
, uint64_t size
)
1615 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1616 amdgpu_bo_handle buf_handle
;
1617 struct amdgpu_winsys_bo
*bo
;
1619 amdgpu_va_handle va_handle
;
1620 /* Avoid failure when the size is not page aligned */
1621 uint64_t aligned_size
= align64(size
, ws
->info
.gart_page_size
);
1623 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1627 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
,
1628 aligned_size
, &buf_handle
))
1631 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1633 amdgpu_get_optimal_vm_alignment(ws
, aligned_size
,
1634 ws
->info
.gart_page_size
),
1635 0, &va
, &va_handle
, AMDGPU_VA_RANGE_HIGH
))
1636 goto error_va_alloc
;
1638 if (amdgpu_bo_va_op(buf_handle
, 0, aligned_size
, va
, 0, AMDGPU_VA_OP_MAP
))
1641 /* Initialize it. */
1642 bo
->is_user_ptr
= true;
1643 pipe_reference_init(&bo
->base
.reference
, 1);
1644 simple_mtx_init(&bo
->lock
, mtx_plain
);
1645 bo
->bo
= buf_handle
;
1646 bo
->base
.alignment
= 0;
1647 bo
->base
.size
= size
;
1648 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1650 bo
->cpu_ptr
= pointer
;
1652 bo
->u
.real
.va_handle
= va_handle
;
1653 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1654 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1656 ws
->allocated_gtt
+= aligned_size
;
1658 amdgpu_add_buffer_to_global_list(bo
);
1660 amdgpu_bo_export(bo
->bo
, amdgpu_bo_handle_type_kms
, &bo
->u
.real
.kms_handle
);
1662 return (struct pb_buffer
*)bo
;
1665 amdgpu_va_range_free(va_handle
);
1668 amdgpu_bo_free(buf_handle
);
1675 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1677 return ((struct amdgpu_winsys_bo
*)buf
)->is_user_ptr
;
1680 static bool amdgpu_bo_is_suballocated(struct pb_buffer
*buf
)
1682 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
1684 return !bo
->bo
&& !bo
->sparse
;
1687 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1689 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1692 void amdgpu_bo_init_functions(struct amdgpu_screen_winsys
*ws
)
1694 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1695 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1696 ws
->base
.buffer_map
= amdgpu_bo_map
;
1697 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1698 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1699 ws
->base
.buffer_create
= amdgpu_buffer_create
;
1700 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1701 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1702 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1703 ws
->base
.buffer_is_suballocated
= amdgpu_bo_is_suballocated
;
1704 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1705 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1706 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1707 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;