2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
34 #include "amd/common/sid.h"
36 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
40 static struct pipe_fence_handle
*
41 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
42 unsigned ip_instance
, unsigned ring
)
44 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
46 fence
->reference
.count
= 1;
49 fence
->fence
.context
= ctx
->ctx
;
50 fence
->fence
.ip_type
= ip_type
;
51 fence
->fence
.ip_instance
= ip_instance
;
52 fence
->fence
.ring
= ring
;
53 fence
->submission_in_progress
= true;
54 p_atomic_inc(&ctx
->refcount
);
55 return (struct pipe_fence_handle
*)fence
;
58 static struct pipe_fence_handle
*
59 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
61 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
62 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
67 pipe_reference_init(&fence
->reference
, 1);
69 /* fence->ctx == NULL means that the fence is syncobj-based. */
71 /* Convert sync_file into syncobj. */
72 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
78 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
80 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
84 return (struct pipe_fence_handle
*)fence
;
87 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
88 struct pipe_fence_handle
*pfence
)
90 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
91 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
93 if (amdgpu_fence_is_syncobj(fence
)) {
96 /* Convert syncobj into sync_file. */
97 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
101 os_wait_until_zero(&fence
->submission_in_progress
, PIPE_TIMEOUT_INFINITE
);
103 /* Convert the amdgpu fence into a fence FD. */
105 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
106 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
113 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
115 uint64_t *user_fence_cpu_address
)
117 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
119 rfence
->fence
.fence
= seq_no
;
120 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
121 rfence
->submission_in_progress
= false;
124 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
126 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
128 rfence
->signalled
= true;
129 rfence
->submission_in_progress
= false;
132 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
135 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
138 uint64_t *user_fence_cpu
;
141 if (rfence
->signalled
)
144 /* Handle syncobjs. */
145 if (amdgpu_fence_is_syncobj(rfence
)) {
146 /* Absolute timeouts are only be used by BO fences, which aren't
147 * backed by syncobjs.
151 if (amdgpu_cs_syncobj_wait(rfence
->ws
->dev
, &rfence
->syncobj
, 1,
155 rfence
->signalled
= true;
160 abs_timeout
= timeout
;
162 abs_timeout
= os_time_get_absolute_timeout(timeout
);
164 /* The fence might not have a number assigned if its IB is being
165 * submitted in the other thread right now. Wait until the submission
167 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
171 user_fence_cpu
= rfence
->user_fence_cpu_address
;
172 if (user_fence_cpu
) {
173 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
174 rfence
->signalled
= true;
178 /* No timeout, just query: no need for the ioctl. */
179 if (!absolute
&& !timeout
)
183 /* Now use the libdrm query. */
184 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
186 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
189 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
194 /* This variable can only transition from false to true, so it doesn't
195 * matter if threads race for it. */
196 rfence
->signalled
= true;
202 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
203 struct pipe_fence_handle
*fence
,
206 return amdgpu_fence_wait(fence
, timeout
, false);
209 static struct pipe_fence_handle
*
210 amdgpu_cs_get_next_fence(struct radeon_winsys_cs
*rcs
)
212 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
213 struct pipe_fence_handle
*fence
= NULL
;
215 if (debug_get_option_noop())
218 if (cs
->next_fence
) {
219 amdgpu_fence_reference(&fence
, cs
->next_fence
);
223 fence
= amdgpu_fence_create(cs
->ctx
,
224 cs
->csc
->ib
[IB_MAIN
].ip_type
,
225 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
226 cs
->csc
->ib
[IB_MAIN
].ring
);
230 amdgpu_fence_reference(&cs
->next_fence
, fence
);
236 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
238 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
240 struct amdgpu_bo_alloc_request alloc_buffer
= {};
241 amdgpu_bo_handle buf_handle
;
246 ctx
->ws
= amdgpu_winsys(ws
);
248 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
250 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
252 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
256 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
257 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
258 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
260 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
262 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
263 goto error_user_fence_alloc
;
266 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
268 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
269 goto error_user_fence_map
;
272 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
273 ctx
->user_fence_bo
= buf_handle
;
275 return (struct radeon_winsys_ctx
*)ctx
;
277 error_user_fence_map
:
278 amdgpu_bo_free(buf_handle
);
279 error_user_fence_alloc
:
280 amdgpu_cs_ctx_free(ctx
->ctx
);
286 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
288 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
291 static enum pipe_reset_status
292 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
294 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
295 uint32_t result
, hangs
;
298 /* Return a failure due to a rejected command submission. */
299 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
300 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
301 PIPE_INNOCENT_CONTEXT_RESET
;
304 /* Return a failure due to a GPU hang. */
305 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
307 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
308 return PIPE_NO_RESET
;
312 case AMDGPU_CTX_GUILTY_RESET
:
313 return PIPE_GUILTY_CONTEXT_RESET
;
314 case AMDGPU_CTX_INNOCENT_RESET
:
315 return PIPE_INNOCENT_CONTEXT_RESET
;
316 case AMDGPU_CTX_UNKNOWN_RESET
:
317 return PIPE_UNKNOWN_CONTEXT_RESET
;
318 case AMDGPU_CTX_NO_RESET
:
320 return PIPE_NO_RESET
;
324 /* COMMAND SUBMISSION */
326 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
328 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
329 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
330 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
;
333 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
335 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
336 cs
->ring_type
== RING_GFX
;
339 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
341 if (ring_type
== RING_GFX
)
342 return 4; /* for chaining */
347 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
349 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
350 int i
= cs
->buffer_indices_hashlist
[hash
];
351 struct amdgpu_cs_buffer
*buffers
;
355 buffers
= cs
->real_buffers
;
356 num_buffers
= cs
->num_real_buffers
;
357 } else if (!bo
->sparse
) {
358 buffers
= cs
->slab_buffers
;
359 num_buffers
= cs
->num_slab_buffers
;
361 buffers
= cs
->sparse_buffers
;
362 num_buffers
= cs
->num_sparse_buffers
;
365 /* not found or found */
366 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
369 /* Hash collision, look for the BO in the list of buffers linearly. */
370 for (i
= num_buffers
- 1; i
>= 0; i
--) {
371 if (buffers
[i
].bo
== bo
) {
372 /* Put this buffer in the hash list.
373 * This will prevent additional hash collisions if there are
374 * several consecutive lookup_buffer calls for the same buffer.
376 * Example: Assuming buffers A,B,C collide in the hash list,
377 * the following sequence of buffers:
378 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
379 * will collide here: ^ and here: ^,
380 * meaning that we should get very few collisions in the end. */
381 cs
->buffer_indices_hashlist
[hash
] = i
;
389 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
391 struct amdgpu_cs_buffer
*buffer
;
394 /* New buffer, check if the backing array is large enough. */
395 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
397 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
398 struct amdgpu_cs_buffer
*new_buffers
;
400 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
403 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
408 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
410 FREE(cs
->real_buffers
);
412 cs
->max_real_buffers
= new_max
;
413 cs
->real_buffers
= new_buffers
;
416 idx
= cs
->num_real_buffers
;
417 buffer
= &cs
->real_buffers
[idx
];
419 memset(buffer
, 0, sizeof(*buffer
));
420 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
421 p_atomic_inc(&bo
->num_cs_references
);
422 cs
->num_real_buffers
++;
428 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
430 struct amdgpu_cs_context
*cs
= acs
->csc
;
432 int idx
= amdgpu_lookup_buffer(cs
, bo
);
437 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
439 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
440 cs
->buffer_indices_hashlist
[hash
] = idx
;
442 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
443 acs
->main
.base
.used_vram
+= bo
->base
.size
;
444 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
445 acs
->main
.base
.used_gart
+= bo
->base
.size
;
450 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
451 struct amdgpu_winsys_bo
*bo
)
453 struct amdgpu_cs_context
*cs
= acs
->csc
;
454 struct amdgpu_cs_buffer
*buffer
;
456 int idx
= amdgpu_lookup_buffer(cs
, bo
);
462 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
466 /* New buffer, check if the backing array is large enough. */
467 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
469 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
470 struct amdgpu_cs_buffer
*new_buffers
;
472 new_buffers
= REALLOC(cs
->slab_buffers
,
473 cs
->max_slab_buffers
* sizeof(*new_buffers
),
474 new_max
* sizeof(*new_buffers
));
476 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
480 cs
->max_slab_buffers
= new_max
;
481 cs
->slab_buffers
= new_buffers
;
484 idx
= cs
->num_slab_buffers
;
485 buffer
= &cs
->slab_buffers
[idx
];
487 memset(buffer
, 0, sizeof(*buffer
));
488 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
489 buffer
->u
.slab
.real_idx
= real_idx
;
490 p_atomic_inc(&bo
->num_cs_references
);
491 cs
->num_slab_buffers
++;
493 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
494 cs
->buffer_indices_hashlist
[hash
] = idx
;
499 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
500 struct amdgpu_winsys_bo
*bo
)
502 struct amdgpu_cs_context
*cs
= acs
->csc
;
503 struct amdgpu_cs_buffer
*buffer
;
505 int idx
= amdgpu_lookup_buffer(cs
, bo
);
510 /* New buffer, check if the backing array is large enough. */
511 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
513 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
514 struct amdgpu_cs_buffer
*new_buffers
;
516 new_buffers
= REALLOC(cs
->sparse_buffers
,
517 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
518 new_max
* sizeof(*new_buffers
));
520 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
524 cs
->max_sparse_buffers
= new_max
;
525 cs
->sparse_buffers
= new_buffers
;
528 idx
= cs
->num_sparse_buffers
;
529 buffer
= &cs
->sparse_buffers
[idx
];
531 memset(buffer
, 0, sizeof(*buffer
));
532 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
533 p_atomic_inc(&bo
->num_cs_references
);
534 cs
->num_sparse_buffers
++;
536 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
537 cs
->buffer_indices_hashlist
[hash
] = idx
;
539 /* We delay adding the backing buffers until we really have to. However,
540 * we cannot delay accounting for memory use.
542 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
544 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
545 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
546 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
547 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
548 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
551 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
556 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
557 struct pb_buffer
*buf
,
558 enum radeon_bo_usage usage
,
559 enum radeon_bo_domain domains
,
560 enum radeon_bo_priority priority
)
562 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
563 * the buffer placement during command submission.
565 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
566 struct amdgpu_cs_context
*cs
= acs
->csc
;
567 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
568 struct amdgpu_cs_buffer
*buffer
;
571 /* Fast exit for no-op calls.
572 * This is very effective with suballocators and linear uploaders that
573 * are outside of the winsys.
575 if (bo
== cs
->last_added_bo
&&
576 (usage
& cs
->last_added_bo_usage
) == usage
&&
577 (1ull << priority
) & cs
->last_added_bo_priority_usage
)
578 return cs
->last_added_bo_index
;
582 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
586 buffer
= &cs
->slab_buffers
[index
];
587 buffer
->usage
|= usage
;
589 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
590 index
= buffer
->u
.slab
.real_idx
;
592 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
597 buffer
= &cs
->real_buffers
[index
];
599 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
603 buffer
= &cs
->sparse_buffers
[index
];
606 buffer
->u
.real
.priority_usage
|= 1ull << priority
;
607 buffer
->usage
|= usage
;
609 cs
->last_added_bo
= bo
;
610 cs
->last_added_bo_index
= index
;
611 cs
->last_added_bo_usage
= buffer
->usage
;
612 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
616 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
,
617 enum ring_type ring_type
)
619 struct pb_buffer
*pb
;
621 unsigned buffer_size
;
623 /* Always create a buffer that is at least as large as the maximum seen IB
624 * size, aligned to a power of two (and multiplied by 4 to reduce internal
625 * fragmentation if chaining is not available). Limit to 512k dwords, which
626 * is the largest power of two that fits into the size field of the
627 * INDIRECT_BUFFER packet.
629 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
630 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
632 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
634 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
636 switch (ib
->ib_type
) {
638 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
641 unreachable("unhandled IB type");
644 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
645 ws
->info
.gart_page_size
,
647 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
648 (ring_type
== RING_GFX
||
649 ring_type
== RING_COMPUTE
||
650 ring_type
== RING_DMA
?
651 RADEON_FLAG_GTT_WC
: 0));
655 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
657 pb_reference(&pb
, NULL
);
661 pb_reference(&ib
->big_ib_buffer
, pb
);
662 pb_reference(&pb
, NULL
);
664 ib
->ib_mapped
= mapped
;
665 ib
->used_ib_space
= 0;
670 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
674 /* Smaller submits means the GPU gets busy sooner and there is less
675 * waiting for buffers and fences. Proof:
676 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
680 unreachable("bad ib_type");
684 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
685 enum ib_type ib_type
)
687 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
688 /* Small IBs are better than big IBs, because the GPU goes idle quicker
689 * and there is less waiting for buffers and fences. Proof:
690 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
692 struct amdgpu_ib
*ib
= NULL
;
693 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
694 unsigned ib_size
= 0;
699 ib_size
= 4 * 1024 * 4;
702 unreachable("unhandled IB type");
705 if (!amdgpu_cs_has_chaining(cs
)) {
706 ib_size
= MAX2(ib_size
,
707 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
708 amdgpu_ib_max_submit_dwords(ib_type
)));
711 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
713 ib
->base
.prev_dw
= 0;
714 ib
->base
.num_prev
= 0;
715 ib
->base
.current
.cdw
= 0;
716 ib
->base
.current
.buf
= NULL
;
718 /* Allocate a new buffer for IBs if the current buffer is all used. */
719 if (!ib
->big_ib_buffer
||
720 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
721 if (!amdgpu_ib_new_buffer(aws
, ib
, cs
->ring_type
))
725 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
727 /* ib_bytes is in dwords and the conversion to bytes will be done before
729 ib
->ptr_ib_size
= &info
->ib_bytes
;
730 ib
->ptr_ib_size_inside_ib
= false;
732 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
733 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
735 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
737 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
738 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
742 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
744 if (ib
->ptr_ib_size_inside_ib
) {
745 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
746 S_3F2_CHAIN(1) | S_3F2_VALID(1);
748 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
752 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
754 amdgpu_set_ib_size(ib
);
755 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
756 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
759 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
760 enum ring_type ring_type
)
764 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
768 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
772 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
776 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_COMPUTE
;
780 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
785 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_GFX
;
789 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
790 cs
->last_added_bo
= NULL
;
794 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
798 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
799 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
800 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
802 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
803 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
804 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
806 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
807 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
808 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
810 for (i
= 0; i
< cs
->num_fence_dependencies
; i
++)
811 amdgpu_fence_reference(&cs
->fence_dependencies
[i
], NULL
);
813 cs
->num_real_buffers
= 0;
814 cs
->num_slab_buffers
= 0;
815 cs
->num_sparse_buffers
= 0;
816 cs
->num_fence_dependencies
= 0;
817 amdgpu_fence_reference(&cs
->fence
, NULL
);
819 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
820 cs
->last_added_bo
= NULL
;
823 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
825 amdgpu_cs_context_cleanup(cs
);
827 FREE(cs
->real_buffers
);
829 FREE(cs
->slab_buffers
);
830 FREE(cs
->sparse_buffers
);
831 FREE(cs
->fence_dependencies
);
835 static struct radeon_winsys_cs
*
836 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
837 enum ring_type ring_type
,
838 void (*flush
)(void *ctx
, unsigned flags
,
839 struct pipe_fence_handle
**fence
),
842 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
843 struct amdgpu_cs
*cs
;
845 cs
= CALLOC_STRUCT(amdgpu_cs
);
850 util_queue_fence_init(&cs
->flush_completed
);
853 cs
->flush_cs
= flush
;
854 cs
->flush_data
= flush_ctx
;
855 cs
->ring_type
= ring_type
;
857 struct amdgpu_cs_fence_info fence_info
;
858 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
859 fence_info
.offset
= cs
->ring_type
;
860 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
862 cs
->main
.ib_type
= IB_MAIN
;
864 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
869 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
870 amdgpu_destroy_cs_context(&cs
->csc1
);
875 /* Set the first submission context as current. */
879 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
880 amdgpu_destroy_cs_context(&cs
->csc2
);
881 amdgpu_destroy_cs_context(&cs
->csc1
);
886 p_atomic_inc(&ctx
->ws
->num_cs
);
887 return &cs
->main
.base
;
890 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
895 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
897 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
898 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
899 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
901 uint32_t *new_ptr_ib_size
;
903 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
905 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
908 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
910 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
913 if (!amdgpu_cs_has_chaining(cs
))
916 /* Allocate a new chunk */
917 if (rcs
->num_prev
>= rcs
->max_prev
) {
918 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
919 struct radeon_winsys_cs_chunk
*new_prev
;
921 new_prev
= REALLOC(rcs
->prev
,
922 sizeof(*new_prev
) * rcs
->max_prev
,
923 sizeof(*new_prev
) * new_max_prev
);
927 rcs
->prev
= new_prev
;
928 rcs
->max_prev
= new_max_prev
;
931 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
934 assert(ib
->used_ib_space
== 0);
935 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
937 /* This space was originally reserved. */
938 rcs
->current
.max_dw
+= 4;
939 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
941 /* Pad with NOPs and add INDIRECT_BUFFER packet */
942 while ((rcs
->current
.cdw
& 7) != 4)
943 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
945 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
946 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
947 radeon_emit(rcs
, va
);
948 radeon_emit(rcs
, va
>> 32);
949 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
951 assert((rcs
->current
.cdw
& 7) == 0);
952 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
954 amdgpu_set_ib_size(ib
);
955 ib
->ptr_ib_size
= new_ptr_ib_size
;
956 ib
->ptr_ib_size_inside_ib
= true;
958 /* Hook up the new chunk */
959 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
960 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
961 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
964 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
965 ib
->base
.current
.cdw
= 0;
967 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
968 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
970 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
971 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
976 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
977 struct radeon_bo_list_item
*list
)
979 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
983 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
984 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
985 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
986 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
989 return cs
->num_real_buffers
;
992 static unsigned add_fence_dependency_entry(struct amdgpu_cs_context
*cs
)
994 unsigned idx
= cs
->num_fence_dependencies
++;
996 if (idx
>= cs
->max_fence_dependencies
) {
998 const unsigned increment
= 8;
1000 cs
->max_fence_dependencies
= idx
+ increment
;
1001 size
= cs
->max_fence_dependencies
* sizeof(cs
->fence_dependencies
[0]);
1002 cs
->fence_dependencies
= realloc(cs
->fence_dependencies
, size
);
1003 /* Clear the newly-allocated elements. */
1004 memset(cs
->fence_dependencies
+ idx
, 0,
1005 increment
* sizeof(cs
->fence_dependencies
[0]));
1010 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1011 struct amdgpu_fence
*fence
)
1013 struct amdgpu_cs_context
*cs
= acs
->csc
;
1015 if (!amdgpu_fence_is_syncobj(fence
) &&
1016 fence
->ctx
== acs
->ctx
&&
1017 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1018 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1019 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1022 return amdgpu_fence_wait((void *)fence
, 0, false);
1025 static void amdgpu_cs_add_fence_dependency(struct radeon_winsys_cs
*rws
,
1026 struct pipe_fence_handle
*pfence
)
1028 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1029 struct amdgpu_cs_context
*cs
= acs
->csc
;
1030 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1032 if (is_noop_fence_dependency(acs
, fence
))
1035 unsigned idx
= add_fence_dependency_entry(cs
);
1036 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1037 (struct pipe_fence_handle
*)fence
);
1040 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1041 struct amdgpu_cs_buffer
*buffer
)
1043 struct amdgpu_cs_context
*cs
= acs
->csc
;
1044 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1045 unsigned new_num_fences
= 0;
1047 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1048 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1050 if (is_noop_fence_dependency(acs
, bo_fence
))
1053 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1056 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1059 unsigned idx
= add_fence_dependency_entry(cs
);
1060 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1061 (struct pipe_fence_handle
*)bo_fence
);
1064 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1065 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1067 bo
->num_fences
= new_num_fences
;
1070 /* Add the given list of fences to the buffer's fence list.
1072 * Must be called with the winsys bo_fence_lock held.
1074 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1075 unsigned num_fences
,
1076 struct pipe_fence_handle
**fences
)
1078 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1079 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1080 struct pipe_fence_handle
**new_fences
=
1082 bo
->num_fences
* sizeof(*new_fences
),
1083 new_max_fences
* sizeof(*new_fences
));
1084 if (likely(new_fences
)) {
1085 bo
->fences
= new_fences
;
1086 bo
->max_fences
= new_max_fences
;
1090 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1091 if (!bo
->num_fences
)
1094 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1095 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1097 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1103 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1104 bo
->fences
[bo
->num_fences
] = NULL
;
1105 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1110 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1111 struct pipe_fence_handle
*fence
,
1112 unsigned num_buffers
,
1113 struct amdgpu_cs_buffer
*buffers
)
1115 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1116 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1117 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1119 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1120 p_atomic_inc(&bo
->num_active_ioctls
);
1121 amdgpu_add_fences(bo
, 1, &fence
);
1125 /* Since the kernel driver doesn't synchronize execution between different
1126 * rings automatically, we have to add fence dependencies manually.
1128 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1130 struct amdgpu_cs_context
*cs
= acs
->csc
;
1132 cs
->num_fence_dependencies
= 0;
1134 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1135 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1136 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1139 /* Add backing of sparse buffers to the buffer list.
1141 * This is done late, during submission, to keep the buffer list short before
1142 * submit, and to avoid managing fences for the backing buffers.
1144 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1146 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1147 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1148 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1150 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
1152 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1153 /* We can directly add the buffer here, because we know that each
1154 * backing buffer occurs only once.
1156 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1158 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1159 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1163 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1164 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1165 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1168 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1174 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1176 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1177 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1178 struct amdgpu_cs_context
*cs
= acs
->cst
;
1180 amdgpu_bo_list_handle bo_list
= NULL
;
1181 uint64_t seq_no
= 0;
1182 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1184 /* Create the buffer list.
1185 * Use a buffer list containing all allocated buffers if requested.
1187 if (ws
->debug_all_bos
) {
1188 struct amdgpu_winsys_bo
*bo
;
1189 amdgpu_bo_handle
*handles
;
1192 simple_mtx_lock(&ws
->global_bo_list_lock
);
1194 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
1196 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1197 amdgpu_cs_context_cleanup(cs
);
1198 cs
->error_code
= -ENOMEM
;
1202 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1203 assert(num
< ws
->num_buffers
);
1204 handles
[num
++] = bo
->bo
;
1207 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1208 handles
, NULL
, &bo_list
);
1210 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1212 unsigned num_handles
;
1214 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1219 if (cs
->max_real_submit
< cs
->num_real_buffers
) {
1223 cs
->handles
= MALLOC(sizeof(*cs
->handles
) * cs
->num_real_buffers
);
1224 cs
->flags
= MALLOC(sizeof(*cs
->flags
) * cs
->num_real_buffers
);
1226 if (!cs
->handles
|| !cs
->flags
) {
1227 cs
->max_real_submit
= 0;
1234 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1235 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1237 if (buffer
->bo
->is_local
)
1240 assert(buffer
->u
.real
.priority_usage
!= 0);
1242 cs
->handles
[num_handles
] = buffer
->bo
->bo
;
1243 cs
->flags
[num_handles
] = (util_last_bit64(buffer
->u
.real
.priority_usage
) - 1) / 4;
1247 if (acs
->ring_type
== RING_GFX
)
1248 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1251 r
= amdgpu_bo_list_create(ws
->dev
, num_handles
,
1252 cs
->handles
, cs
->flags
, &bo_list
);
1260 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1261 amdgpu_fence_signalled(cs
->fence
);
1266 if (acs
->ctx
->num_rejected_cs
) {
1269 struct drm_amdgpu_cs_chunk chunks
[4];
1270 unsigned num_chunks
= 0;
1272 /* Convert from dwords to bytes. */
1273 cs
->ib
[IB_MAIN
].ib_bytes
*= 4;
1276 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1277 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1278 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1282 if (has_user_fence
) {
1283 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1284 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1285 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1290 unsigned num_dependencies
= cs
->num_fence_dependencies
;
1291 unsigned num_syncobj_dependencies
= 0;
1293 if (num_dependencies
) {
1294 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1295 alloca(num_dependencies
* sizeof(*dep_chunk
));
1298 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1299 struct amdgpu_fence
*fence
=
1300 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1302 if (amdgpu_fence_is_syncobj(fence
)) {
1303 num_syncobj_dependencies
++;
1307 assert(!fence
->submission_in_progress
);
1308 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[num
++]);
1311 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1312 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num
;
1313 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1317 /* Syncobj dependencies. */
1318 if (num_syncobj_dependencies
) {
1319 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1320 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1323 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1324 struct amdgpu_fence
*fence
=
1325 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1327 if (!amdgpu_fence_is_syncobj(fence
))
1330 assert(!fence
->submission_in_progress
);
1331 sem_chunk
[num
++].handle
= fence
->syncobj
;
1334 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1335 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num
;
1336 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1340 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1342 r
= amdgpu_cs_submit_raw(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1343 num_chunks
, chunks
, &seq_no
);
1349 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1350 else if (r
== -ECANCELED
)
1351 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1353 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1354 "see dmesg for more information (%i).\n", r
);
1356 amdgpu_fence_signalled(cs
->fence
);
1358 acs
->ctx
->num_rejected_cs
++;
1359 ws
->num_total_rejected_cs
++;
1362 uint64_t *user_fence
= NULL
;
1365 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1366 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1371 amdgpu_bo_list_destroy(bo_list
);
1374 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1375 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1376 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1377 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1378 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1379 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1381 amdgpu_cs_context_cleanup(cs
);
1384 /* Make sure the previous submission is completed. */
1385 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
1387 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1389 /* Wait for any pending ioctl of this CS to complete. */
1390 util_queue_fence_wait(&cs
->flush_completed
);
1393 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
1395 struct pipe_fence_handle
**fence
)
1397 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1398 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1401 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1403 switch (cs
->ring_type
) {
1405 /* pad DMA ring to 8 DWs */
1406 if (ws
->info
.chip_class
<= SI
) {
1407 while (rcs
->current
.cdw
& 7)
1408 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1410 while (rcs
->current
.cdw
& 7)
1411 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1415 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1416 if (ws
->info
.gfx_ib_pad_with_type2
) {
1417 while (rcs
->current
.cdw
& 7)
1418 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1420 while (rcs
->current
.cdw
& 7)
1421 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1423 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1426 while (rcs
->current
.cdw
& 15)
1427 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1430 while (rcs
->current
.cdw
& 15)
1431 radeon_emit(rcs
, 0x81ff); /* nop packet */
1437 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1438 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1441 /* If the CS is not empty or overflowed.... */
1442 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1443 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1444 !debug_get_option_noop())) {
1445 struct amdgpu_cs_context
*cur
= cs
->csc
;
1448 amdgpu_ib_finalize(&cs
->main
);
1450 /* Create a fence. */
1451 amdgpu_fence_reference(&cur
->fence
, NULL
);
1452 if (cs
->next_fence
) {
1453 /* just move the reference */
1454 cur
->fence
= cs
->next_fence
;
1455 cs
->next_fence
= NULL
;
1457 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1458 cur
->ib
[IB_MAIN
].ip_type
,
1459 cur
->ib
[IB_MAIN
].ip_instance
,
1460 cur
->ib
[IB_MAIN
].ring
);
1463 amdgpu_fence_reference(fence
, cur
->fence
);
1465 amdgpu_cs_sync_flush(rcs
);
1469 * This fence must be held until the submission is queued to ensure
1470 * that the order of fence dependency updates matches the order of
1473 simple_mtx_lock(&ws
->bo_fence_lock
);
1474 amdgpu_add_fence_dependencies_bo_lists(cs
);
1476 /* Swap command streams. "cst" is going to be submitted. */
1481 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1482 amdgpu_cs_submit_ib
, NULL
);
1483 /* The submission has been queued, unlock the fence now. */
1484 simple_mtx_unlock(&ws
->bo_fence_lock
);
1486 if (!(flags
& RADEON_FLUSH_ASYNC
)) {
1487 amdgpu_cs_sync_flush(rcs
);
1488 error_code
= cur
->error_code
;
1491 amdgpu_cs_context_cleanup(cs
->csc
);
1494 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1496 cs
->main
.base
.used_gart
= 0;
1497 cs
->main
.base
.used_vram
= 0;
1499 if (cs
->ring_type
== RING_GFX
)
1501 else if (cs
->ring_type
== RING_DMA
)
1507 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1509 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1511 amdgpu_cs_sync_flush(rcs
);
1512 util_queue_fence_destroy(&cs
->flush_completed
);
1513 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1514 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1515 FREE(cs
->main
.base
.prev
);
1516 amdgpu_destroy_cs_context(&cs
->csc1
);
1517 amdgpu_destroy_cs_context(&cs
->csc2
);
1518 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1522 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1523 struct pb_buffer
*_buf
,
1524 enum radeon_bo_usage usage
)
1526 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1527 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1529 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1532 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1534 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1535 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1536 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1537 ws
->base
.cs_create
= amdgpu_cs_create
;
1538 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1539 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1540 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1541 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1542 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1543 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1544 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1545 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1546 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1547 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1548 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1549 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1550 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1551 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;