2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
30 * Marek Olšák <maraeo@gmail.com>
33 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
36 #include <amdgpu_drm.h>
38 #include "amd/common/sid.h"
40 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
44 static struct pipe_fence_handle
*
45 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
46 unsigned ip_instance
, unsigned ring
)
48 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
50 fence
->reference
.count
= 1;
52 fence
->fence
.context
= ctx
->ctx
;
53 fence
->fence
.ip_type
= ip_type
;
54 fence
->fence
.ip_instance
= ip_instance
;
55 fence
->fence
.ring
= ring
;
56 fence
->submission_in_progress
= true;
57 p_atomic_inc(&ctx
->refcount
);
58 return (struct pipe_fence_handle
*)fence
;
61 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
62 struct amdgpu_cs_request
* request
,
63 uint64_t *user_fence_cpu_address
)
65 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
67 rfence
->fence
.fence
= request
->seq_no
;
68 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
69 rfence
->submission_in_progress
= false;
72 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
74 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
76 rfence
->signalled
= true;
77 rfence
->submission_in_progress
= false;
80 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
83 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
86 uint64_t *user_fence_cpu
;
89 if (rfence
->signalled
)
93 abs_timeout
= timeout
;
95 abs_timeout
= os_time_get_absolute_timeout(timeout
);
97 /* The fence might not have a number assigned if its IB is being
98 * submitted in the other thread right now. Wait until the submission
100 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
104 user_fence_cpu
= rfence
->user_fence_cpu_address
;
105 if (user_fence_cpu
) {
106 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
107 rfence
->signalled
= true;
111 /* No timeout, just query: no need for the ioctl. */
112 if (!absolute
&& !timeout
)
116 /* Now use the libdrm query. */
117 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
119 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
122 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
127 /* This variable can only transition from false to true, so it doesn't
128 * matter if threads race for it. */
129 rfence
->signalled
= true;
135 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
136 struct pipe_fence_handle
*fence
,
139 return amdgpu_fence_wait(fence
, timeout
, false);
142 static struct pipe_fence_handle
*
143 amdgpu_cs_get_next_fence(struct radeon_winsys_cs
*rcs
)
145 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
146 struct pipe_fence_handle
*fence
= NULL
;
148 if (debug_get_option_noop())
151 if (cs
->next_fence
) {
152 amdgpu_fence_reference(&fence
, cs
->next_fence
);
156 fence
= amdgpu_fence_create(cs
->ctx
,
157 cs
->csc
->request
.ip_type
,
158 cs
->csc
->request
.ip_instance
,
159 cs
->csc
->request
.ring
);
163 amdgpu_fence_reference(&cs
->next_fence
, fence
);
169 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
171 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
173 struct amdgpu_bo_alloc_request alloc_buffer
= {};
174 amdgpu_bo_handle buf_handle
;
179 ctx
->ws
= amdgpu_winsys(ws
);
181 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
183 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
185 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
189 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
190 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
191 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
193 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
195 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
196 goto error_user_fence_alloc
;
199 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
201 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
202 goto error_user_fence_map
;
205 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
206 ctx
->user_fence_bo
= buf_handle
;
208 return (struct radeon_winsys_ctx
*)ctx
;
210 error_user_fence_map
:
211 amdgpu_bo_free(buf_handle
);
212 error_user_fence_alloc
:
213 amdgpu_cs_ctx_free(ctx
->ctx
);
219 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
221 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
224 static enum pipe_reset_status
225 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
227 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
228 uint32_t result
, hangs
;
231 /* Return a failure due to a rejected command submission. */
232 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
233 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
234 PIPE_INNOCENT_CONTEXT_RESET
;
237 /* Return a failure due to a GPU hang. */
238 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
240 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
241 return PIPE_NO_RESET
;
245 case AMDGPU_CTX_GUILTY_RESET
:
246 return PIPE_GUILTY_CONTEXT_RESET
;
247 case AMDGPU_CTX_INNOCENT_RESET
:
248 return PIPE_INNOCENT_CONTEXT_RESET
;
249 case AMDGPU_CTX_UNKNOWN_RESET
:
250 return PIPE_UNKNOWN_CONTEXT_RESET
;
251 case AMDGPU_CTX_NO_RESET
:
253 return PIPE_NO_RESET
;
257 /* COMMAND SUBMISSION */
259 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
261 return cs
->request
.ip_type
!= AMDGPU_HW_IP_UVD
&&
262 cs
->request
.ip_type
!= AMDGPU_HW_IP_VCE
;
265 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
267 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
268 cs
->ring_type
== RING_GFX
;
271 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
273 if (ring_type
== RING_GFX
)
274 return 4; /* for chaining */
279 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
281 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
282 int i
= cs
->buffer_indices_hashlist
[hash
];
283 struct amdgpu_cs_buffer
*buffers
;
287 buffers
= cs
->real_buffers
;
288 num_buffers
= cs
->num_real_buffers
;
290 buffers
= cs
->slab_buffers
;
291 num_buffers
= cs
->num_slab_buffers
;
294 /* not found or found */
295 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
298 /* Hash collision, look for the BO in the list of buffers linearly. */
299 for (i
= num_buffers
- 1; i
>= 0; i
--) {
300 if (buffers
[i
].bo
== bo
) {
301 /* Put this buffer in the hash list.
302 * This will prevent additional hash collisions if there are
303 * several consecutive lookup_buffer calls for the same buffer.
305 * Example: Assuming buffers A,B,C collide in the hash list,
306 * the following sequence of buffers:
307 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
308 * will collide here: ^ and here: ^,
309 * meaning that we should get very few collisions in the end. */
310 cs
->buffer_indices_hashlist
[hash
] = i
;
318 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
320 struct amdgpu_cs_buffer
*buffer
;
323 /* New buffer, check if the backing array is large enough. */
324 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
326 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
327 struct amdgpu_cs_buffer
*new_buffers
;
328 amdgpu_bo_handle
*new_handles
;
331 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
332 new_handles
= MALLOC(new_max
* sizeof(*new_handles
));
333 new_flags
= MALLOC(new_max
* sizeof(*new_flags
));
335 if (!new_buffers
|| !new_handles
|| !new_flags
) {
336 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
343 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
344 memcpy(new_handles
, cs
->handles
, cs
->num_real_buffers
* sizeof(*new_handles
));
345 memcpy(new_flags
, cs
->flags
, cs
->num_real_buffers
* sizeof(*new_flags
));
347 FREE(cs
->real_buffers
);
351 cs
->max_real_buffers
= new_max
;
352 cs
->real_buffers
= new_buffers
;
353 cs
->handles
= new_handles
;
354 cs
->flags
= new_flags
;
357 idx
= cs
->num_real_buffers
;
358 buffer
= &cs
->real_buffers
[idx
];
360 memset(buffer
, 0, sizeof(*buffer
));
361 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
362 cs
->handles
[idx
] = bo
->bo
;
364 p_atomic_inc(&bo
->num_cs_references
);
365 cs
->num_real_buffers
++;
371 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
373 struct amdgpu_cs_context
*cs
= acs
->csc
;
375 int idx
= amdgpu_lookup_buffer(cs
, bo
);
380 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
382 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
383 cs
->buffer_indices_hashlist
[hash
] = idx
;
385 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
386 acs
->main
.base
.used_vram
+= bo
->base
.size
;
387 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
388 acs
->main
.base
.used_gart
+= bo
->base
.size
;
393 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
394 struct amdgpu_winsys_bo
*bo
)
396 struct amdgpu_cs_context
*cs
= acs
->csc
;
397 struct amdgpu_cs_buffer
*buffer
;
399 int idx
= amdgpu_lookup_buffer(cs
, bo
);
405 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
409 /* New buffer, check if the backing array is large enough. */
410 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
412 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
413 struct amdgpu_cs_buffer
*new_buffers
;
415 new_buffers
= REALLOC(cs
->slab_buffers
,
416 cs
->max_slab_buffers
* sizeof(*new_buffers
),
417 new_max
* sizeof(*new_buffers
));
419 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
423 cs
->max_slab_buffers
= new_max
;
424 cs
->slab_buffers
= new_buffers
;
427 idx
= cs
->num_slab_buffers
;
428 buffer
= &cs
->slab_buffers
[idx
];
430 memset(buffer
, 0, sizeof(*buffer
));
431 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
432 buffer
->u
.slab
.real_idx
= real_idx
;
433 p_atomic_inc(&bo
->num_cs_references
);
434 cs
->num_slab_buffers
++;
436 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
437 cs
->buffer_indices_hashlist
[hash
] = idx
;
442 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
443 struct pb_buffer
*buf
,
444 enum radeon_bo_usage usage
,
445 enum radeon_bo_domain domains
,
446 enum radeon_bo_priority priority
)
448 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
449 * the buffer placement during command submission.
451 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
452 struct amdgpu_cs_context
*cs
= acs
->csc
;
453 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
454 struct amdgpu_cs_buffer
*buffer
;
457 /* Fast exit for no-op calls.
458 * This is very effective with suballocators and linear uploaders that
459 * are outside of the winsys.
461 if (bo
== cs
->last_added_bo
&&
462 (usage
& cs
->last_added_bo_usage
) == usage
&&
463 (1ull << priority
) & cs
->last_added_bo_priority_usage
)
464 return cs
->last_added_bo_index
;
467 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
471 buffer
= &cs
->slab_buffers
[index
];
472 buffer
->usage
|= usage
;
474 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
475 index
= buffer
->u
.slab
.real_idx
;
477 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
482 buffer
= &cs
->real_buffers
[index
];
483 buffer
->u
.real
.priority_usage
|= 1llu << priority
;
484 buffer
->usage
|= usage
;
485 cs
->flags
[index
] = MAX2(cs
->flags
[index
], priority
/ 4);
487 cs
->last_added_bo
= bo
;
488 cs
->last_added_bo_index
= index
;
489 cs
->last_added_bo_usage
= buffer
->usage
;
490 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
494 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
496 struct pb_buffer
*pb
;
498 unsigned buffer_size
;
500 /* Always create a buffer that is at least as large as the maximum seen IB
501 * size, aligned to a power of two (and multiplied by 4 to reduce internal
502 * fragmentation if chaining is not available). Limit to 512k dwords, which
503 * is the largest power of two that fits into the size field of the
504 * INDIRECT_BUFFER packet.
506 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
507 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
509 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
511 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
513 switch (ib
->ib_type
) {
514 case IB_CONST_PREAMBLE
:
515 buffer_size
= MAX2(buffer_size
, 4 * 1024);
518 buffer_size
= MAX2(buffer_size
, 16 * 1024 * 4);
521 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
524 unreachable("unhandled IB type");
527 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
528 ws
->info
.gart_page_size
,
530 RADEON_FLAG_CPU_ACCESS
);
534 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
536 pb_reference(&pb
, NULL
);
540 pb_reference(&ib
->big_ib_buffer
, pb
);
541 pb_reference(&pb
, NULL
);
543 ib
->ib_mapped
= mapped
;
544 ib
->used_ib_space
= 0;
549 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
553 /* Smaller submits means the GPU gets busy sooner and there is less
554 * waiting for buffers and fences. Proof:
555 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
558 case IB_CONST_PREAMBLE
:
560 /* There isn't really any reason to limit CE IB size beyond the natural
561 * limit implied by the main IB, except perhaps GTT size. Just return
562 * an extremely large value that we never get anywhere close to.
564 return 16 * 1024 * 1024;
566 unreachable("bad ib_type");
570 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
571 enum ib_type ib_type
)
573 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
574 /* Small IBs are better than big IBs, because the GPU goes idle quicker
575 * and there is less waiting for buffers and fences. Proof:
576 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
578 struct amdgpu_ib
*ib
= NULL
;
579 struct amdgpu_cs_ib_info
*info
= &cs
->csc
->ib
[ib_type
];
580 unsigned ib_size
= 0;
583 case IB_CONST_PREAMBLE
:
584 ib
= &cs
->const_preamble_ib
;
589 ib_size
= 8 * 1024 * 4;
593 ib_size
= 4 * 1024 * 4;
596 unreachable("unhandled IB type");
599 if (!amdgpu_cs_has_chaining(cs
)) {
600 ib_size
= MAX2(ib_size
,
601 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
602 amdgpu_ib_max_submit_dwords(ib_type
)));
605 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
607 ib
->base
.prev_dw
= 0;
608 ib
->base
.num_prev
= 0;
609 ib
->base
.current
.cdw
= 0;
610 ib
->base
.current
.buf
= NULL
;
612 /* Allocate a new buffer for IBs if the current buffer is all used. */
613 if (!ib
->big_ib_buffer
||
614 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
615 if (!amdgpu_ib_new_buffer(aws
, ib
))
619 info
->ib_mc_address
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+
622 ib
->ptr_ib_size
= &info
->size
;
624 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
625 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
627 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
629 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
630 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
634 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
636 *ib
->ptr_ib_size
|= ib
->base
.current
.cdw
;
637 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
638 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
641 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
642 enum ring_type ring_type
)
648 cs
->request
.ip_type
= AMDGPU_HW_IP_DMA
;
652 cs
->request
.ip_type
= AMDGPU_HW_IP_UVD
;
656 cs
->request
.ip_type
= AMDGPU_HW_IP_VCE
;
660 cs
->request
.ip_type
= AMDGPU_HW_IP_COMPUTE
;
665 cs
->request
.ip_type
= AMDGPU_HW_IP_GFX
;
669 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
670 cs
->buffer_indices_hashlist
[i
] = -1;
672 cs
->last_added_bo
= NULL
;
674 cs
->request
.number_of_ibs
= 1;
675 cs
->request
.ibs
= &cs
->ib
[IB_MAIN
];
677 cs
->ib
[IB_CONST
].flags
= AMDGPU_IB_FLAG_CE
;
678 cs
->ib
[IB_CONST_PREAMBLE
].flags
= AMDGPU_IB_FLAG_CE
|
679 AMDGPU_IB_FLAG_PREAMBLE
;
684 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
688 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
689 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
690 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
692 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
693 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
694 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
697 cs
->num_real_buffers
= 0;
698 cs
->num_slab_buffers
= 0;
699 amdgpu_fence_reference(&cs
->fence
, NULL
);
701 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
702 cs
->buffer_indices_hashlist
[i
] = -1;
704 cs
->last_added_bo
= NULL
;
707 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
709 amdgpu_cs_context_cleanup(cs
);
711 FREE(cs
->real_buffers
);
713 FREE(cs
->slab_buffers
);
714 FREE(cs
->request
.dependencies
);
718 static struct radeon_winsys_cs
*
719 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
720 enum ring_type ring_type
,
721 void (*flush
)(void *ctx
, unsigned flags
,
722 struct pipe_fence_handle
**fence
),
725 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
726 struct amdgpu_cs
*cs
;
728 cs
= CALLOC_STRUCT(amdgpu_cs
);
733 util_queue_fence_init(&cs
->flush_completed
);
736 cs
->flush_cs
= flush
;
737 cs
->flush_data
= flush_ctx
;
738 cs
->ring_type
= ring_type
;
740 cs
->main
.ib_type
= IB_MAIN
;
741 cs
->const_ib
.ib_type
= IB_CONST
;
742 cs
->const_preamble_ib
.ib_type
= IB_CONST_PREAMBLE
;
744 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
749 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
750 amdgpu_destroy_cs_context(&cs
->csc1
);
755 /* Set the first submission context as current. */
759 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
760 amdgpu_destroy_cs_context(&cs
->csc2
);
761 amdgpu_destroy_cs_context(&cs
->csc1
);
766 p_atomic_inc(&ctx
->ws
->num_cs
);
767 return &cs
->main
.base
;
770 static struct radeon_winsys_cs
*
771 amdgpu_cs_add_const_ib(struct radeon_winsys_cs
*rcs
)
773 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
774 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
776 /* only one const IB can be added */
777 if (cs
->ring_type
!= RING_GFX
|| cs
->const_ib
.ib_mapped
)
780 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
))
783 cs
->csc
->request
.number_of_ibs
= 2;
784 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST
];
786 cs
->cst
->request
.number_of_ibs
= 2;
787 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST
];
789 return &cs
->const_ib
.base
;
792 static struct radeon_winsys_cs
*
793 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs
*rcs
)
795 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
796 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
798 /* only one const preamble IB can be added and only when the const IB has
799 * also been mapped */
800 if (cs
->ring_type
!= RING_GFX
|| !cs
->const_ib
.ib_mapped
||
801 cs
->const_preamble_ib
.ib_mapped
)
804 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
))
807 cs
->csc
->request
.number_of_ibs
= 3;
808 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST_PREAMBLE
];
810 cs
->cst
->request
.number_of_ibs
= 3;
811 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST_PREAMBLE
];
813 return &cs
->const_preamble_ib
.base
;
816 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
821 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
823 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
824 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
825 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
827 uint32_t *new_ptr_ib_size
;
829 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
831 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
834 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
836 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
839 if (!amdgpu_cs_has_chaining(cs
))
842 /* Allocate a new chunk */
843 if (rcs
->num_prev
>= rcs
->max_prev
) {
844 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
845 struct radeon_winsys_cs_chunk
*new_prev
;
847 new_prev
= REALLOC(rcs
->prev
,
848 sizeof(*new_prev
) * rcs
->max_prev
,
849 sizeof(*new_prev
) * new_max_prev
);
853 rcs
->prev
= new_prev
;
854 rcs
->max_prev
= new_max_prev
;
857 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
))
860 assert(ib
->used_ib_space
== 0);
861 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
863 /* This space was originally reserved. */
864 rcs
->current
.max_dw
+= 4;
865 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
867 /* Pad with NOPs and add INDIRECT_BUFFER packet */
868 while ((rcs
->current
.cdw
& 7) != 4)
869 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
871 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
872 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
873 radeon_emit(rcs
, va
);
874 radeon_emit(rcs
, va
>> 32);
875 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
];
876 radeon_emit(rcs
, S_3F2_CHAIN(1) | S_3F2_VALID(1));
878 assert((rcs
->current
.cdw
& 7) == 0);
879 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
881 *ib
->ptr_ib_size
|= rcs
->current
.cdw
;
882 ib
->ptr_ib_size
= new_ptr_ib_size
;
884 /* Hook up the new chunk */
885 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
886 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
887 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
890 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
891 ib
->base
.current
.cdw
= 0;
893 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
894 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
896 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
897 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
902 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
903 struct radeon_bo_list_item
*list
)
905 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
909 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
910 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
911 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
912 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
915 return cs
->num_real_buffers
;
918 DEBUG_GET_ONCE_BOOL_OPTION(all_bos
, "RADEON_ALL_BOS", false)
920 static void amdgpu_add_fence_dependency(struct amdgpu_cs
*acs
,
921 struct amdgpu_cs_buffer
*buffer
)
923 struct amdgpu_cs_context
*cs
= acs
->csc
;
924 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
925 struct amdgpu_cs_fence
*dep
;
926 unsigned new_num_fences
= 0;
928 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
929 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
932 if (bo_fence
->ctx
== acs
->ctx
&&
933 bo_fence
->fence
.ip_type
== cs
->request
.ip_type
&&
934 bo_fence
->fence
.ip_instance
== cs
->request
.ip_instance
&&
935 bo_fence
->fence
.ring
== cs
->request
.ring
)
938 if (amdgpu_fence_wait((void *)bo_fence
, 0, false))
941 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
944 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
947 if (bo_fence
->submission_in_progress
)
948 os_wait_until_zero(&bo_fence
->submission_in_progress
,
949 PIPE_TIMEOUT_INFINITE
);
951 idx
= cs
->request
.number_of_dependencies
++;
952 if (idx
>= cs
->max_dependencies
) {
955 cs
->max_dependencies
= idx
+ 8;
956 size
= cs
->max_dependencies
* sizeof(struct amdgpu_cs_fence
);
957 cs
->request
.dependencies
= realloc(cs
->request
.dependencies
, size
);
960 dep
= &cs
->request
.dependencies
[idx
];
961 memcpy(dep
, &bo_fence
->fence
, sizeof(*dep
));
964 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
965 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
967 bo
->num_fences
= new_num_fences
;
970 static void amdgpu_add_fence(struct amdgpu_winsys_bo
*bo
,
971 struct pipe_fence_handle
*fence
)
973 if (bo
->num_fences
>= bo
->max_fences
) {
974 unsigned new_max_fences
= MAX2(1, bo
->max_fences
* 2);
975 struct pipe_fence_handle
**new_fences
=
977 bo
->num_fences
* sizeof(*new_fences
),
978 new_max_fences
* sizeof(*new_fences
));
980 bo
->fences
= new_fences
;
981 bo
->max_fences
= new_max_fences
;
983 fprintf(stderr
, "amdgpu_add_fence: allocation failure, dropping fence\n");
987 bo
->num_fences
--; /* prefer to keep a more recent fence if possible */
988 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
992 bo
->fences
[bo
->num_fences
] = NULL
;
993 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fence
);
997 /* Since the kernel driver doesn't synchronize execution between different
998 * rings automatically, we have to add fence dependencies manually.
1000 static void amdgpu_add_fence_dependencies(struct amdgpu_cs
*acs
)
1002 struct amdgpu_cs_context
*cs
= acs
->csc
;
1003 unsigned num_buffers
;
1006 cs
->request
.number_of_dependencies
= 0;
1008 num_buffers
= cs
->num_real_buffers
;
1009 for (i
= 0; i
< num_buffers
; i
++) {
1010 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1011 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1013 amdgpu_add_fence_dependency(acs
, buffer
);
1014 p_atomic_inc(&bo
->num_active_ioctls
);
1015 amdgpu_add_fence(bo
, cs
->fence
);
1018 num_buffers
= cs
->num_slab_buffers
;
1019 for (i
= 0; i
< num_buffers
; i
++) {
1020 struct amdgpu_cs_buffer
*buffer
= &cs
->slab_buffers
[i
];
1021 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1023 amdgpu_add_fence_dependency(acs
, buffer
);
1024 p_atomic_inc(&bo
->num_active_ioctls
);
1025 amdgpu_add_fence(bo
, cs
->fence
);
1029 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1031 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1032 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1033 struct amdgpu_cs_context
*cs
= acs
->cst
;
1036 cs
->request
.fence_info
.handle
= NULL
;
1037 if (amdgpu_cs_has_user_fence(cs
)) {
1038 cs
->request
.fence_info
.handle
= acs
->ctx
->user_fence_bo
;
1039 cs
->request
.fence_info
.offset
= acs
->ring_type
;
1042 /* Create the buffer list.
1043 * Use a buffer list containing all allocated buffers if requested.
1045 if (debug_get_option_all_bos()) {
1046 struct amdgpu_winsys_bo
*bo
;
1047 amdgpu_bo_handle
*handles
;
1050 mtx_lock(&ws
->global_bo_list_lock
);
1052 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
1054 mtx_unlock(&ws
->global_bo_list_lock
);
1055 amdgpu_cs_context_cleanup(cs
);
1056 cs
->error_code
= -ENOMEM
;
1060 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1061 assert(num
< ws
->num_buffers
);
1062 handles
[num
++] = bo
->bo
;
1065 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1067 &cs
->request
.resources
);
1069 mtx_unlock(&ws
->global_bo_list_lock
);
1071 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_real_buffers
,
1072 cs
->handles
, cs
->flags
,
1073 &cs
->request
.resources
);
1077 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1078 cs
->request
.resources
= NULL
;
1079 amdgpu_fence_signalled(cs
->fence
);
1084 if (acs
->ctx
->num_rejected_cs
)
1087 r
= amdgpu_cs_submit(acs
->ctx
->ctx
, 0, &cs
->request
, 1);
1092 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1093 else if (r
== -ECANCELED
)
1094 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1096 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1097 "see dmesg for more information (%i).\n", r
);
1099 amdgpu_fence_signalled(cs
->fence
);
1101 acs
->ctx
->num_rejected_cs
++;
1102 ws
->num_total_rejected_cs
++;
1105 uint64_t *user_fence
= NULL
;
1106 if (amdgpu_cs_has_user_fence(cs
))
1107 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+
1108 cs
->request
.fence_info
.offset
;
1109 amdgpu_fence_submitted(cs
->fence
, &cs
->request
, user_fence
);
1113 if (cs
->request
.resources
)
1114 amdgpu_bo_list_destroy(cs
->request
.resources
);
1117 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1118 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1119 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1120 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1122 amdgpu_cs_context_cleanup(cs
);
1125 /* Make sure the previous submission is completed. */
1126 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
1128 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1130 /* Wait for any pending ioctl of this CS to complete. */
1131 util_queue_fence_wait(&cs
->flush_completed
);
1134 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
1136 struct pipe_fence_handle
**fence
)
1138 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1139 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1142 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1144 switch (cs
->ring_type
) {
1146 /* pad DMA ring to 8 DWs */
1147 if (ws
->info
.chip_class
<= SI
) {
1148 while (rcs
->current
.cdw
& 7)
1149 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1151 while (rcs
->current
.cdw
& 7)
1152 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1156 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1157 if (ws
->info
.gfx_ib_pad_with_type2
) {
1158 while (rcs
->current
.cdw
& 7)
1159 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1161 while (rcs
->current
.cdw
& 7)
1162 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1165 /* Also pad the const IB. */
1166 if (cs
->const_ib
.ib_mapped
)
1167 while (!cs
->const_ib
.base
.current
.cdw
|| (cs
->const_ib
.base
.current
.cdw
& 7))
1168 radeon_emit(&cs
->const_ib
.base
, 0xffff1000); /* type3 nop packet */
1170 if (cs
->const_preamble_ib
.ib_mapped
)
1171 while (!cs
->const_preamble_ib
.base
.current
.cdw
|| (cs
->const_preamble_ib
.base
.current
.cdw
& 7))
1172 radeon_emit(&cs
->const_preamble_ib
.base
, 0xffff1000);
1175 while (rcs
->current
.cdw
& 15)
1176 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1182 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1183 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1186 /* If the CS is not empty or overflowed.... */
1187 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1188 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1189 !debug_get_option_noop())) {
1190 struct amdgpu_cs_context
*cur
= cs
->csc
;
1193 amdgpu_ib_finalize(&cs
->main
);
1195 if (cs
->const_ib
.ib_mapped
)
1196 amdgpu_ib_finalize(&cs
->const_ib
);
1198 if (cs
->const_preamble_ib
.ib_mapped
)
1199 amdgpu_ib_finalize(&cs
->const_preamble_ib
);
1201 /* Create a fence. */
1202 amdgpu_fence_reference(&cur
->fence
, NULL
);
1203 if (cs
->next_fence
) {
1204 /* just move the reference */
1205 cur
->fence
= cs
->next_fence
;
1206 cs
->next_fence
= NULL
;
1208 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1209 cur
->request
.ip_type
,
1210 cur
->request
.ip_instance
,
1214 amdgpu_fence_reference(fence
, cur
->fence
);
1216 amdgpu_cs_sync_flush(rcs
);
1220 * This fence must be held until the submission is queued to ensure
1221 * that the order of fence dependency updates matches the order of
1224 mtx_lock(&ws
->bo_fence_lock
);
1225 amdgpu_add_fence_dependencies(cs
);
1227 /* Swap command streams. "cst" is going to be submitted. */
1232 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1233 amdgpu_cs_submit_ib
, NULL
);
1234 /* The submission has been queued, unlock the fence now. */
1235 mtx_unlock(&ws
->bo_fence_lock
);
1237 if (!(flags
& RADEON_FLUSH_ASYNC
)) {
1238 amdgpu_cs_sync_flush(rcs
);
1239 error_code
= cur
->error_code
;
1242 amdgpu_cs_context_cleanup(cs
->csc
);
1245 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1246 if (cs
->const_ib
.ib_mapped
)
1247 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
);
1248 if (cs
->const_preamble_ib
.ib_mapped
)
1249 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
);
1251 cs
->main
.base
.used_gart
= 0;
1252 cs
->main
.base
.used_vram
= 0;
1254 if (cs
->ring_type
== RING_GFX
)
1256 else if (cs
->ring_type
== RING_DMA
)
1262 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1264 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1266 amdgpu_cs_sync_flush(rcs
);
1267 util_queue_fence_destroy(&cs
->flush_completed
);
1268 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1269 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1270 FREE(cs
->main
.base
.prev
);
1271 pb_reference(&cs
->const_ib
.big_ib_buffer
, NULL
);
1272 FREE(cs
->const_ib
.base
.prev
);
1273 pb_reference(&cs
->const_preamble_ib
.big_ib_buffer
, NULL
);
1274 FREE(cs
->const_preamble_ib
.base
.prev
);
1275 amdgpu_destroy_cs_context(&cs
->csc1
);
1276 amdgpu_destroy_cs_context(&cs
->csc2
);
1277 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1281 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1282 struct pb_buffer
*_buf
,
1283 enum radeon_bo_usage usage
)
1285 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1286 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1288 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1291 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1293 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1294 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1295 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1296 ws
->base
.cs_create
= amdgpu_cs_create
;
1297 ws
->base
.cs_add_const_ib
= amdgpu_cs_add_const_ib
;
1298 ws
->base
.cs_add_const_preamble_ib
= amdgpu_cs_add_const_preamble_ib
;
1299 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1300 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1301 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1302 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1303 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1304 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1305 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1306 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1307 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1308 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1309 ws
->base
.fence_reference
= amdgpu_fence_reference
;