2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
34 #include "amd/common/sid.h"
36 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
40 static struct pipe_fence_handle
*
41 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
42 unsigned ip_instance
, unsigned ring
)
44 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
46 fence
->reference
.count
= 1;
49 fence
->fence
.context
= ctx
->ctx
;
50 fence
->fence
.ip_type
= ip_type
;
51 fence
->fence
.ip_instance
= ip_instance
;
52 fence
->fence
.ring
= ring
;
53 util_queue_fence_init(&fence
->submitted
);
54 util_queue_fence_reset(&fence
->submitted
);
55 p_atomic_inc(&ctx
->refcount
);
56 return (struct pipe_fence_handle
*)fence
;
59 static struct pipe_fence_handle
*
60 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
62 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
63 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
68 pipe_reference_init(&fence
->reference
, 1);
70 /* fence->ctx == NULL means that the fence is syncobj-based. */
72 /* Convert sync_file into syncobj. */
73 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
79 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
81 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
86 util_queue_fence_init(&fence
->submitted
);
88 return (struct pipe_fence_handle
*)fence
;
91 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
92 struct pipe_fence_handle
*pfence
)
94 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
95 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
97 if (amdgpu_fence_is_syncobj(fence
)) {
100 /* Convert syncobj into sync_file. */
101 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
105 util_queue_fence_wait(&fence
->submitted
);
107 /* Convert the amdgpu fence into a fence FD. */
109 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
110 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
117 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
119 uint64_t *user_fence_cpu_address
)
121 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
123 rfence
->fence
.fence
= seq_no
;
124 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
125 util_queue_fence_signal(&rfence
->submitted
);
128 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
130 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
132 rfence
->signalled
= true;
133 util_queue_fence_signal(&rfence
->submitted
);
136 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
139 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
142 uint64_t *user_fence_cpu
;
145 if (rfence
->signalled
)
148 /* Handle syncobjs. */
149 if (amdgpu_fence_is_syncobj(rfence
)) {
150 /* Absolute timeouts are only be used by BO fences, which aren't
151 * backed by syncobjs.
155 if (amdgpu_cs_syncobj_wait(rfence
->ws
->dev
, &rfence
->syncobj
, 1,
159 rfence
->signalled
= true;
164 abs_timeout
= timeout
;
166 abs_timeout
= os_time_get_absolute_timeout(timeout
);
168 /* The fence might not have a number assigned if its IB is being
169 * submitted in the other thread right now. Wait until the submission
171 if (!util_queue_fence_wait_timeout(&rfence
->submitted
, abs_timeout
))
174 user_fence_cpu
= rfence
->user_fence_cpu_address
;
175 if (user_fence_cpu
) {
176 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
177 rfence
->signalled
= true;
181 /* No timeout, just query: no need for the ioctl. */
182 if (!absolute
&& !timeout
)
186 /* Now use the libdrm query. */
187 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
189 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
192 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
197 /* This variable can only transition from false to true, so it doesn't
198 * matter if threads race for it. */
199 rfence
->signalled
= true;
205 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
206 struct pipe_fence_handle
*fence
,
209 return amdgpu_fence_wait(fence
, timeout
, false);
212 static struct pipe_fence_handle
*
213 amdgpu_cs_get_next_fence(struct radeon_winsys_cs
*rcs
)
215 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
216 struct pipe_fence_handle
*fence
= NULL
;
218 if (debug_get_option_noop())
221 if (cs
->next_fence
) {
222 amdgpu_fence_reference(&fence
, cs
->next_fence
);
226 fence
= amdgpu_fence_create(cs
->ctx
,
227 cs
->csc
->ib
[IB_MAIN
].ip_type
,
228 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
229 cs
->csc
->ib
[IB_MAIN
].ring
);
233 amdgpu_fence_reference(&cs
->next_fence
, fence
);
239 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
241 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
243 struct amdgpu_bo_alloc_request alloc_buffer
= {};
244 amdgpu_bo_handle buf_handle
;
249 ctx
->ws
= amdgpu_winsys(ws
);
251 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
253 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
255 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
259 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
260 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
261 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
263 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
265 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
266 goto error_user_fence_alloc
;
269 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
271 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
272 goto error_user_fence_map
;
275 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
276 ctx
->user_fence_bo
= buf_handle
;
278 return (struct radeon_winsys_ctx
*)ctx
;
280 error_user_fence_map
:
281 amdgpu_bo_free(buf_handle
);
282 error_user_fence_alloc
:
283 amdgpu_cs_ctx_free(ctx
->ctx
);
289 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
291 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
294 static enum pipe_reset_status
295 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
297 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
298 uint32_t result
, hangs
;
301 /* Return a failure due to a rejected command submission. */
302 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
303 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
304 PIPE_INNOCENT_CONTEXT_RESET
;
307 /* Return a failure due to a GPU hang. */
308 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
310 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
311 return PIPE_NO_RESET
;
315 case AMDGPU_CTX_GUILTY_RESET
:
316 return PIPE_GUILTY_CONTEXT_RESET
;
317 case AMDGPU_CTX_INNOCENT_RESET
:
318 return PIPE_INNOCENT_CONTEXT_RESET
;
319 case AMDGPU_CTX_UNKNOWN_RESET
:
320 return PIPE_UNKNOWN_CONTEXT_RESET
;
321 case AMDGPU_CTX_NO_RESET
:
323 return PIPE_NO_RESET
;
327 /* COMMAND SUBMISSION */
329 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
331 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
332 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
333 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
&&
334 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_ENC
;
337 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
339 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
340 cs
->ring_type
== RING_GFX
;
343 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
345 if (ring_type
== RING_GFX
)
346 return 4; /* for chaining */
351 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
353 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
354 int i
= cs
->buffer_indices_hashlist
[hash
];
355 struct amdgpu_cs_buffer
*buffers
;
359 buffers
= cs
->real_buffers
;
360 num_buffers
= cs
->num_real_buffers
;
361 } else if (!bo
->sparse
) {
362 buffers
= cs
->slab_buffers
;
363 num_buffers
= cs
->num_slab_buffers
;
365 buffers
= cs
->sparse_buffers
;
366 num_buffers
= cs
->num_sparse_buffers
;
369 /* not found or found */
370 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
373 /* Hash collision, look for the BO in the list of buffers linearly. */
374 for (i
= num_buffers
- 1; i
>= 0; i
--) {
375 if (buffers
[i
].bo
== bo
) {
376 /* Put this buffer in the hash list.
377 * This will prevent additional hash collisions if there are
378 * several consecutive lookup_buffer calls for the same buffer.
380 * Example: Assuming buffers A,B,C collide in the hash list,
381 * the following sequence of buffers:
382 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
383 * will collide here: ^ and here: ^,
384 * meaning that we should get very few collisions in the end. */
385 cs
->buffer_indices_hashlist
[hash
] = i
;
393 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
395 struct amdgpu_cs_buffer
*buffer
;
398 /* New buffer, check if the backing array is large enough. */
399 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
401 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
402 struct amdgpu_cs_buffer
*new_buffers
;
404 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
407 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
412 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
414 FREE(cs
->real_buffers
);
416 cs
->max_real_buffers
= new_max
;
417 cs
->real_buffers
= new_buffers
;
420 idx
= cs
->num_real_buffers
;
421 buffer
= &cs
->real_buffers
[idx
];
423 memset(buffer
, 0, sizeof(*buffer
));
424 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
425 p_atomic_inc(&bo
->num_cs_references
);
426 cs
->num_real_buffers
++;
432 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
434 struct amdgpu_cs_context
*cs
= acs
->csc
;
436 int idx
= amdgpu_lookup_buffer(cs
, bo
);
441 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
443 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
444 cs
->buffer_indices_hashlist
[hash
] = idx
;
446 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
447 acs
->main
.base
.used_vram
+= bo
->base
.size
;
448 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
449 acs
->main
.base
.used_gart
+= bo
->base
.size
;
454 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
455 struct amdgpu_winsys_bo
*bo
)
457 struct amdgpu_cs_context
*cs
= acs
->csc
;
458 struct amdgpu_cs_buffer
*buffer
;
460 int idx
= amdgpu_lookup_buffer(cs
, bo
);
466 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
470 /* New buffer, check if the backing array is large enough. */
471 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
473 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
474 struct amdgpu_cs_buffer
*new_buffers
;
476 new_buffers
= REALLOC(cs
->slab_buffers
,
477 cs
->max_slab_buffers
* sizeof(*new_buffers
),
478 new_max
* sizeof(*new_buffers
));
480 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
484 cs
->max_slab_buffers
= new_max
;
485 cs
->slab_buffers
= new_buffers
;
488 idx
= cs
->num_slab_buffers
;
489 buffer
= &cs
->slab_buffers
[idx
];
491 memset(buffer
, 0, sizeof(*buffer
));
492 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
493 buffer
->u
.slab
.real_idx
= real_idx
;
494 p_atomic_inc(&bo
->num_cs_references
);
495 cs
->num_slab_buffers
++;
497 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
498 cs
->buffer_indices_hashlist
[hash
] = idx
;
503 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
504 struct amdgpu_winsys_bo
*bo
)
506 struct amdgpu_cs_context
*cs
= acs
->csc
;
507 struct amdgpu_cs_buffer
*buffer
;
509 int idx
= amdgpu_lookup_buffer(cs
, bo
);
514 /* New buffer, check if the backing array is large enough. */
515 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
517 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
518 struct amdgpu_cs_buffer
*new_buffers
;
520 new_buffers
= REALLOC(cs
->sparse_buffers
,
521 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
522 new_max
* sizeof(*new_buffers
));
524 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
528 cs
->max_sparse_buffers
= new_max
;
529 cs
->sparse_buffers
= new_buffers
;
532 idx
= cs
->num_sparse_buffers
;
533 buffer
= &cs
->sparse_buffers
[idx
];
535 memset(buffer
, 0, sizeof(*buffer
));
536 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
537 p_atomic_inc(&bo
->num_cs_references
);
538 cs
->num_sparse_buffers
++;
540 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
541 cs
->buffer_indices_hashlist
[hash
] = idx
;
543 /* We delay adding the backing buffers until we really have to. However,
544 * we cannot delay accounting for memory use.
546 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
548 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
549 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
550 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
551 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
552 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
555 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
560 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
561 struct pb_buffer
*buf
,
562 enum radeon_bo_usage usage
,
563 enum radeon_bo_domain domains
,
564 enum radeon_bo_priority priority
)
566 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
567 * the buffer placement during command submission.
569 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
570 struct amdgpu_cs_context
*cs
= acs
->csc
;
571 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
572 struct amdgpu_cs_buffer
*buffer
;
575 /* Fast exit for no-op calls.
576 * This is very effective with suballocators and linear uploaders that
577 * are outside of the winsys.
579 if (bo
== cs
->last_added_bo
&&
580 (usage
& cs
->last_added_bo_usage
) == usage
&&
581 (1ull << priority
) & cs
->last_added_bo_priority_usage
)
582 return cs
->last_added_bo_index
;
586 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
590 buffer
= &cs
->slab_buffers
[index
];
591 buffer
->usage
|= usage
;
593 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
594 index
= buffer
->u
.slab
.real_idx
;
596 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
601 buffer
= &cs
->real_buffers
[index
];
603 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
607 buffer
= &cs
->sparse_buffers
[index
];
610 buffer
->u
.real
.priority_usage
|= 1ull << priority
;
611 buffer
->usage
|= usage
;
613 cs
->last_added_bo
= bo
;
614 cs
->last_added_bo_index
= index
;
615 cs
->last_added_bo_usage
= buffer
->usage
;
616 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
620 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
,
621 enum ring_type ring_type
)
623 struct pb_buffer
*pb
;
625 unsigned buffer_size
;
627 /* Always create a buffer that is at least as large as the maximum seen IB
628 * size, aligned to a power of two (and multiplied by 4 to reduce internal
629 * fragmentation if chaining is not available). Limit to 512k dwords, which
630 * is the largest power of two that fits into the size field of the
631 * INDIRECT_BUFFER packet.
633 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
634 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
636 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
638 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
640 switch (ib
->ib_type
) {
642 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
645 unreachable("unhandled IB type");
648 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
649 ws
->info
.gart_page_size
,
651 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
652 (ring_type
== RING_GFX
||
653 ring_type
== RING_COMPUTE
||
654 ring_type
== RING_DMA
?
655 RADEON_FLAG_GTT_WC
: 0));
659 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
661 pb_reference(&pb
, NULL
);
665 pb_reference(&ib
->big_ib_buffer
, pb
);
666 pb_reference(&pb
, NULL
);
668 ib
->ib_mapped
= mapped
;
669 ib
->used_ib_space
= 0;
674 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
678 /* Smaller submits means the GPU gets busy sooner and there is less
679 * waiting for buffers and fences. Proof:
680 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
684 unreachable("bad ib_type");
688 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
689 enum ib_type ib_type
)
691 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
692 /* Small IBs are better than big IBs, because the GPU goes idle quicker
693 * and there is less waiting for buffers and fences. Proof:
694 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
696 struct amdgpu_ib
*ib
= NULL
;
697 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
698 unsigned ib_size
= 0;
703 ib_size
= 4 * 1024 * 4;
706 unreachable("unhandled IB type");
709 if (!amdgpu_cs_has_chaining(cs
)) {
710 ib_size
= MAX2(ib_size
,
711 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
712 amdgpu_ib_max_submit_dwords(ib_type
)));
715 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
717 ib
->base
.prev_dw
= 0;
718 ib
->base
.num_prev
= 0;
719 ib
->base
.current
.cdw
= 0;
720 ib
->base
.current
.buf
= NULL
;
722 /* Allocate a new buffer for IBs if the current buffer is all used. */
723 if (!ib
->big_ib_buffer
||
724 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
725 if (!amdgpu_ib_new_buffer(aws
, ib
, cs
->ring_type
))
729 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
731 /* ib_bytes is in dwords and the conversion to bytes will be done before
733 ib
->ptr_ib_size
= &info
->ib_bytes
;
734 ib
->ptr_ib_size_inside_ib
= false;
736 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
737 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
739 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
741 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
742 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
746 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
748 if (ib
->ptr_ib_size_inside_ib
) {
749 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
750 S_3F2_CHAIN(1) | S_3F2_VALID(1);
752 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
756 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
758 amdgpu_set_ib_size(ib
);
759 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
760 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
763 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
764 enum ring_type ring_type
)
768 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
772 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
776 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
780 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_COMPUTE
;
784 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
788 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_ENC
;
793 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_GFX
;
797 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
798 cs
->last_added_bo
= NULL
;
802 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
806 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
807 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
808 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
810 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
811 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
812 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
814 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
815 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
816 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
818 for (i
= 0; i
< cs
->num_fence_dependencies
; i
++)
819 amdgpu_fence_reference(&cs
->fence_dependencies
[i
], NULL
);
821 cs
->num_real_buffers
= 0;
822 cs
->num_slab_buffers
= 0;
823 cs
->num_sparse_buffers
= 0;
824 cs
->num_fence_dependencies
= 0;
825 amdgpu_fence_reference(&cs
->fence
, NULL
);
827 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
828 cs
->last_added_bo
= NULL
;
831 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
833 amdgpu_cs_context_cleanup(cs
);
835 FREE(cs
->real_buffers
);
837 FREE(cs
->slab_buffers
);
838 FREE(cs
->sparse_buffers
);
839 FREE(cs
->fence_dependencies
);
843 static struct radeon_winsys_cs
*
844 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
845 enum ring_type ring_type
,
846 void (*flush
)(void *ctx
, unsigned flags
,
847 struct pipe_fence_handle
**fence
),
850 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
851 struct amdgpu_cs
*cs
;
853 cs
= CALLOC_STRUCT(amdgpu_cs
);
858 util_queue_fence_init(&cs
->flush_completed
);
861 cs
->flush_cs
= flush
;
862 cs
->flush_data
= flush_ctx
;
863 cs
->ring_type
= ring_type
;
865 struct amdgpu_cs_fence_info fence_info
;
866 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
867 fence_info
.offset
= cs
->ring_type
;
868 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
870 cs
->main
.ib_type
= IB_MAIN
;
872 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
877 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
878 amdgpu_destroy_cs_context(&cs
->csc1
);
883 /* Set the first submission context as current. */
887 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
888 amdgpu_destroy_cs_context(&cs
->csc2
);
889 amdgpu_destroy_cs_context(&cs
->csc1
);
894 p_atomic_inc(&ctx
->ws
->num_cs
);
895 return &cs
->main
.base
;
898 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
903 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
905 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
906 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
907 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
909 uint32_t *new_ptr_ib_size
;
911 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
913 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
916 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
918 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
921 if (!amdgpu_cs_has_chaining(cs
))
924 /* Allocate a new chunk */
925 if (rcs
->num_prev
>= rcs
->max_prev
) {
926 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
927 struct radeon_winsys_cs_chunk
*new_prev
;
929 new_prev
= REALLOC(rcs
->prev
,
930 sizeof(*new_prev
) * rcs
->max_prev
,
931 sizeof(*new_prev
) * new_max_prev
);
935 rcs
->prev
= new_prev
;
936 rcs
->max_prev
= new_max_prev
;
939 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
942 assert(ib
->used_ib_space
== 0);
943 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
945 /* This space was originally reserved. */
946 rcs
->current
.max_dw
+= 4;
947 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
949 /* Pad with NOPs and add INDIRECT_BUFFER packet */
950 while ((rcs
->current
.cdw
& 7) != 4)
951 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
953 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
954 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
955 radeon_emit(rcs
, va
);
956 radeon_emit(rcs
, va
>> 32);
957 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
959 assert((rcs
->current
.cdw
& 7) == 0);
960 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
962 amdgpu_set_ib_size(ib
);
963 ib
->ptr_ib_size
= new_ptr_ib_size
;
964 ib
->ptr_ib_size_inside_ib
= true;
966 /* Hook up the new chunk */
967 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
968 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
969 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
972 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
973 ib
->base
.current
.cdw
= 0;
975 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
976 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
978 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
979 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
984 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
985 struct radeon_bo_list_item
*list
)
987 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
991 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
992 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
993 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
994 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
997 return cs
->num_real_buffers
;
1000 static unsigned add_fence_dependency_entry(struct amdgpu_cs_context
*cs
)
1002 unsigned idx
= cs
->num_fence_dependencies
++;
1004 if (idx
>= cs
->max_fence_dependencies
) {
1006 const unsigned increment
= 8;
1008 cs
->max_fence_dependencies
= idx
+ increment
;
1009 size
= cs
->max_fence_dependencies
* sizeof(cs
->fence_dependencies
[0]);
1010 cs
->fence_dependencies
= realloc(cs
->fence_dependencies
, size
);
1011 /* Clear the newly-allocated elements. */
1012 memset(cs
->fence_dependencies
+ idx
, 0,
1013 increment
* sizeof(cs
->fence_dependencies
[0]));
1018 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1019 struct amdgpu_fence
*fence
)
1021 struct amdgpu_cs_context
*cs
= acs
->csc
;
1023 if (!amdgpu_fence_is_syncobj(fence
) &&
1024 fence
->ctx
== acs
->ctx
&&
1025 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1026 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1027 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1030 return amdgpu_fence_wait((void *)fence
, 0, false);
1033 static void amdgpu_cs_add_fence_dependency(struct radeon_winsys_cs
*rws
,
1034 struct pipe_fence_handle
*pfence
)
1036 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1037 struct amdgpu_cs_context
*cs
= acs
->csc
;
1038 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1040 util_queue_fence_wait(&fence
->submitted
);
1042 if (is_noop_fence_dependency(acs
, fence
))
1045 unsigned idx
= add_fence_dependency_entry(cs
);
1046 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1047 (struct pipe_fence_handle
*)fence
);
1050 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1051 struct amdgpu_cs_buffer
*buffer
)
1053 struct amdgpu_cs_context
*cs
= acs
->csc
;
1054 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1055 unsigned new_num_fences
= 0;
1057 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1058 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1060 if (is_noop_fence_dependency(acs
, bo_fence
))
1063 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1066 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1069 unsigned idx
= add_fence_dependency_entry(cs
);
1070 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1071 (struct pipe_fence_handle
*)bo_fence
);
1074 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1075 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1077 bo
->num_fences
= new_num_fences
;
1080 /* Add the given list of fences to the buffer's fence list.
1082 * Must be called with the winsys bo_fence_lock held.
1084 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1085 unsigned num_fences
,
1086 struct pipe_fence_handle
**fences
)
1088 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1089 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1090 struct pipe_fence_handle
**new_fences
=
1092 bo
->num_fences
* sizeof(*new_fences
),
1093 new_max_fences
* sizeof(*new_fences
));
1094 if (likely(new_fences
)) {
1095 bo
->fences
= new_fences
;
1096 bo
->max_fences
= new_max_fences
;
1100 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1101 if (!bo
->num_fences
)
1104 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1105 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1107 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1113 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1114 bo
->fences
[bo
->num_fences
] = NULL
;
1115 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1120 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1121 struct pipe_fence_handle
*fence
,
1122 unsigned num_buffers
,
1123 struct amdgpu_cs_buffer
*buffers
)
1125 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1126 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1127 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1129 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1130 p_atomic_inc(&bo
->num_active_ioctls
);
1131 amdgpu_add_fences(bo
, 1, &fence
);
1135 /* Since the kernel driver doesn't synchronize execution between different
1136 * rings automatically, we have to add fence dependencies manually.
1138 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1140 struct amdgpu_cs_context
*cs
= acs
->csc
;
1142 cs
->num_fence_dependencies
= 0;
1144 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1145 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1146 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1149 /* Add backing of sparse buffers to the buffer list.
1151 * This is done late, during submission, to keep the buffer list short before
1152 * submit, and to avoid managing fences for the backing buffers.
1154 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1156 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1157 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1158 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1160 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
1162 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1163 /* We can directly add the buffer here, because we know that each
1164 * backing buffer occurs only once.
1166 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1168 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1169 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1173 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1174 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1175 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1178 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1184 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1186 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1187 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1188 struct amdgpu_cs_context
*cs
= acs
->cst
;
1190 amdgpu_bo_list_handle bo_list
= NULL
;
1191 uint64_t seq_no
= 0;
1192 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1194 /* Create the buffer list.
1195 * Use a buffer list containing all allocated buffers if requested.
1197 if (ws
->debug_all_bos
) {
1198 struct amdgpu_winsys_bo
*bo
;
1199 amdgpu_bo_handle
*handles
;
1202 simple_mtx_lock(&ws
->global_bo_list_lock
);
1204 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
1206 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1207 amdgpu_cs_context_cleanup(cs
);
1208 cs
->error_code
= -ENOMEM
;
1212 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1213 assert(num
< ws
->num_buffers
);
1214 handles
[num
++] = bo
->bo
;
1217 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1218 handles
, NULL
, &bo_list
);
1220 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1222 unsigned num_handles
;
1224 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1229 if (cs
->max_real_submit
< cs
->num_real_buffers
) {
1233 cs
->handles
= MALLOC(sizeof(*cs
->handles
) * cs
->num_real_buffers
);
1234 cs
->flags
= MALLOC(sizeof(*cs
->flags
) * cs
->num_real_buffers
);
1236 if (!cs
->handles
|| !cs
->flags
) {
1237 cs
->max_real_submit
= 0;
1244 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1245 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1247 if (buffer
->bo
->is_local
)
1250 assert(buffer
->u
.real
.priority_usage
!= 0);
1252 cs
->handles
[num_handles
] = buffer
->bo
->bo
;
1253 cs
->flags
[num_handles
] = (util_last_bit64(buffer
->u
.real
.priority_usage
) - 1) / 4;
1257 if (acs
->ring_type
== RING_GFX
)
1258 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1261 r
= amdgpu_bo_list_create(ws
->dev
, num_handles
,
1262 cs
->handles
, cs
->flags
, &bo_list
);
1270 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1271 amdgpu_fence_signalled(cs
->fence
);
1276 if (acs
->ctx
->num_rejected_cs
) {
1279 struct drm_amdgpu_cs_chunk chunks
[4];
1280 unsigned num_chunks
= 0;
1282 /* Convert from dwords to bytes. */
1283 cs
->ib
[IB_MAIN
].ib_bytes
*= 4;
1286 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1287 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1288 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1292 if (has_user_fence
) {
1293 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1294 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1295 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1300 unsigned num_dependencies
= cs
->num_fence_dependencies
;
1301 unsigned num_syncobj_dependencies
= 0;
1303 if (num_dependencies
) {
1304 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1305 alloca(num_dependencies
* sizeof(*dep_chunk
));
1308 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1309 struct amdgpu_fence
*fence
=
1310 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1312 if (amdgpu_fence_is_syncobj(fence
)) {
1313 num_syncobj_dependencies
++;
1317 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1318 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[num
++]);
1321 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1322 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num
;
1323 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1327 /* Syncobj dependencies. */
1328 if (num_syncobj_dependencies
) {
1329 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1330 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1333 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1334 struct amdgpu_fence
*fence
=
1335 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1337 if (!amdgpu_fence_is_syncobj(fence
))
1340 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1341 sem_chunk
[num
++].handle
= fence
->syncobj
;
1344 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1345 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num
;
1346 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1350 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1352 r
= amdgpu_cs_submit_raw(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1353 num_chunks
, chunks
, &seq_no
);
1359 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1360 else if (r
== -ECANCELED
)
1361 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1363 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1364 "see dmesg for more information (%i).\n", r
);
1366 amdgpu_fence_signalled(cs
->fence
);
1368 acs
->ctx
->num_rejected_cs
++;
1369 ws
->num_total_rejected_cs
++;
1372 uint64_t *user_fence
= NULL
;
1375 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1376 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1381 amdgpu_bo_list_destroy(bo_list
);
1384 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1385 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1386 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1387 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1388 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1389 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1391 amdgpu_cs_context_cleanup(cs
);
1394 /* Make sure the previous submission is completed. */
1395 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
1397 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1399 /* Wait for any pending ioctl of this CS to complete. */
1400 util_queue_fence_wait(&cs
->flush_completed
);
1403 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
1405 struct pipe_fence_handle
**fence
)
1407 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1408 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1411 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1413 switch (cs
->ring_type
) {
1415 /* pad DMA ring to 8 DWs */
1416 if (ws
->info
.chip_class
<= SI
) {
1417 while (rcs
->current
.cdw
& 7)
1418 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1420 while (rcs
->current
.cdw
& 7)
1421 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1425 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1426 if (ws
->info
.gfx_ib_pad_with_type2
) {
1427 while (rcs
->current
.cdw
& 7)
1428 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1430 while (rcs
->current
.cdw
& 7)
1431 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1433 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1436 while (rcs
->current
.cdw
& 15)
1437 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1440 while (rcs
->current
.cdw
& 15)
1441 radeon_emit(rcs
, 0x81ff); /* nop packet */
1447 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1448 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1451 /* If the CS is not empty or overflowed.... */
1452 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1453 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1454 !debug_get_option_noop())) {
1455 struct amdgpu_cs_context
*cur
= cs
->csc
;
1458 amdgpu_ib_finalize(&cs
->main
);
1460 /* Create a fence. */
1461 amdgpu_fence_reference(&cur
->fence
, NULL
);
1462 if (cs
->next_fence
) {
1463 /* just move the reference */
1464 cur
->fence
= cs
->next_fence
;
1465 cs
->next_fence
= NULL
;
1467 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1468 cur
->ib
[IB_MAIN
].ip_type
,
1469 cur
->ib
[IB_MAIN
].ip_instance
,
1470 cur
->ib
[IB_MAIN
].ring
);
1473 amdgpu_fence_reference(fence
, cur
->fence
);
1475 amdgpu_cs_sync_flush(rcs
);
1479 * This fence must be held until the submission is queued to ensure
1480 * that the order of fence dependency updates matches the order of
1483 simple_mtx_lock(&ws
->bo_fence_lock
);
1484 amdgpu_add_fence_dependencies_bo_lists(cs
);
1486 /* Swap command streams. "cst" is going to be submitted. */
1491 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1492 amdgpu_cs_submit_ib
, NULL
);
1493 /* The submission has been queued, unlock the fence now. */
1494 simple_mtx_unlock(&ws
->bo_fence_lock
);
1496 if (!(flags
& PIPE_FLUSH_ASYNC
)) {
1497 amdgpu_cs_sync_flush(rcs
);
1498 error_code
= cur
->error_code
;
1501 amdgpu_cs_context_cleanup(cs
->csc
);
1504 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1506 cs
->main
.base
.used_gart
= 0;
1507 cs
->main
.base
.used_vram
= 0;
1509 if (cs
->ring_type
== RING_GFX
)
1511 else if (cs
->ring_type
== RING_DMA
)
1517 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1519 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1521 amdgpu_cs_sync_flush(rcs
);
1522 util_queue_fence_destroy(&cs
->flush_completed
);
1523 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1524 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1525 FREE(cs
->main
.base
.prev
);
1526 amdgpu_destroy_cs_context(&cs
->csc1
);
1527 amdgpu_destroy_cs_context(&cs
->csc2
);
1528 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1532 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1533 struct pb_buffer
*_buf
,
1534 enum radeon_bo_usage usage
)
1536 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1537 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1539 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1542 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1544 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1545 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1546 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1547 ws
->base
.cs_create
= amdgpu_cs_create
;
1548 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1549 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1550 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1551 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1552 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1553 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1554 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1555 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1556 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1557 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1558 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1559 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1560 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1561 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;