2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "os/os_time.h"
33 #include "amd/common/sid.h"
35 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
39 static struct pipe_fence_handle
*
40 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
41 unsigned ip_instance
, unsigned ring
)
43 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
45 fence
->reference
.count
= 1;
48 fence
->fence
.context
= ctx
->ctx
;
49 fence
->fence
.ip_type
= ip_type
;
50 fence
->fence
.ip_instance
= ip_instance
;
51 fence
->fence
.ring
= ring
;
52 fence
->submission_in_progress
= true;
53 p_atomic_inc(&ctx
->refcount
);
54 return (struct pipe_fence_handle
*)fence
;
57 static struct pipe_fence_handle
*
58 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
60 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
61 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
66 pipe_reference_init(&fence
->reference
, 1);
68 /* fence->ctx == NULL means that the fence is syncobj-based. */
70 /* Convert sync_file into syncobj. */
71 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
77 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
79 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
83 return (struct pipe_fence_handle
*)fence
;
86 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
87 struct pipe_fence_handle
*pfence
)
89 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
90 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
92 if (amdgpu_fence_is_syncobj(fence
)) {
95 /* Convert syncobj into sync_file. */
96 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
100 os_wait_until_zero(&fence
->submission_in_progress
, PIPE_TIMEOUT_INFINITE
);
102 /* Convert the amdgpu fence into a fence FD. */
104 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
105 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
112 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
114 uint64_t *user_fence_cpu_address
)
116 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
118 rfence
->fence
.fence
= seq_no
;
119 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
120 rfence
->submission_in_progress
= false;
123 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
125 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
127 rfence
->signalled
= true;
128 rfence
->submission_in_progress
= false;
131 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
134 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
137 uint64_t *user_fence_cpu
;
140 if (rfence
->signalled
)
143 /* Handle syncobjs. */
144 if (amdgpu_fence_is_syncobj(rfence
)) {
145 /* Absolute timeouts are only be used by BO fences, which aren't
146 * backed by syncobjs.
150 if (amdgpu_cs_syncobj_wait(rfence
->ws
->dev
, &rfence
->syncobj
, 1,
154 rfence
->signalled
= true;
159 abs_timeout
= timeout
;
161 abs_timeout
= os_time_get_absolute_timeout(timeout
);
163 /* The fence might not have a number assigned if its IB is being
164 * submitted in the other thread right now. Wait until the submission
166 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
170 user_fence_cpu
= rfence
->user_fence_cpu_address
;
171 if (user_fence_cpu
) {
172 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
173 rfence
->signalled
= true;
177 /* No timeout, just query: no need for the ioctl. */
178 if (!absolute
&& !timeout
)
182 /* Now use the libdrm query. */
183 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
185 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
188 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
193 /* This variable can only transition from false to true, so it doesn't
194 * matter if threads race for it. */
195 rfence
->signalled
= true;
201 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
202 struct pipe_fence_handle
*fence
,
205 return amdgpu_fence_wait(fence
, timeout
, false);
208 static struct pipe_fence_handle
*
209 amdgpu_cs_get_next_fence(struct radeon_winsys_cs
*rcs
)
211 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
212 struct pipe_fence_handle
*fence
= NULL
;
214 if (debug_get_option_noop())
217 if (cs
->next_fence
) {
218 amdgpu_fence_reference(&fence
, cs
->next_fence
);
222 fence
= amdgpu_fence_create(cs
->ctx
,
223 cs
->csc
->ib
[IB_MAIN
].ip_type
,
224 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
225 cs
->csc
->ib
[IB_MAIN
].ring
);
229 amdgpu_fence_reference(&cs
->next_fence
, fence
);
235 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
237 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
239 struct amdgpu_bo_alloc_request alloc_buffer
= {};
240 amdgpu_bo_handle buf_handle
;
245 ctx
->ws
= amdgpu_winsys(ws
);
247 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
249 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
251 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
255 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
256 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
257 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
259 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
261 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
262 goto error_user_fence_alloc
;
265 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
267 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
268 goto error_user_fence_map
;
271 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
272 ctx
->user_fence_bo
= buf_handle
;
274 return (struct radeon_winsys_ctx
*)ctx
;
276 error_user_fence_map
:
277 amdgpu_bo_free(buf_handle
);
278 error_user_fence_alloc
:
279 amdgpu_cs_ctx_free(ctx
->ctx
);
285 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
287 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
290 static enum pipe_reset_status
291 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
293 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
294 uint32_t result
, hangs
;
297 /* Return a failure due to a rejected command submission. */
298 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
299 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
300 PIPE_INNOCENT_CONTEXT_RESET
;
303 /* Return a failure due to a GPU hang. */
304 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
306 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
307 return PIPE_NO_RESET
;
311 case AMDGPU_CTX_GUILTY_RESET
:
312 return PIPE_GUILTY_CONTEXT_RESET
;
313 case AMDGPU_CTX_INNOCENT_RESET
:
314 return PIPE_INNOCENT_CONTEXT_RESET
;
315 case AMDGPU_CTX_UNKNOWN_RESET
:
316 return PIPE_UNKNOWN_CONTEXT_RESET
;
317 case AMDGPU_CTX_NO_RESET
:
319 return PIPE_NO_RESET
;
323 /* COMMAND SUBMISSION */
325 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
327 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
328 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
329 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
;
332 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
334 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
335 cs
->ring_type
== RING_GFX
;
338 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
340 if (ring_type
== RING_GFX
)
341 return 4; /* for chaining */
346 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
348 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
349 int i
= cs
->buffer_indices_hashlist
[hash
];
350 struct amdgpu_cs_buffer
*buffers
;
354 buffers
= cs
->real_buffers
;
355 num_buffers
= cs
->num_real_buffers
;
356 } else if (!bo
->sparse
) {
357 buffers
= cs
->slab_buffers
;
358 num_buffers
= cs
->num_slab_buffers
;
360 buffers
= cs
->sparse_buffers
;
361 num_buffers
= cs
->num_sparse_buffers
;
364 /* not found or found */
365 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
368 /* Hash collision, look for the BO in the list of buffers linearly. */
369 for (i
= num_buffers
- 1; i
>= 0; i
--) {
370 if (buffers
[i
].bo
== bo
) {
371 /* Put this buffer in the hash list.
372 * This will prevent additional hash collisions if there are
373 * several consecutive lookup_buffer calls for the same buffer.
375 * Example: Assuming buffers A,B,C collide in the hash list,
376 * the following sequence of buffers:
377 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
378 * will collide here: ^ and here: ^,
379 * meaning that we should get very few collisions in the end. */
380 cs
->buffer_indices_hashlist
[hash
] = i
;
388 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
390 struct amdgpu_cs_buffer
*buffer
;
393 /* New buffer, check if the backing array is large enough. */
394 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
396 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
397 struct amdgpu_cs_buffer
*new_buffers
;
399 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
402 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
407 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
409 FREE(cs
->real_buffers
);
411 cs
->max_real_buffers
= new_max
;
412 cs
->real_buffers
= new_buffers
;
415 idx
= cs
->num_real_buffers
;
416 buffer
= &cs
->real_buffers
[idx
];
418 memset(buffer
, 0, sizeof(*buffer
));
419 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
420 p_atomic_inc(&bo
->num_cs_references
);
421 cs
->num_real_buffers
++;
427 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
429 struct amdgpu_cs_context
*cs
= acs
->csc
;
431 int idx
= amdgpu_lookup_buffer(cs
, bo
);
436 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
438 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
439 cs
->buffer_indices_hashlist
[hash
] = idx
;
441 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
442 acs
->main
.base
.used_vram
+= bo
->base
.size
;
443 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
444 acs
->main
.base
.used_gart
+= bo
->base
.size
;
449 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
450 struct amdgpu_winsys_bo
*bo
)
452 struct amdgpu_cs_context
*cs
= acs
->csc
;
453 struct amdgpu_cs_buffer
*buffer
;
455 int idx
= amdgpu_lookup_buffer(cs
, bo
);
461 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
465 /* New buffer, check if the backing array is large enough. */
466 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
468 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
469 struct amdgpu_cs_buffer
*new_buffers
;
471 new_buffers
= REALLOC(cs
->slab_buffers
,
472 cs
->max_slab_buffers
* sizeof(*new_buffers
),
473 new_max
* sizeof(*new_buffers
));
475 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
479 cs
->max_slab_buffers
= new_max
;
480 cs
->slab_buffers
= new_buffers
;
483 idx
= cs
->num_slab_buffers
;
484 buffer
= &cs
->slab_buffers
[idx
];
486 memset(buffer
, 0, sizeof(*buffer
));
487 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
488 buffer
->u
.slab
.real_idx
= real_idx
;
489 p_atomic_inc(&bo
->num_cs_references
);
490 cs
->num_slab_buffers
++;
492 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
493 cs
->buffer_indices_hashlist
[hash
] = idx
;
498 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
499 struct amdgpu_winsys_bo
*bo
)
501 struct amdgpu_cs_context
*cs
= acs
->csc
;
502 struct amdgpu_cs_buffer
*buffer
;
504 int idx
= amdgpu_lookup_buffer(cs
, bo
);
509 /* New buffer, check if the backing array is large enough. */
510 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
512 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
513 struct amdgpu_cs_buffer
*new_buffers
;
515 new_buffers
= REALLOC(cs
->sparse_buffers
,
516 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
517 new_max
* sizeof(*new_buffers
));
519 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
523 cs
->max_sparse_buffers
= new_max
;
524 cs
->sparse_buffers
= new_buffers
;
527 idx
= cs
->num_sparse_buffers
;
528 buffer
= &cs
->sparse_buffers
[idx
];
530 memset(buffer
, 0, sizeof(*buffer
));
531 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
532 p_atomic_inc(&bo
->num_cs_references
);
533 cs
->num_sparse_buffers
++;
535 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
536 cs
->buffer_indices_hashlist
[hash
] = idx
;
538 /* We delay adding the backing buffers until we really have to. However,
539 * we cannot delay accounting for memory use.
541 mtx_lock(&bo
->u
.sparse
.commit_lock
);
543 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
544 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
545 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
546 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
547 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
550 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
555 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
556 struct pb_buffer
*buf
,
557 enum radeon_bo_usage usage
,
558 enum radeon_bo_domain domains
,
559 enum radeon_bo_priority priority
)
561 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
562 * the buffer placement during command submission.
564 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
565 struct amdgpu_cs_context
*cs
= acs
->csc
;
566 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
567 struct amdgpu_cs_buffer
*buffer
;
570 /* Fast exit for no-op calls.
571 * This is very effective with suballocators and linear uploaders that
572 * are outside of the winsys.
574 if (bo
== cs
->last_added_bo
&&
575 (usage
& cs
->last_added_bo_usage
) == usage
&&
576 (1ull << priority
) & cs
->last_added_bo_priority_usage
)
577 return cs
->last_added_bo_index
;
581 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
585 buffer
= &cs
->slab_buffers
[index
];
586 buffer
->usage
|= usage
;
588 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
589 index
= buffer
->u
.slab
.real_idx
;
591 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
596 buffer
= &cs
->real_buffers
[index
];
598 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
602 buffer
= &cs
->sparse_buffers
[index
];
605 buffer
->u
.real
.priority_usage
|= 1ull << priority
;
606 buffer
->usage
|= usage
;
608 cs
->last_added_bo
= bo
;
609 cs
->last_added_bo_index
= index
;
610 cs
->last_added_bo_usage
= buffer
->usage
;
611 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
615 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
,
616 enum ring_type ring_type
)
618 struct pb_buffer
*pb
;
620 unsigned buffer_size
;
622 /* Always create a buffer that is at least as large as the maximum seen IB
623 * size, aligned to a power of two (and multiplied by 4 to reduce internal
624 * fragmentation if chaining is not available). Limit to 512k dwords, which
625 * is the largest power of two that fits into the size field of the
626 * INDIRECT_BUFFER packet.
628 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
629 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
631 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
633 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
635 switch (ib
->ib_type
) {
637 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
640 unreachable("unhandled IB type");
643 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
644 ws
->info
.gart_page_size
,
646 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
647 (ring_type
== RING_GFX
||
648 ring_type
== RING_COMPUTE
||
649 ring_type
== RING_DMA
?
650 RADEON_FLAG_GTT_WC
: 0));
654 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
656 pb_reference(&pb
, NULL
);
660 pb_reference(&ib
->big_ib_buffer
, pb
);
661 pb_reference(&pb
, NULL
);
663 ib
->ib_mapped
= mapped
;
664 ib
->used_ib_space
= 0;
669 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
673 /* Smaller submits means the GPU gets busy sooner and there is less
674 * waiting for buffers and fences. Proof:
675 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
679 unreachable("bad ib_type");
683 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
684 enum ib_type ib_type
)
686 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
687 /* Small IBs are better than big IBs, because the GPU goes idle quicker
688 * and there is less waiting for buffers and fences. Proof:
689 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
691 struct amdgpu_ib
*ib
= NULL
;
692 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
693 unsigned ib_size
= 0;
698 ib_size
= 4 * 1024 * 4;
701 unreachable("unhandled IB type");
704 if (!amdgpu_cs_has_chaining(cs
)) {
705 ib_size
= MAX2(ib_size
,
706 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
707 amdgpu_ib_max_submit_dwords(ib_type
)));
710 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
712 ib
->base
.prev_dw
= 0;
713 ib
->base
.num_prev
= 0;
714 ib
->base
.current
.cdw
= 0;
715 ib
->base
.current
.buf
= NULL
;
717 /* Allocate a new buffer for IBs if the current buffer is all used. */
718 if (!ib
->big_ib_buffer
||
719 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
720 if (!amdgpu_ib_new_buffer(aws
, ib
, cs
->ring_type
))
724 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
726 /* ib_bytes is in dwords and the conversion to bytes will be done before
728 ib
->ptr_ib_size
= &info
->ib_bytes
;
729 ib
->ptr_ib_size_inside_ib
= false;
731 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
732 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
734 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
736 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
737 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
741 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
743 if (ib
->ptr_ib_size_inside_ib
) {
744 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
745 S_3F2_CHAIN(1) | S_3F2_VALID(1);
747 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
751 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
753 amdgpu_set_ib_size(ib
);
754 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
755 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
758 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
759 enum ring_type ring_type
)
763 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
767 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
771 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
775 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_COMPUTE
;
779 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
784 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_GFX
;
788 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
789 cs
->last_added_bo
= NULL
;
793 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
797 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
798 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
799 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
801 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
802 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
803 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
805 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
806 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
807 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
809 for (i
= 0; i
< cs
->num_fence_dependencies
; i
++)
810 amdgpu_fence_reference(&cs
->fence_dependencies
[i
], NULL
);
812 cs
->num_real_buffers
= 0;
813 cs
->num_slab_buffers
= 0;
814 cs
->num_sparse_buffers
= 0;
815 cs
->num_fence_dependencies
= 0;
816 amdgpu_fence_reference(&cs
->fence
, NULL
);
818 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
819 cs
->last_added_bo
= NULL
;
822 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
824 amdgpu_cs_context_cleanup(cs
);
826 FREE(cs
->real_buffers
);
828 FREE(cs
->slab_buffers
);
829 FREE(cs
->sparse_buffers
);
830 FREE(cs
->fence_dependencies
);
834 static struct radeon_winsys_cs
*
835 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
836 enum ring_type ring_type
,
837 void (*flush
)(void *ctx
, unsigned flags
,
838 struct pipe_fence_handle
**fence
),
841 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
842 struct amdgpu_cs
*cs
;
844 cs
= CALLOC_STRUCT(amdgpu_cs
);
849 util_queue_fence_init(&cs
->flush_completed
);
852 cs
->flush_cs
= flush
;
853 cs
->flush_data
= flush_ctx
;
854 cs
->ring_type
= ring_type
;
856 struct amdgpu_cs_fence_info fence_info
;
857 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
858 fence_info
.offset
= cs
->ring_type
;
859 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
861 cs
->main
.ib_type
= IB_MAIN
;
863 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
868 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
869 amdgpu_destroy_cs_context(&cs
->csc1
);
874 /* Set the first submission context as current. */
878 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
879 amdgpu_destroy_cs_context(&cs
->csc2
);
880 amdgpu_destroy_cs_context(&cs
->csc1
);
885 p_atomic_inc(&ctx
->ws
->num_cs
);
886 return &cs
->main
.base
;
889 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
894 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
896 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
897 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
898 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
900 uint32_t *new_ptr_ib_size
;
902 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
904 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
907 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
909 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
912 if (!amdgpu_cs_has_chaining(cs
))
915 /* Allocate a new chunk */
916 if (rcs
->num_prev
>= rcs
->max_prev
) {
917 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
918 struct radeon_winsys_cs_chunk
*new_prev
;
920 new_prev
= REALLOC(rcs
->prev
,
921 sizeof(*new_prev
) * rcs
->max_prev
,
922 sizeof(*new_prev
) * new_max_prev
);
926 rcs
->prev
= new_prev
;
927 rcs
->max_prev
= new_max_prev
;
930 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
933 assert(ib
->used_ib_space
== 0);
934 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
936 /* This space was originally reserved. */
937 rcs
->current
.max_dw
+= 4;
938 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
940 /* Pad with NOPs and add INDIRECT_BUFFER packet */
941 while ((rcs
->current
.cdw
& 7) != 4)
942 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
944 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
945 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
946 radeon_emit(rcs
, va
);
947 radeon_emit(rcs
, va
>> 32);
948 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
950 assert((rcs
->current
.cdw
& 7) == 0);
951 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
953 amdgpu_set_ib_size(ib
);
954 ib
->ptr_ib_size
= new_ptr_ib_size
;
955 ib
->ptr_ib_size_inside_ib
= true;
957 /* Hook up the new chunk */
958 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
959 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
960 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
963 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
964 ib
->base
.current
.cdw
= 0;
966 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
967 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
969 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
970 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
975 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
976 struct radeon_bo_list_item
*list
)
978 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
982 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
983 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
984 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
985 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
988 return cs
->num_real_buffers
;
991 static unsigned add_fence_dependency_entry(struct amdgpu_cs_context
*cs
)
993 unsigned idx
= cs
->num_fence_dependencies
++;
995 if (idx
>= cs
->max_fence_dependencies
) {
997 const unsigned increment
= 8;
999 cs
->max_fence_dependencies
= idx
+ increment
;
1000 size
= cs
->max_fence_dependencies
* sizeof(cs
->fence_dependencies
[0]);
1001 cs
->fence_dependencies
= realloc(cs
->fence_dependencies
, size
);
1002 /* Clear the newly-allocated elements. */
1003 memset(cs
->fence_dependencies
+ idx
, 0,
1004 increment
* sizeof(cs
->fence_dependencies
[0]));
1009 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1010 struct amdgpu_fence
*fence
)
1012 struct amdgpu_cs_context
*cs
= acs
->csc
;
1014 if (!amdgpu_fence_is_syncobj(fence
) &&
1015 fence
->ctx
== acs
->ctx
&&
1016 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1017 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1018 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1021 return amdgpu_fence_wait((void *)fence
, 0, false);
1024 static void amdgpu_cs_add_fence_dependency(struct radeon_winsys_cs
*rws
,
1025 struct pipe_fence_handle
*pfence
)
1027 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1028 struct amdgpu_cs_context
*cs
= acs
->csc
;
1029 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1031 if (is_noop_fence_dependency(acs
, fence
))
1034 unsigned idx
= add_fence_dependency_entry(cs
);
1035 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1036 (struct pipe_fence_handle
*)fence
);
1039 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1040 struct amdgpu_cs_buffer
*buffer
)
1042 struct amdgpu_cs_context
*cs
= acs
->csc
;
1043 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1044 unsigned new_num_fences
= 0;
1046 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1047 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1049 if (is_noop_fence_dependency(acs
, bo_fence
))
1052 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1055 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1058 unsigned idx
= add_fence_dependency_entry(cs
);
1059 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1060 (struct pipe_fence_handle
*)bo_fence
);
1063 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1064 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1066 bo
->num_fences
= new_num_fences
;
1069 /* Add the given list of fences to the buffer's fence list.
1071 * Must be called with the winsys bo_fence_lock held.
1073 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1074 unsigned num_fences
,
1075 struct pipe_fence_handle
**fences
)
1077 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1078 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1079 struct pipe_fence_handle
**new_fences
=
1081 bo
->num_fences
* sizeof(*new_fences
),
1082 new_max_fences
* sizeof(*new_fences
));
1083 if (likely(new_fences
)) {
1084 bo
->fences
= new_fences
;
1085 bo
->max_fences
= new_max_fences
;
1089 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1090 if (!bo
->num_fences
)
1093 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1094 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1096 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1102 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1103 bo
->fences
[bo
->num_fences
] = NULL
;
1104 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1109 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1110 struct pipe_fence_handle
*fence
,
1111 unsigned num_buffers
,
1112 struct amdgpu_cs_buffer
*buffers
)
1114 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1115 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1116 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1118 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1119 p_atomic_inc(&bo
->num_active_ioctls
);
1120 amdgpu_add_fences(bo
, 1, &fence
);
1124 /* Since the kernel driver doesn't synchronize execution between different
1125 * rings automatically, we have to add fence dependencies manually.
1127 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1129 struct amdgpu_cs_context
*cs
= acs
->csc
;
1131 cs
->num_fence_dependencies
= 0;
1133 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1134 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1135 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1138 /* Add backing of sparse buffers to the buffer list.
1140 * This is done late, during submission, to keep the buffer list short before
1141 * submit, and to avoid managing fences for the backing buffers.
1143 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1145 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1146 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1147 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1149 mtx_lock(&bo
->u
.sparse
.commit_lock
);
1151 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1152 /* We can directly add the buffer here, because we know that each
1153 * backing buffer occurs only once.
1155 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1157 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1158 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1162 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1163 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1164 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1167 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1173 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1175 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1176 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1177 struct amdgpu_cs_context
*cs
= acs
->cst
;
1179 amdgpu_bo_list_handle bo_list
= NULL
;
1180 uint64_t seq_no
= 0;
1181 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1183 /* Create the buffer list.
1184 * Use a buffer list containing all allocated buffers if requested.
1186 if (ws
->debug_all_bos
) {
1187 struct amdgpu_winsys_bo
*bo
;
1188 amdgpu_bo_handle
*handles
;
1191 mtx_lock(&ws
->global_bo_list_lock
);
1193 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
1195 mtx_unlock(&ws
->global_bo_list_lock
);
1196 amdgpu_cs_context_cleanup(cs
);
1197 cs
->error_code
= -ENOMEM
;
1201 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1202 assert(num
< ws
->num_buffers
);
1203 handles
[num
++] = bo
->bo
;
1206 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1207 handles
, NULL
, &bo_list
);
1209 mtx_unlock(&ws
->global_bo_list_lock
);
1211 unsigned num_handles
;
1213 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1218 if (cs
->max_real_submit
< cs
->num_real_buffers
) {
1222 cs
->handles
= MALLOC(sizeof(*cs
->handles
) * cs
->num_real_buffers
);
1223 cs
->flags
= MALLOC(sizeof(*cs
->flags
) * cs
->num_real_buffers
);
1225 if (!cs
->handles
|| !cs
->flags
) {
1226 cs
->max_real_submit
= 0;
1233 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1234 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1236 if (buffer
->bo
->is_local
)
1239 assert(buffer
->u
.real
.priority_usage
!= 0);
1241 cs
->handles
[num_handles
] = buffer
->bo
->bo
;
1242 cs
->flags
[num_handles
] = (util_last_bit64(buffer
->u
.real
.priority_usage
) - 1) / 4;
1246 if (acs
->ring_type
== RING_GFX
)
1247 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1250 r
= amdgpu_bo_list_create(ws
->dev
, num_handles
,
1251 cs
->handles
, cs
->flags
, &bo_list
);
1259 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1260 amdgpu_fence_signalled(cs
->fence
);
1265 if (acs
->ctx
->num_rejected_cs
) {
1268 struct drm_amdgpu_cs_chunk chunks
[4];
1269 unsigned num_chunks
= 0;
1271 /* Convert from dwords to bytes. */
1272 cs
->ib
[IB_MAIN
].ib_bytes
*= 4;
1275 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1276 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1277 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1281 if (has_user_fence
) {
1282 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1283 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1284 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1289 unsigned num_dependencies
= cs
->num_fence_dependencies
;
1290 unsigned num_syncobj_dependencies
= 0;
1292 if (num_dependencies
) {
1293 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1294 alloca(num_dependencies
* sizeof(*dep_chunk
));
1297 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1298 struct amdgpu_fence
*fence
=
1299 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1301 if (amdgpu_fence_is_syncobj(fence
)) {
1302 num_syncobj_dependencies
++;
1306 assert(!fence
->submission_in_progress
);
1307 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[num
++]);
1310 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1311 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num
;
1312 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1316 /* Syncobj dependencies. */
1317 if (num_syncobj_dependencies
) {
1318 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1319 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1322 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1323 struct amdgpu_fence
*fence
=
1324 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1326 if (!amdgpu_fence_is_syncobj(fence
))
1329 assert(!fence
->submission_in_progress
);
1330 sem_chunk
[num
++].handle
= fence
->syncobj
;
1333 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1334 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num
;
1335 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1339 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1341 r
= amdgpu_cs_submit_raw(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1342 num_chunks
, chunks
, &seq_no
);
1348 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1349 else if (r
== -ECANCELED
)
1350 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1352 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1353 "see dmesg for more information (%i).\n", r
);
1355 amdgpu_fence_signalled(cs
->fence
);
1357 acs
->ctx
->num_rejected_cs
++;
1358 ws
->num_total_rejected_cs
++;
1361 uint64_t *user_fence
= NULL
;
1364 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1365 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1370 amdgpu_bo_list_destroy(bo_list
);
1373 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1374 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1375 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1376 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1377 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1378 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1380 amdgpu_cs_context_cleanup(cs
);
1383 /* Make sure the previous submission is completed. */
1384 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
1386 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1388 /* Wait for any pending ioctl of this CS to complete. */
1389 util_queue_fence_wait(&cs
->flush_completed
);
1392 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
1394 struct pipe_fence_handle
**fence
)
1396 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1397 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1400 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1402 switch (cs
->ring_type
) {
1404 /* pad DMA ring to 8 DWs */
1405 if (ws
->info
.chip_class
<= SI
) {
1406 while (rcs
->current
.cdw
& 7)
1407 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1409 while (rcs
->current
.cdw
& 7)
1410 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1414 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1415 if (ws
->info
.gfx_ib_pad_with_type2
) {
1416 while (rcs
->current
.cdw
& 7)
1417 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1419 while (rcs
->current
.cdw
& 7)
1420 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1422 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1425 while (rcs
->current
.cdw
& 15)
1426 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1429 while (rcs
->current
.cdw
& 15)
1430 radeon_emit(rcs
, 0x81ff); /* nop packet */
1436 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1437 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1440 /* If the CS is not empty or overflowed.... */
1441 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1442 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1443 !debug_get_option_noop())) {
1444 struct amdgpu_cs_context
*cur
= cs
->csc
;
1447 amdgpu_ib_finalize(&cs
->main
);
1449 /* Create a fence. */
1450 amdgpu_fence_reference(&cur
->fence
, NULL
);
1451 if (cs
->next_fence
) {
1452 /* just move the reference */
1453 cur
->fence
= cs
->next_fence
;
1454 cs
->next_fence
= NULL
;
1456 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1457 cur
->ib
[IB_MAIN
].ip_type
,
1458 cur
->ib
[IB_MAIN
].ip_instance
,
1459 cur
->ib
[IB_MAIN
].ring
);
1462 amdgpu_fence_reference(fence
, cur
->fence
);
1464 amdgpu_cs_sync_flush(rcs
);
1468 * This fence must be held until the submission is queued to ensure
1469 * that the order of fence dependency updates matches the order of
1472 mtx_lock(&ws
->bo_fence_lock
);
1473 amdgpu_add_fence_dependencies_bo_lists(cs
);
1475 /* Swap command streams. "cst" is going to be submitted. */
1480 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1481 amdgpu_cs_submit_ib
, NULL
);
1482 /* The submission has been queued, unlock the fence now. */
1483 mtx_unlock(&ws
->bo_fence_lock
);
1485 if (!(flags
& RADEON_FLUSH_ASYNC
)) {
1486 amdgpu_cs_sync_flush(rcs
);
1487 error_code
= cur
->error_code
;
1490 amdgpu_cs_context_cleanup(cs
->csc
);
1493 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1495 cs
->main
.base
.used_gart
= 0;
1496 cs
->main
.base
.used_vram
= 0;
1498 if (cs
->ring_type
== RING_GFX
)
1500 else if (cs
->ring_type
== RING_DMA
)
1506 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1508 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1510 amdgpu_cs_sync_flush(rcs
);
1511 util_queue_fence_destroy(&cs
->flush_completed
);
1512 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1513 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1514 FREE(cs
->main
.base
.prev
);
1515 amdgpu_destroy_cs_context(&cs
->csc1
);
1516 amdgpu_destroy_cs_context(&cs
->csc2
);
1517 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1521 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1522 struct pb_buffer
*_buf
,
1523 enum radeon_bo_usage usage
)
1525 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1526 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1528 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1531 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1533 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1534 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1535 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1536 ws
->base
.cs_create
= amdgpu_cs_create
;
1537 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1538 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1539 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1540 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1541 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1542 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1543 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1544 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1545 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1546 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1547 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1548 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1549 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1550 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;