2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
34 #include "amd/common/sid.h"
36 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
38 #ifndef AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
39 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
42 #ifndef AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
43 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
48 static struct pipe_fence_handle
*
49 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
50 unsigned ip_instance
, unsigned ring
)
52 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
54 fence
->reference
.count
= 1;
57 fence
->fence
.context
= ctx
->ctx
;
58 fence
->fence
.ip_type
= ip_type
;
59 fence
->fence
.ip_instance
= ip_instance
;
60 fence
->fence
.ring
= ring
;
61 util_queue_fence_init(&fence
->submitted
);
62 util_queue_fence_reset(&fence
->submitted
);
63 p_atomic_inc(&ctx
->refcount
);
64 return (struct pipe_fence_handle
*)fence
;
67 static struct pipe_fence_handle
*
68 amdgpu_fence_import_syncobj(struct radeon_winsys
*rws
, int fd
)
70 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
71 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
77 pipe_reference_init(&fence
->reference
, 1);
80 r
= amdgpu_cs_import_syncobj(ws
->dev
, fd
, &fence
->syncobj
);
86 util_queue_fence_init(&fence
->submitted
);
88 assert(amdgpu_fence_is_syncobj(fence
));
89 return (struct pipe_fence_handle
*)fence
;
92 static struct pipe_fence_handle
*
93 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
95 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
96 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
101 pipe_reference_init(&fence
->reference
, 1);
103 /* fence->ctx == NULL means that the fence is syncobj-based. */
105 /* Convert sync_file into syncobj. */
106 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
112 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
114 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
119 util_queue_fence_init(&fence
->submitted
);
121 return (struct pipe_fence_handle
*)fence
;
124 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
125 struct pipe_fence_handle
*pfence
)
127 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
128 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
130 if (amdgpu_fence_is_syncobj(fence
)) {
133 /* Convert syncobj into sync_file. */
134 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
138 util_queue_fence_wait(&fence
->submitted
);
140 /* Convert the amdgpu fence into a fence FD. */
142 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
143 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
150 static int amdgpu_export_signalled_sync_file(struct radeon_winsys
*rws
)
152 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
156 int r
= amdgpu_cs_create_syncobj2(ws
->dev
, DRM_SYNCOBJ_CREATE_SIGNALED
,
162 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, &fd
);
167 amdgpu_cs_destroy_syncobj(ws
->dev
, syncobj
);
171 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
173 uint64_t *user_fence_cpu_address
)
175 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
177 afence
->fence
.fence
= seq_no
;
178 afence
->user_fence_cpu_address
= user_fence_cpu_address
;
179 util_queue_fence_signal(&afence
->submitted
);
182 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
184 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
186 afence
->signalled
= true;
187 util_queue_fence_signal(&afence
->submitted
);
190 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
193 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
196 uint64_t *user_fence_cpu
;
199 if (afence
->signalled
)
202 /* Handle syncobjs. */
203 if (amdgpu_fence_is_syncobj(afence
)) {
204 /* Absolute timeouts are only be used by BO fences, which aren't
205 * backed by syncobjs.
209 if (amdgpu_cs_syncobj_wait(afence
->ws
->dev
, &afence
->syncobj
, 1,
213 afence
->signalled
= true;
218 abs_timeout
= timeout
;
220 abs_timeout
= os_time_get_absolute_timeout(timeout
);
222 /* The fence might not have a number assigned if its IB is being
223 * submitted in the other thread right now. Wait until the submission
225 if (!util_queue_fence_wait_timeout(&afence
->submitted
, abs_timeout
))
228 user_fence_cpu
= afence
->user_fence_cpu_address
;
229 if (user_fence_cpu
) {
230 if (*user_fence_cpu
>= afence
->fence
.fence
) {
231 afence
->signalled
= true;
235 /* No timeout, just query: no need for the ioctl. */
236 if (!absolute
&& !timeout
)
240 /* Now use the libdrm query. */
241 r
= amdgpu_cs_query_fence_status(&afence
->fence
,
243 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
246 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
251 /* This variable can only transition from false to true, so it doesn't
252 * matter if threads race for it. */
253 afence
->signalled
= true;
259 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
260 struct pipe_fence_handle
*fence
,
263 return amdgpu_fence_wait(fence
, timeout
, false);
266 static struct pipe_fence_handle
*
267 amdgpu_cs_get_next_fence(struct radeon_cmdbuf
*rcs
)
269 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
270 struct pipe_fence_handle
*fence
= NULL
;
272 if (debug_get_option_noop())
275 if (cs
->next_fence
) {
276 amdgpu_fence_reference(&fence
, cs
->next_fence
);
280 fence
= amdgpu_fence_create(cs
->ctx
,
281 cs
->csc
->ib
[IB_MAIN
].ip_type
,
282 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
283 cs
->csc
->ib
[IB_MAIN
].ring
);
287 amdgpu_fence_reference(&cs
->next_fence
, fence
);
293 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
295 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
297 struct amdgpu_bo_alloc_request alloc_buffer
= {};
298 amdgpu_bo_handle buf_handle
;
303 ctx
->ws
= amdgpu_winsys(ws
);
305 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
307 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
309 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
313 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
314 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
315 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
317 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
319 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
320 goto error_user_fence_alloc
;
323 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
325 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
326 goto error_user_fence_map
;
329 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
330 ctx
->user_fence_bo
= buf_handle
;
332 return (struct radeon_winsys_ctx
*)ctx
;
334 error_user_fence_map
:
335 amdgpu_bo_free(buf_handle
);
336 error_user_fence_alloc
:
337 amdgpu_cs_ctx_free(ctx
->ctx
);
343 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
345 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
348 static enum pipe_reset_status
349 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
351 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
352 uint32_t result
, hangs
;
355 /* Return a failure due to a GPU hang. */
356 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
358 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
359 return PIPE_NO_RESET
;
363 case AMDGPU_CTX_GUILTY_RESET
:
364 return PIPE_GUILTY_CONTEXT_RESET
;
365 case AMDGPU_CTX_INNOCENT_RESET
:
366 return PIPE_INNOCENT_CONTEXT_RESET
;
367 case AMDGPU_CTX_UNKNOWN_RESET
:
368 return PIPE_UNKNOWN_CONTEXT_RESET
;
369 case AMDGPU_CTX_NO_RESET
:
371 /* Return a failure due to a rejected command submission. */
372 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
373 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
374 PIPE_INNOCENT_CONTEXT_RESET
;
376 return PIPE_NO_RESET
;
380 /* COMMAND SUBMISSION */
382 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
384 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
385 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
386 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD_ENC
&&
387 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
&&
388 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_ENC
&&
389 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_JPEG
;
392 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
394 return cs
->ctx
->ws
->info
.chip_class
>= GFX7
&&
395 (cs
->ring_type
== RING_GFX
|| cs
->ring_type
== RING_COMPUTE
);
398 static unsigned amdgpu_cs_epilog_dws(struct amdgpu_cs
*cs
)
400 if (amdgpu_cs_has_chaining(cs
))
401 return 4; /* for chaining */
406 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
408 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
409 int i
= cs
->buffer_indices_hashlist
[hash
];
410 struct amdgpu_cs_buffer
*buffers
;
414 buffers
= cs
->real_buffers
;
415 num_buffers
= cs
->num_real_buffers
;
416 } else if (!bo
->sparse
) {
417 buffers
= cs
->slab_buffers
;
418 num_buffers
= cs
->num_slab_buffers
;
420 buffers
= cs
->sparse_buffers
;
421 num_buffers
= cs
->num_sparse_buffers
;
424 /* not found or found */
425 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
428 /* Hash collision, look for the BO in the list of buffers linearly. */
429 for (i
= num_buffers
- 1; i
>= 0; i
--) {
430 if (buffers
[i
].bo
== bo
) {
431 /* Put this buffer in the hash list.
432 * This will prevent additional hash collisions if there are
433 * several consecutive lookup_buffer calls for the same buffer.
435 * Example: Assuming buffers A,B,C collide in the hash list,
436 * the following sequence of buffers:
437 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
438 * will collide here: ^ and here: ^,
439 * meaning that we should get very few collisions in the end. */
440 cs
->buffer_indices_hashlist
[hash
] = i
;
448 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
450 struct amdgpu_cs_buffer
*buffer
;
453 /* New buffer, check if the backing array is large enough. */
454 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
456 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
457 struct amdgpu_cs_buffer
*new_buffers
;
459 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
462 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
467 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
469 FREE(cs
->real_buffers
);
471 cs
->max_real_buffers
= new_max
;
472 cs
->real_buffers
= new_buffers
;
475 idx
= cs
->num_real_buffers
;
476 buffer
= &cs
->real_buffers
[idx
];
478 memset(buffer
, 0, sizeof(*buffer
));
479 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
480 p_atomic_inc(&bo
->num_cs_references
);
481 cs
->num_real_buffers
++;
487 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
489 struct amdgpu_cs_context
*cs
= acs
->csc
;
491 int idx
= amdgpu_lookup_buffer(cs
, bo
);
496 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
498 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
499 cs
->buffer_indices_hashlist
[hash
] = idx
;
501 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
502 acs
->main
.base
.used_vram
+= bo
->base
.size
;
503 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
504 acs
->main
.base
.used_gart
+= bo
->base
.size
;
509 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
510 struct amdgpu_winsys_bo
*bo
)
512 struct amdgpu_cs_context
*cs
= acs
->csc
;
513 struct amdgpu_cs_buffer
*buffer
;
515 int idx
= amdgpu_lookup_buffer(cs
, bo
);
521 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
525 /* New buffer, check if the backing array is large enough. */
526 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
528 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
529 struct amdgpu_cs_buffer
*new_buffers
;
531 new_buffers
= REALLOC(cs
->slab_buffers
,
532 cs
->max_slab_buffers
* sizeof(*new_buffers
),
533 new_max
* sizeof(*new_buffers
));
535 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
539 cs
->max_slab_buffers
= new_max
;
540 cs
->slab_buffers
= new_buffers
;
543 idx
= cs
->num_slab_buffers
;
544 buffer
= &cs
->slab_buffers
[idx
];
546 memset(buffer
, 0, sizeof(*buffer
));
547 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
548 buffer
->u
.slab
.real_idx
= real_idx
;
549 p_atomic_inc(&bo
->num_cs_references
);
550 cs
->num_slab_buffers
++;
552 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
553 cs
->buffer_indices_hashlist
[hash
] = idx
;
558 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
559 struct amdgpu_winsys_bo
*bo
)
561 struct amdgpu_cs_context
*cs
= acs
->csc
;
562 struct amdgpu_cs_buffer
*buffer
;
564 int idx
= amdgpu_lookup_buffer(cs
, bo
);
569 /* New buffer, check if the backing array is large enough. */
570 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
572 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
573 struct amdgpu_cs_buffer
*new_buffers
;
575 new_buffers
= REALLOC(cs
->sparse_buffers
,
576 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
577 new_max
* sizeof(*new_buffers
));
579 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
583 cs
->max_sparse_buffers
= new_max
;
584 cs
->sparse_buffers
= new_buffers
;
587 idx
= cs
->num_sparse_buffers
;
588 buffer
= &cs
->sparse_buffers
[idx
];
590 memset(buffer
, 0, sizeof(*buffer
));
591 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
592 p_atomic_inc(&bo
->num_cs_references
);
593 cs
->num_sparse_buffers
++;
595 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
596 cs
->buffer_indices_hashlist
[hash
] = idx
;
598 /* We delay adding the backing buffers until we really have to. However,
599 * we cannot delay accounting for memory use.
601 simple_mtx_lock(&bo
->lock
);
603 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
604 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
605 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
606 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
607 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
610 simple_mtx_unlock(&bo
->lock
);
615 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf
*rcs
,
616 struct pb_buffer
*buf
,
617 enum radeon_bo_usage usage
,
618 enum radeon_bo_domain domains
,
619 enum radeon_bo_priority priority
)
621 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
622 * the buffer placement during command submission.
624 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
625 struct amdgpu_cs_context
*cs
= acs
->csc
;
626 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
627 struct amdgpu_cs_buffer
*buffer
;
630 /* Fast exit for no-op calls.
631 * This is very effective with suballocators and linear uploaders that
632 * are outside of the winsys.
634 if (bo
== cs
->last_added_bo
&&
635 (usage
& cs
->last_added_bo_usage
) == usage
&&
636 (1u << priority
) & cs
->last_added_bo_priority_usage
)
637 return cs
->last_added_bo_index
;
641 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
645 buffer
= &cs
->slab_buffers
[index
];
646 buffer
->usage
|= usage
;
648 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
649 index
= buffer
->u
.slab
.real_idx
;
651 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
656 buffer
= &cs
->real_buffers
[index
];
658 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
662 buffer
= &cs
->sparse_buffers
[index
];
665 buffer
->u
.real
.priority_usage
|= 1u << priority
;
666 buffer
->usage
|= usage
;
668 cs
->last_added_bo
= bo
;
669 cs
->last_added_bo_index
= index
;
670 cs
->last_added_bo_usage
= buffer
->usage
;
671 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
675 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
,
676 enum ring_type ring_type
)
678 struct pb_buffer
*pb
;
680 unsigned buffer_size
;
682 /* Always create a buffer that is at least as large as the maximum seen IB
683 * size, aligned to a power of two (and multiplied by 4 to reduce internal
684 * fragmentation if chaining is not available). Limit to 512k dwords, which
685 * is the largest power of two that fits into the size field of the
686 * INDIRECT_BUFFER packet.
688 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
689 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
691 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
693 const unsigned min_size
= MAX2(ib
->max_check_space_size
, 8 * 1024 * 4);
694 const unsigned max_size
= 512 * 1024 * 4;
696 buffer_size
= MIN2(buffer_size
, max_size
);
697 buffer_size
= MAX2(buffer_size
, min_size
); /* min_size is more important */
699 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
700 ws
->info
.gart_page_size
,
702 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
703 (ring_type
== RING_GFX
||
704 ring_type
== RING_COMPUTE
||
705 ring_type
== RING_DMA
?
706 RADEON_FLAG_32BIT
| RADEON_FLAG_GTT_WC
: 0));
710 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
712 pb_reference(&pb
, NULL
);
716 pb_reference(&ib
->big_ib_buffer
, pb
);
717 pb_reference(&pb
, NULL
);
719 ib
->ib_mapped
= mapped
;
720 ib
->used_ib_space
= 0;
725 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
727 /* The maximum IB size including all chained IBs. */
730 /* Smaller submits means the GPU gets busy sooner and there is less
731 * waiting for buffers and fences. Proof:
732 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
735 case IB_PARALLEL_COMPUTE
:
736 /* Always chain this IB. */
739 unreachable("bad ib_type");
743 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
744 enum ib_type ib_type
)
746 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
747 /* Small IBs are better than big IBs, because the GPU goes idle quicker
748 * and there is less waiting for buffers and fences. Proof:
749 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
751 struct amdgpu_ib
*ib
= NULL
;
752 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
753 /* This is the minimum size of a contiguous IB. */
754 unsigned ib_size
= 4 * 1024 * 4;
757 case IB_PARALLEL_COMPUTE
:
758 ib
= &cs
->compute_ib
;
764 unreachable("unhandled IB type");
767 /* Always allocate at least the size of the biggest cs_check_space call,
768 * because precisely the last call might have requested this size.
770 ib_size
= MAX2(ib_size
, ib
->max_check_space_size
);
772 if (!amdgpu_cs_has_chaining(cs
)) {
773 ib_size
= MAX2(ib_size
,
774 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
775 amdgpu_ib_max_submit_dwords(ib_type
)));
778 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
780 ib
->base
.prev_dw
= 0;
781 ib
->base
.num_prev
= 0;
782 ib
->base
.current
.cdw
= 0;
783 ib
->base
.current
.buf
= NULL
;
785 /* Allocate a new buffer for IBs if the current buffer is all used. */
786 if (!ib
->big_ib_buffer
||
787 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
788 if (!amdgpu_ib_new_buffer(aws
, ib
, cs
->ring_type
))
792 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
794 /* ib_bytes is in dwords and the conversion to bytes will be done before
796 ib
->ptr_ib_size
= &info
->ib_bytes
;
797 ib
->ptr_ib_size_inside_ib
= false;
799 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
800 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
802 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
804 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
805 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
);
806 assert(ib
->base
.current
.max_dw
>= ib
->max_check_space_size
/ 4);
807 ib
->base
.gpu_address
= info
->va_start
;
811 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
813 if (ib
->ptr_ib_size_inside_ib
) {
814 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
815 S_3F2_CHAIN(1) | S_3F2_VALID(1);
817 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
821 static void amdgpu_ib_finalize(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
823 amdgpu_set_ib_size(ib
);
824 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
825 ib
->used_ib_space
= align(ib
->used_ib_space
, ws
->info
.ib_start_alignment
);
826 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
829 static bool amdgpu_init_cs_context(struct amdgpu_winsys
*ws
,
830 struct amdgpu_cs_context
*cs
,
831 enum ring_type ring_type
)
835 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
839 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
843 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD_ENC
;
847 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
851 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
855 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_ENC
;
859 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_JPEG
;
864 cs
->ib
[IB_MAIN
].ip_type
= ring_type
== RING_GFX
? AMDGPU_HW_IP_GFX
:
865 AMDGPU_HW_IP_COMPUTE
;
867 /* The kernel shouldn't invalidate L2 and vL1. The proper place for cache
868 * invalidation is the beginning of IBs (the previous commit does that),
869 * because completion of an IB doesn't care about the state of GPU caches,
870 * but the beginning of an IB does. Draw calls from multiple IBs can be
871 * executed in parallel, so draw calls from the current IB can finish after
872 * the next IB starts drawing, and so the cache flush at the end of IB
875 if (ws
->info
.drm_minor
>= 26)
876 cs
->ib
[IB_MAIN
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
883 cs
->ib
[IB_PARALLEL_COMPUTE
].ip_type
= AMDGPU_HW_IP_COMPUTE
;
884 cs
->ib
[IB_PARALLEL_COMPUTE
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
886 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
887 cs
->last_added_bo
= NULL
;
891 static void cleanup_fence_list(struct amdgpu_fence_list
*fences
)
893 for (unsigned i
= 0; i
< fences
->num
; i
++)
894 amdgpu_fence_reference(&fences
->list
[i
], NULL
);
898 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
902 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
903 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
904 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
906 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
907 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
908 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
910 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
911 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
912 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
914 cleanup_fence_list(&cs
->fence_dependencies
);
915 cleanup_fence_list(&cs
->syncobj_dependencies
);
916 cleanup_fence_list(&cs
->syncobj_to_signal
);
917 cleanup_fence_list(&cs
->compute_fence_dependencies
);
918 cleanup_fence_list(&cs
->compute_start_fence_dependencies
);
920 cs
->num_real_buffers
= 0;
921 cs
->num_slab_buffers
= 0;
922 cs
->num_sparse_buffers
= 0;
923 amdgpu_fence_reference(&cs
->fence
, NULL
);
925 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
926 cs
->last_added_bo
= NULL
;
929 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
931 amdgpu_cs_context_cleanup(cs
);
932 FREE(cs
->real_buffers
);
933 FREE(cs
->slab_buffers
);
934 FREE(cs
->sparse_buffers
);
935 FREE(cs
->fence_dependencies
.list
);
936 FREE(cs
->syncobj_dependencies
.list
);
937 FREE(cs
->syncobj_to_signal
.list
);
938 FREE(cs
->compute_fence_dependencies
.list
);
939 FREE(cs
->compute_start_fence_dependencies
.list
);
943 static struct radeon_cmdbuf
*
944 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
945 enum ring_type ring_type
,
946 void (*flush
)(void *ctx
, unsigned flags
,
947 struct pipe_fence_handle
**fence
),
949 bool stop_exec_on_failure
)
951 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
952 struct amdgpu_cs
*cs
;
954 cs
= CALLOC_STRUCT(amdgpu_cs
);
959 util_queue_fence_init(&cs
->flush_completed
);
962 cs
->flush_cs
= flush
;
963 cs
->flush_data
= flush_ctx
;
964 cs
->ring_type
= ring_type
;
965 cs
->stop_exec_on_failure
= stop_exec_on_failure
;
967 struct amdgpu_cs_fence_info fence_info
;
968 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
969 fence_info
.offset
= cs
->ring_type
;
970 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
972 cs
->main
.ib_type
= IB_MAIN
;
973 cs
->compute_ib
.ib_type
= IB_PARALLEL_COMPUTE
;
975 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc1
, ring_type
)) {
980 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc2
, ring_type
)) {
981 amdgpu_destroy_cs_context(&cs
->csc1
);
986 /* Set the first submission context as current. */
990 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
991 amdgpu_destroy_cs_context(&cs
->csc2
);
992 amdgpu_destroy_cs_context(&cs
->csc1
);
997 p_atomic_inc(&ctx
->ws
->num_cs
);
998 return &cs
->main
.base
;
1001 static struct radeon_cmdbuf
*
1002 amdgpu_cs_add_parallel_compute_ib(struct radeon_cmdbuf
*ib
,
1003 bool uses_gds_ordered_append
)
1005 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)ib
;
1006 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1008 if (cs
->ring_type
!= RING_GFX
)
1011 /* only one secondary IB can be added */
1012 if (cs
->compute_ib
.ib_mapped
)
1015 /* Allocate the compute IB. */
1016 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_PARALLEL_COMPUTE
))
1019 if (uses_gds_ordered_append
) {
1020 cs
->csc1
.ib
[IB_PARALLEL_COMPUTE
].flags
|=
1021 AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
;
1022 cs
->csc2
.ib
[IB_PARALLEL_COMPUTE
].flags
|=
1023 AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
;
1025 return &cs
->compute_ib
.base
;
1028 static bool amdgpu_cs_validate(struct radeon_cmdbuf
*rcs
)
1033 static bool amdgpu_cs_check_space(struct radeon_cmdbuf
*rcs
, unsigned dw
,
1034 bool force_chaining
)
1036 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
1037 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
1038 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
1039 unsigned cs_epilog_dw
= amdgpu_cs_epilog_dws(cs
);
1040 unsigned need_byte_size
= (dw
+ cs_epilog_dw
) * 4;
1042 uint32_t *new_ptr_ib_size
;
1044 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1046 /* 125% of the size for IB epilog. */
1047 unsigned safe_byte_size
= need_byte_size
+ need_byte_size
/ 4;
1048 ib
->max_check_space_size
= MAX2(ib
->max_check_space_size
,
1051 /* If force_chaining is true, we can't return. We have to chain. */
1052 if (!force_chaining
) {
1053 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
1056 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
1058 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
1062 if (!amdgpu_cs_has_chaining(cs
)) {
1063 assert(!force_chaining
);
1067 /* Allocate a new chunk */
1068 if (rcs
->num_prev
>= rcs
->max_prev
) {
1069 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
1070 struct radeon_cmdbuf_chunk
*new_prev
;
1072 new_prev
= REALLOC(rcs
->prev
,
1073 sizeof(*new_prev
) * rcs
->max_prev
,
1074 sizeof(*new_prev
) * new_max_prev
);
1078 rcs
->prev
= new_prev
;
1079 rcs
->max_prev
= new_max_prev
;
1082 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
1085 assert(ib
->used_ib_space
== 0);
1086 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
1088 /* This space was originally reserved. */
1089 rcs
->current
.max_dw
+= cs_epilog_dw
;
1091 /* Pad with NOPs and add INDIRECT_BUFFER packet */
1092 while ((rcs
->current
.cdw
& 7) != 4)
1093 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1095 radeon_emit(rcs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
1096 radeon_emit(rcs
, va
);
1097 radeon_emit(rcs
, va
>> 32);
1098 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
1100 assert((rcs
->current
.cdw
& 7) == 0);
1101 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1103 amdgpu_set_ib_size(ib
);
1104 ib
->ptr_ib_size
= new_ptr_ib_size
;
1105 ib
->ptr_ib_size_inside_ib
= true;
1107 /* Hook up the new chunk */
1108 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
1109 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
1110 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
1113 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
1114 ib
->base
.current
.cdw
= 0;
1116 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
1117 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - cs_epilog_dw
;
1118 assert(ib
->base
.current
.max_dw
>= ib
->max_check_space_size
/ 4);
1119 ib
->base
.gpu_address
= va
;
1121 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
1122 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
1127 static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf
*rcs
,
1128 struct radeon_bo_list_item
*list
)
1130 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
1134 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
1135 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
1136 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
1137 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
1140 return cs
->num_real_buffers
;
1143 static void add_fence_to_list(struct amdgpu_fence_list
*fences
,
1144 struct amdgpu_fence
*fence
)
1146 unsigned idx
= fences
->num
++;
1148 if (idx
>= fences
->max
) {
1150 const unsigned increment
= 8;
1152 fences
->max
= idx
+ increment
;
1153 size
= fences
->max
* sizeof(fences
->list
[0]);
1154 fences
->list
= realloc(fences
->list
, size
);
1155 /* Clear the newly-allocated elements. */
1156 memset(fences
->list
+ idx
, 0,
1157 increment
* sizeof(fences
->list
[0]));
1159 amdgpu_fence_reference(&fences
->list
[idx
], (struct pipe_fence_handle
*)fence
);
1162 /* TODO: recognizing dependencies as no-ops doesn't take the parallel
1163 * compute IB into account. The compute IB won't wait for these.
1164 * Also, the scheduler can execute compute and SDMA IBs on any rings.
1165 * Should we always insert dependencies?
1167 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1168 struct amdgpu_fence
*fence
)
1170 struct amdgpu_cs_context
*cs
= acs
->csc
;
1172 if (!amdgpu_fence_is_syncobj(fence
) &&
1173 fence
->ctx
== acs
->ctx
&&
1174 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1175 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1176 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1179 return amdgpu_fence_wait((void *)fence
, 0, false);
1182 static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf
*rws
,
1183 struct pipe_fence_handle
*pfence
,
1184 unsigned dependency_flags
)
1186 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1187 struct amdgpu_cs_context
*cs
= acs
->csc
;
1188 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1190 util_queue_fence_wait(&fence
->submitted
);
1192 if (dependency_flags
& RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY
) {
1193 /* Syncobjs are not needed here. */
1194 assert(!amdgpu_fence_is_syncobj(fence
));
1196 if (acs
->ctx
->ws
->info
.has_scheduled_fence_dependency
&&
1197 dependency_flags
& RADEON_DEPENDENCY_START_FENCE
)
1198 add_fence_to_list(&cs
->compute_start_fence_dependencies
, fence
);
1200 add_fence_to_list(&cs
->compute_fence_dependencies
, fence
);
1204 /* Start fences are not needed here. */
1205 assert(!(dependency_flags
& RADEON_DEPENDENCY_START_FENCE
));
1207 if (is_noop_fence_dependency(acs
, fence
))
1210 if (amdgpu_fence_is_syncobj(fence
))
1211 add_fence_to_list(&cs
->syncobj_dependencies
, fence
);
1213 add_fence_to_list(&cs
->fence_dependencies
, fence
);
1216 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1217 struct amdgpu_cs_buffer
*buffer
)
1219 struct amdgpu_cs_context
*cs
= acs
->csc
;
1220 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1221 unsigned new_num_fences
= 0;
1223 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1224 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1226 if (is_noop_fence_dependency(acs
, bo_fence
))
1229 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1232 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1235 add_fence_to_list(&cs
->fence_dependencies
, bo_fence
);
1238 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1239 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1241 bo
->num_fences
= new_num_fences
;
1244 /* Add the given list of fences to the buffer's fence list.
1246 * Must be called with the winsys bo_fence_lock held.
1248 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1249 unsigned num_fences
,
1250 struct pipe_fence_handle
**fences
)
1252 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1253 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1254 struct pipe_fence_handle
**new_fences
=
1256 bo
->num_fences
* sizeof(*new_fences
),
1257 new_max_fences
* sizeof(*new_fences
));
1258 if (likely(new_fences
)) {
1259 bo
->fences
= new_fences
;
1260 bo
->max_fences
= new_max_fences
;
1264 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1265 if (!bo
->num_fences
)
1268 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1269 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1271 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1277 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1278 bo
->fences
[bo
->num_fences
] = NULL
;
1279 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1284 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1285 struct pipe_fence_handle
*fence
,
1286 unsigned num_buffers
,
1287 struct amdgpu_cs_buffer
*buffers
)
1289 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1290 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1291 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1293 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1294 p_atomic_inc(&bo
->num_active_ioctls
);
1295 amdgpu_add_fences(bo
, 1, &fence
);
1299 /* Since the kernel driver doesn't synchronize execution between different
1300 * rings automatically, we have to add fence dependencies manually.
1302 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1304 struct amdgpu_cs_context
*cs
= acs
->csc
;
1306 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1307 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1308 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1311 static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf
*rws
,
1312 struct pipe_fence_handle
*fence
)
1314 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1315 struct amdgpu_cs_context
*cs
= acs
->csc
;
1317 assert(amdgpu_fence_is_syncobj((struct amdgpu_fence
*)fence
));
1319 add_fence_to_list(&cs
->syncobj_to_signal
, (struct amdgpu_fence
*)fence
);
1322 /* Add backing of sparse buffers to the buffer list.
1324 * This is done late, during submission, to keep the buffer list short before
1325 * submit, and to avoid managing fences for the backing buffers.
1327 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1329 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1330 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1331 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1333 simple_mtx_lock(&bo
->lock
);
1335 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1336 /* We can directly add the buffer here, because we know that each
1337 * backing buffer occurs only once.
1339 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1341 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1342 simple_mtx_unlock(&bo
->lock
);
1346 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1347 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1348 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1351 simple_mtx_unlock(&bo
->lock
);
1357 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1359 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1360 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1361 struct amdgpu_cs_context
*cs
= acs
->cst
;
1363 uint32_t bo_list
= 0;
1364 uint64_t seq_no
= 0;
1365 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1366 bool use_bo_list_create
= ws
->info
.drm_minor
< 27;
1367 struct drm_amdgpu_bo_list_in bo_list_in
;
1369 /* Prepare the buffer list. */
1370 if (ws
->debug_all_bos
) {
1371 /* The buffer list contains all buffers. This is a slow path that
1372 * ensures that no buffer is missing in the BO list.
1374 unsigned num_handles
= 0;
1375 struct drm_amdgpu_bo_list_entry
*list
=
1376 alloca(ws
->num_buffers
* sizeof(struct drm_amdgpu_bo_list_entry
));
1377 struct amdgpu_winsys_bo
*bo
;
1379 simple_mtx_lock(&ws
->global_bo_list_lock
);
1380 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1384 list
[num_handles
].bo_handle
= bo
->u
.real
.kms_handle
;
1385 list
[num_handles
].bo_priority
= 0;
1389 r
= amdgpu_bo_list_create_raw(ws
->dev
, ws
->num_buffers
, list
, &bo_list
);
1390 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1392 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1396 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1397 fprintf(stderr
, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n");
1402 struct drm_amdgpu_bo_list_entry
*list
=
1403 alloca((cs
->num_real_buffers
+ 2) * sizeof(struct drm_amdgpu_bo_list_entry
));
1405 unsigned num_handles
= 0;
1406 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1407 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1409 if (buffer
->bo
->is_local
)
1412 assert(buffer
->u
.real
.priority_usage
!= 0);
1414 list
[num_handles
].bo_handle
= buffer
->bo
->u
.real
.kms_handle
;
1415 list
[num_handles
].bo_priority
= (util_last_bit(buffer
->u
.real
.priority_usage
) - 1) / 2;
1419 if (use_bo_list_create
) {
1420 /* Legacy path creating the buffer list handle and passing it to the CS ioctl. */
1421 r
= amdgpu_bo_list_create_raw(ws
->dev
, num_handles
, list
, &bo_list
);
1423 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1427 /* Standard path passing the buffer list via the CS ioctl. */
1428 bo_list_in
.operation
= ~0;
1429 bo_list_in
.list_handle
= ~0;
1430 bo_list_in
.bo_number
= num_handles
;
1431 bo_list_in
.bo_info_size
= sizeof(struct drm_amdgpu_bo_list_entry
);
1432 bo_list_in
.bo_info_ptr
= (uint64_t)(uintptr_t)list
;
1436 if (acs
->ring_type
== RING_GFX
)
1437 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1439 if (acs
->stop_exec_on_failure
&& acs
->ctx
->num_rejected_cs
) {
1442 struct drm_amdgpu_cs_chunk chunks
[6];
1443 unsigned num_chunks
= 0;
1446 if (!use_bo_list_create
) {
1447 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_BO_HANDLES
;
1448 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_bo_list_in
) / 4;
1449 chunks
[num_chunks
].chunk_data
= (uintptr_t)&bo_list_in
;
1453 /* Fence dependencies. */
1454 unsigned num_dependencies
= cs
->fence_dependencies
.num
;
1455 if (num_dependencies
) {
1456 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1457 alloca(num_dependencies
* sizeof(*dep_chunk
));
1459 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1460 struct amdgpu_fence
*fence
=
1461 (struct amdgpu_fence
*)cs
->fence_dependencies
.list
[i
];
1463 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1464 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1467 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1468 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_dependencies
;
1469 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1473 /* Syncobj dependencies. */
1474 unsigned num_syncobj_dependencies
= cs
->syncobj_dependencies
.num
;
1475 if (num_syncobj_dependencies
) {
1476 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1477 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1479 for (unsigned i
= 0; i
< num_syncobj_dependencies
; i
++) {
1480 struct amdgpu_fence
*fence
=
1481 (struct amdgpu_fence
*)cs
->syncobj_dependencies
.list
[i
];
1483 if (!amdgpu_fence_is_syncobj(fence
))
1486 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1487 sem_chunk
[i
].handle
= fence
->syncobj
;
1490 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1491 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num_syncobj_dependencies
;
1492 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1496 /* Submit the parallel compute IB first. */
1497 if (cs
->ib
[IB_PARALLEL_COMPUTE
].ib_bytes
> 0) {
1498 unsigned old_num_chunks
= num_chunks
;
1500 /* Add compute fence dependencies. */
1501 unsigned num_dependencies
= cs
->compute_fence_dependencies
.num
;
1502 if (num_dependencies
) {
1503 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1504 alloca(num_dependencies
* sizeof(*dep_chunk
));
1506 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1507 struct amdgpu_fence
*fence
=
1508 (struct amdgpu_fence
*)cs
->compute_fence_dependencies
.list
[i
];
1510 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1511 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1514 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1515 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_dependencies
;
1516 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1520 /* Add compute start fence dependencies. */
1521 unsigned num_start_dependencies
= cs
->compute_start_fence_dependencies
.num
;
1522 if (num_start_dependencies
) {
1523 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1524 alloca(num_start_dependencies
* sizeof(*dep_chunk
));
1526 for (unsigned i
= 0; i
< num_start_dependencies
; i
++) {
1527 struct amdgpu_fence
*fence
=
1528 (struct amdgpu_fence
*)cs
->compute_start_fence_dependencies
.list
[i
];
1530 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1531 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[i
]);
1534 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
;
1535 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num_start_dependencies
;
1536 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1540 /* Convert from dwords to bytes. */
1541 cs
->ib
[IB_PARALLEL_COMPUTE
].ib_bytes
*= 4;
1542 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1543 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1544 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_PARALLEL_COMPUTE
];
1547 r
= amdgpu_cs_submit_raw2(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1548 num_chunks
, chunks
, NULL
);
1552 /* Back off the compute chunks. */
1553 num_chunks
= old_num_chunks
;
1556 /* Syncobj signals. */
1557 unsigned num_syncobj_to_signal
= cs
->syncobj_to_signal
.num
;
1558 if (num_syncobj_to_signal
) {
1559 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1560 alloca(num_syncobj_to_signal
* sizeof(sem_chunk
[0]));
1562 for (unsigned i
= 0; i
< num_syncobj_to_signal
; i
++) {
1563 struct amdgpu_fence
*fence
=
1564 (struct amdgpu_fence
*)cs
->syncobj_to_signal
.list
[i
];
1566 assert(amdgpu_fence_is_syncobj(fence
));
1567 sem_chunk
[i
].handle
= fence
->syncobj
;
1570 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_OUT
;
1571 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4
1572 * num_syncobj_to_signal
;
1573 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1578 if (has_user_fence
) {
1579 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1580 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1581 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1586 cs
->ib
[IB_MAIN
].ib_bytes
*= 4; /* Convert from dwords to bytes. */
1587 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1588 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1589 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1592 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1594 r
= amdgpu_cs_submit_raw2(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1595 num_chunks
, chunks
, &seq_no
);
1601 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1602 else if (r
== -ECANCELED
)
1603 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1605 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1606 "see dmesg for more information (%i).\n", r
);
1608 acs
->ctx
->num_rejected_cs
++;
1609 ws
->num_total_rejected_cs
++;
1612 uint64_t *user_fence
= NULL
;
1615 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1616 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1621 amdgpu_bo_list_destroy_raw(ws
->dev
, bo_list
);
1624 /* If there was an error, signal the fence, because it won't be signalled
1625 * by the hardware. */
1627 amdgpu_fence_signalled(cs
->fence
);
1631 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1632 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1633 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1634 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1635 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1636 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1638 amdgpu_cs_context_cleanup(cs
);
1641 /* Make sure the previous submission is completed. */
1642 void amdgpu_cs_sync_flush(struct radeon_cmdbuf
*rcs
)
1644 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1646 /* Wait for any pending ioctl of this CS to complete. */
1647 util_queue_fence_wait(&cs
->flush_completed
);
1650 static int amdgpu_cs_flush(struct radeon_cmdbuf
*rcs
,
1652 struct pipe_fence_handle
**fence
)
1654 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1655 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1658 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
);
1660 switch (cs
->ring_type
) {
1662 /* pad DMA ring to 8 DWs */
1663 if (ws
->info
.chip_class
<= GFX6
) {
1664 while (rcs
->current
.cdw
& 7)
1665 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1667 while (rcs
->current
.cdw
& 7)
1668 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1673 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1674 if (ws
->info
.gfx_ib_pad_with_type2
) {
1675 while (rcs
->current
.cdw
& 7)
1676 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1678 while (rcs
->current
.cdw
& 7)
1679 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1681 if (cs
->ring_type
== RING_GFX
)
1682 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1684 /* Also pad secondary IBs. */
1685 if (cs
->compute_ib
.ib_mapped
) {
1686 while (cs
->compute_ib
.base
.current
.cdw
& 7)
1687 radeon_emit(&cs
->compute_ib
.base
, 0xffff1000); /* type3 nop packet */
1692 while (rcs
->current
.cdw
& 15)
1693 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1696 if (rcs
->current
.cdw
% 2)
1698 while (rcs
->current
.cdw
& 15) {
1699 radeon_emit(rcs
, 0x60000000); /* nop packet */
1700 radeon_emit(rcs
, 0x00000000);
1704 while (rcs
->current
.cdw
& 15)
1705 radeon_emit(rcs
, 0x81ff); /* nop packet */
1711 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1712 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1715 /* If the CS is not empty or overflowed.... */
1716 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1717 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1718 !debug_get_option_noop())) {
1719 struct amdgpu_cs_context
*cur
= cs
->csc
;
1722 amdgpu_ib_finalize(ws
, &cs
->main
);
1724 if (cs
->compute_ib
.ib_mapped
)
1725 amdgpu_ib_finalize(ws
, &cs
->compute_ib
);
1727 /* Create a fence. */
1728 amdgpu_fence_reference(&cur
->fence
, NULL
);
1729 if (cs
->next_fence
) {
1730 /* just move the reference */
1731 cur
->fence
= cs
->next_fence
;
1732 cs
->next_fence
= NULL
;
1734 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1735 cur
->ib
[IB_MAIN
].ip_type
,
1736 cur
->ib
[IB_MAIN
].ip_instance
,
1737 cur
->ib
[IB_MAIN
].ring
);
1740 amdgpu_fence_reference(fence
, cur
->fence
);
1742 amdgpu_cs_sync_flush(rcs
);
1746 * This fence must be held until the submission is queued to ensure
1747 * that the order of fence dependency updates matches the order of
1750 simple_mtx_lock(&ws
->bo_fence_lock
);
1751 amdgpu_add_fence_dependencies_bo_lists(cs
);
1753 /* Swap command streams. "cst" is going to be submitted. */
1758 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1759 amdgpu_cs_submit_ib
, NULL
);
1760 /* The submission has been queued, unlock the fence now. */
1761 simple_mtx_unlock(&ws
->bo_fence_lock
);
1763 if (!(flags
& PIPE_FLUSH_ASYNC
)) {
1764 amdgpu_cs_sync_flush(rcs
);
1765 error_code
= cur
->error_code
;
1768 amdgpu_cs_context_cleanup(cs
->csc
);
1771 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1772 if (cs
->compute_ib
.ib_mapped
)
1773 amdgpu_get_new_ib(&ws
->base
, cs
, IB_PARALLEL_COMPUTE
);
1775 cs
->main
.base
.used_gart
= 0;
1776 cs
->main
.base
.used_vram
= 0;
1778 if (cs
->ring_type
== RING_GFX
)
1780 else if (cs
->ring_type
== RING_DMA
)
1786 static void amdgpu_cs_destroy(struct radeon_cmdbuf
*rcs
)
1788 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1790 amdgpu_cs_sync_flush(rcs
);
1791 util_queue_fence_destroy(&cs
->flush_completed
);
1792 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1793 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1794 FREE(cs
->main
.base
.prev
);
1795 pb_reference(&cs
->compute_ib
.big_ib_buffer
, NULL
);
1796 FREE(cs
->compute_ib
.base
.prev
);
1797 amdgpu_destroy_cs_context(&cs
->csc1
);
1798 amdgpu_destroy_cs_context(&cs
->csc2
);
1799 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1803 static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf
*rcs
,
1804 struct pb_buffer
*_buf
,
1805 enum radeon_bo_usage usage
)
1807 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1808 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1810 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1813 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1815 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1816 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1817 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1818 ws
->base
.cs_create
= amdgpu_cs_create
;
1819 ws
->base
.cs_add_parallel_compute_ib
= amdgpu_cs_add_parallel_compute_ib
;
1820 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1821 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1822 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1823 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1824 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1825 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1826 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1827 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1828 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1829 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1830 ws
->base
.cs_add_syncobj_signal
= amdgpu_cs_add_syncobj_signal
;
1831 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1832 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1833 ws
->base
.fence_import_syncobj
= amdgpu_fence_import_syncobj
;
1834 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1835 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;
1836 ws
->base
.export_signalled_sync_file
= amdgpu_export_signalled_sync_file
;