2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
30 * Marek Olšák <maraeo@gmail.com>
33 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
36 #include <amdgpu_drm.h>
38 #include "amd/common/sid.h"
40 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
44 static struct pipe_fence_handle
*
45 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
46 unsigned ip_instance
, unsigned ring
)
48 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
50 fence
->reference
.count
= 1;
52 fence
->fence
.context
= ctx
->ctx
;
53 fence
->fence
.ip_type
= ip_type
;
54 fence
->fence
.ip_instance
= ip_instance
;
55 fence
->fence
.ring
= ring
;
56 fence
->submission_in_progress
= true;
57 p_atomic_inc(&ctx
->refcount
);
58 return (struct pipe_fence_handle
*)fence
;
61 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
62 struct amdgpu_cs_request
* request
,
63 uint64_t *user_fence_cpu_address
)
65 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
67 rfence
->fence
.fence
= request
->seq_no
;
68 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
69 rfence
->submission_in_progress
= false;
72 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
74 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
76 rfence
->signalled
= true;
77 rfence
->submission_in_progress
= false;
80 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
83 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
86 uint64_t *user_fence_cpu
;
89 if (rfence
->signalled
)
93 abs_timeout
= timeout
;
95 abs_timeout
= os_time_get_absolute_timeout(timeout
);
97 /* The fence might not have a number assigned if its IB is being
98 * submitted in the other thread right now. Wait until the submission
100 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
104 user_fence_cpu
= rfence
->user_fence_cpu_address
;
105 if (user_fence_cpu
) {
106 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
107 rfence
->signalled
= true;
111 /* No timeout, just query: no need for the ioctl. */
112 if (!absolute
&& !timeout
)
116 /* Now use the libdrm query. */
117 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
119 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
122 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
127 /* This variable can only transition from false to true, so it doesn't
128 * matter if threads race for it. */
129 rfence
->signalled
= true;
135 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
136 struct pipe_fence_handle
*fence
,
139 return amdgpu_fence_wait(fence
, timeout
, false);
142 static struct pipe_fence_handle
*
143 amdgpu_cs_get_next_fence(struct radeon_winsys_cs
*rcs
)
145 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
146 struct pipe_fence_handle
*fence
= NULL
;
148 if (debug_get_option_noop())
151 if (cs
->next_fence
) {
152 amdgpu_fence_reference(&fence
, cs
->next_fence
);
156 fence
= amdgpu_fence_create(cs
->ctx
,
157 cs
->csc
->request
.ip_type
,
158 cs
->csc
->request
.ip_instance
,
159 cs
->csc
->request
.ring
);
163 amdgpu_fence_reference(&cs
->next_fence
, fence
);
169 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
171 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
173 struct amdgpu_bo_alloc_request alloc_buffer
= {};
174 amdgpu_bo_handle buf_handle
;
179 ctx
->ws
= amdgpu_winsys(ws
);
181 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
183 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
185 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
189 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
190 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
191 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
193 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
195 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
196 goto error_user_fence_alloc
;
199 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
201 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
202 goto error_user_fence_map
;
205 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
206 ctx
->user_fence_bo
= buf_handle
;
208 return (struct radeon_winsys_ctx
*)ctx
;
210 error_user_fence_map
:
211 amdgpu_bo_free(buf_handle
);
212 error_user_fence_alloc
:
213 amdgpu_cs_ctx_free(ctx
->ctx
);
219 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
221 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
224 static enum pipe_reset_status
225 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
227 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
228 uint32_t result
, hangs
;
231 /* Return a failure due to a rejected command submission. */
232 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
233 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
234 PIPE_INNOCENT_CONTEXT_RESET
;
237 /* Return a failure due to a GPU hang. */
238 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
240 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
241 return PIPE_NO_RESET
;
245 case AMDGPU_CTX_GUILTY_RESET
:
246 return PIPE_GUILTY_CONTEXT_RESET
;
247 case AMDGPU_CTX_INNOCENT_RESET
:
248 return PIPE_INNOCENT_CONTEXT_RESET
;
249 case AMDGPU_CTX_UNKNOWN_RESET
:
250 return PIPE_UNKNOWN_CONTEXT_RESET
;
251 case AMDGPU_CTX_NO_RESET
:
253 return PIPE_NO_RESET
;
257 /* COMMAND SUBMISSION */
259 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
261 return cs
->request
.ip_type
!= AMDGPU_HW_IP_UVD
&&
262 cs
->request
.ip_type
!= AMDGPU_HW_IP_VCE
&&
263 cs
->request
.ip_type
!= AMDGPU_HW_IP_VCN_DEC
;
266 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
268 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
269 cs
->ring_type
== RING_GFX
;
272 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
274 if (ring_type
== RING_GFX
)
275 return 4; /* for chaining */
280 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
282 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
283 int i
= cs
->buffer_indices_hashlist
[hash
];
284 struct amdgpu_cs_buffer
*buffers
;
288 buffers
= cs
->real_buffers
;
289 num_buffers
= cs
->num_real_buffers
;
290 } else if (!bo
->sparse
) {
291 buffers
= cs
->slab_buffers
;
292 num_buffers
= cs
->num_slab_buffers
;
294 buffers
= cs
->sparse_buffers
;
295 num_buffers
= cs
->num_sparse_buffers
;
298 /* not found or found */
299 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
302 /* Hash collision, look for the BO in the list of buffers linearly. */
303 for (i
= num_buffers
- 1; i
>= 0; i
--) {
304 if (buffers
[i
].bo
== bo
) {
305 /* Put this buffer in the hash list.
306 * This will prevent additional hash collisions if there are
307 * several consecutive lookup_buffer calls for the same buffer.
309 * Example: Assuming buffers A,B,C collide in the hash list,
310 * the following sequence of buffers:
311 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
312 * will collide here: ^ and here: ^,
313 * meaning that we should get very few collisions in the end. */
314 cs
->buffer_indices_hashlist
[hash
] = i
;
322 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
324 struct amdgpu_cs_buffer
*buffer
;
327 /* New buffer, check if the backing array is large enough. */
328 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
330 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
331 struct amdgpu_cs_buffer
*new_buffers
;
333 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
336 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
341 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
343 FREE(cs
->real_buffers
);
345 cs
->max_real_buffers
= new_max
;
346 cs
->real_buffers
= new_buffers
;
349 idx
= cs
->num_real_buffers
;
350 buffer
= &cs
->real_buffers
[idx
];
352 memset(buffer
, 0, sizeof(*buffer
));
353 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
354 p_atomic_inc(&bo
->num_cs_references
);
355 cs
->num_real_buffers
++;
361 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
363 struct amdgpu_cs_context
*cs
= acs
->csc
;
365 int idx
= amdgpu_lookup_buffer(cs
, bo
);
370 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
372 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
373 cs
->buffer_indices_hashlist
[hash
] = idx
;
375 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
376 acs
->main
.base
.used_vram
+= bo
->base
.size
;
377 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
378 acs
->main
.base
.used_gart
+= bo
->base
.size
;
383 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
384 struct amdgpu_winsys_bo
*bo
)
386 struct amdgpu_cs_context
*cs
= acs
->csc
;
387 struct amdgpu_cs_buffer
*buffer
;
389 int idx
= amdgpu_lookup_buffer(cs
, bo
);
395 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
399 /* New buffer, check if the backing array is large enough. */
400 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
402 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
403 struct amdgpu_cs_buffer
*new_buffers
;
405 new_buffers
= REALLOC(cs
->slab_buffers
,
406 cs
->max_slab_buffers
* sizeof(*new_buffers
),
407 new_max
* sizeof(*new_buffers
));
409 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
413 cs
->max_slab_buffers
= new_max
;
414 cs
->slab_buffers
= new_buffers
;
417 idx
= cs
->num_slab_buffers
;
418 buffer
= &cs
->slab_buffers
[idx
];
420 memset(buffer
, 0, sizeof(*buffer
));
421 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
422 buffer
->u
.slab
.real_idx
= real_idx
;
423 p_atomic_inc(&bo
->num_cs_references
);
424 cs
->num_slab_buffers
++;
426 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
427 cs
->buffer_indices_hashlist
[hash
] = idx
;
432 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
433 struct amdgpu_winsys_bo
*bo
)
435 struct amdgpu_cs_context
*cs
= acs
->csc
;
436 struct amdgpu_cs_buffer
*buffer
;
438 int idx
= amdgpu_lookup_buffer(cs
, bo
);
443 /* New buffer, check if the backing array is large enough. */
444 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
446 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
447 struct amdgpu_cs_buffer
*new_buffers
;
449 new_buffers
= REALLOC(cs
->sparse_buffers
,
450 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
451 new_max
* sizeof(*new_buffers
));
453 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
457 cs
->max_sparse_buffers
= new_max
;
458 cs
->sparse_buffers
= new_buffers
;
461 idx
= cs
->num_sparse_buffers
;
462 buffer
= &cs
->sparse_buffers
[idx
];
464 memset(buffer
, 0, sizeof(*buffer
));
465 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
466 p_atomic_inc(&bo
->num_cs_references
);
467 cs
->num_sparse_buffers
++;
469 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
470 cs
->buffer_indices_hashlist
[hash
] = idx
;
472 /* We delay adding the backing buffers until we really have to. However,
473 * we cannot delay accounting for memory use.
475 mtx_lock(&bo
->u
.sparse
.commit_lock
);
477 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
478 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
479 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
480 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
481 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
484 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
489 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
490 struct pb_buffer
*buf
,
491 enum radeon_bo_usage usage
,
492 enum radeon_bo_domain domains
,
493 enum radeon_bo_priority priority
)
495 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
496 * the buffer placement during command submission.
498 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
499 struct amdgpu_cs_context
*cs
= acs
->csc
;
500 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
501 struct amdgpu_cs_buffer
*buffer
;
504 /* Fast exit for no-op calls.
505 * This is very effective with suballocators and linear uploaders that
506 * are outside of the winsys.
508 if (bo
== cs
->last_added_bo
&&
509 (usage
& cs
->last_added_bo_usage
) == usage
&&
510 (1ull << priority
) & cs
->last_added_bo_priority_usage
)
511 return cs
->last_added_bo_index
;
515 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
519 buffer
= &cs
->slab_buffers
[index
];
520 buffer
->usage
|= usage
;
522 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
523 index
= buffer
->u
.slab
.real_idx
;
525 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
530 buffer
= &cs
->real_buffers
[index
];
532 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
536 buffer
= &cs
->sparse_buffers
[index
];
539 buffer
->u
.real
.priority_usage
|= 1llu << priority
;
540 buffer
->usage
|= usage
;
542 cs
->last_added_bo
= bo
;
543 cs
->last_added_bo_index
= index
;
544 cs
->last_added_bo_usage
= buffer
->usage
;
545 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
549 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
551 struct pb_buffer
*pb
;
553 unsigned buffer_size
;
555 /* Always create a buffer that is at least as large as the maximum seen IB
556 * size, aligned to a power of two (and multiplied by 4 to reduce internal
557 * fragmentation if chaining is not available). Limit to 512k dwords, which
558 * is the largest power of two that fits into the size field of the
559 * INDIRECT_BUFFER packet.
561 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
562 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
564 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
566 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
568 switch (ib
->ib_type
) {
569 case IB_CONST_PREAMBLE
:
570 buffer_size
= MAX2(buffer_size
, 4 * 1024);
573 buffer_size
= MAX2(buffer_size
, 16 * 1024 * 4);
576 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
579 unreachable("unhandled IB type");
582 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
583 ws
->info
.gart_page_size
,
585 RADEON_FLAG_CPU_ACCESS
);
589 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
591 pb_reference(&pb
, NULL
);
595 pb_reference(&ib
->big_ib_buffer
, pb
);
596 pb_reference(&pb
, NULL
);
598 ib
->ib_mapped
= mapped
;
599 ib
->used_ib_space
= 0;
604 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
608 /* Smaller submits means the GPU gets busy sooner and there is less
609 * waiting for buffers and fences. Proof:
610 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
613 case IB_CONST_PREAMBLE
:
615 /* There isn't really any reason to limit CE IB size beyond the natural
616 * limit implied by the main IB, except perhaps GTT size. Just return
617 * an extremely large value that we never get anywhere close to.
619 return 16 * 1024 * 1024;
621 unreachable("bad ib_type");
625 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
626 enum ib_type ib_type
)
628 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
629 /* Small IBs are better than big IBs, because the GPU goes idle quicker
630 * and there is less waiting for buffers and fences. Proof:
631 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
633 struct amdgpu_ib
*ib
= NULL
;
634 struct amdgpu_cs_ib_info
*info
= &cs
->csc
->ib
[ib_type
];
635 unsigned ib_size
= 0;
638 case IB_CONST_PREAMBLE
:
639 ib
= &cs
->const_preamble_ib
;
644 ib_size
= 8 * 1024 * 4;
648 ib_size
= 4 * 1024 * 4;
651 unreachable("unhandled IB type");
654 if (!amdgpu_cs_has_chaining(cs
)) {
655 ib_size
= MAX2(ib_size
,
656 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
657 amdgpu_ib_max_submit_dwords(ib_type
)));
660 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
662 ib
->base
.prev_dw
= 0;
663 ib
->base
.num_prev
= 0;
664 ib
->base
.current
.cdw
= 0;
665 ib
->base
.current
.buf
= NULL
;
667 /* Allocate a new buffer for IBs if the current buffer is all used. */
668 if (!ib
->big_ib_buffer
||
669 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
670 if (!amdgpu_ib_new_buffer(aws
, ib
))
674 info
->ib_mc_address
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+
677 ib
->ptr_ib_size
= &info
->size
;
679 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
680 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
682 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
684 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
685 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
689 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
691 *ib
->ptr_ib_size
|= ib
->base
.current
.cdw
;
692 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
693 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
696 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
697 enum ring_type ring_type
)
701 cs
->request
.ip_type
= AMDGPU_HW_IP_DMA
;
705 cs
->request
.ip_type
= AMDGPU_HW_IP_UVD
;
709 cs
->request
.ip_type
= AMDGPU_HW_IP_VCE
;
713 cs
->request
.ip_type
= AMDGPU_HW_IP_COMPUTE
;
717 cs
->request
.ip_type
= AMDGPU_HW_IP_VCN_DEC
;
722 cs
->request
.ip_type
= AMDGPU_HW_IP_GFX
;
726 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
727 cs
->last_added_bo
= NULL
;
729 cs
->request
.number_of_ibs
= 1;
730 cs
->request
.ibs
= &cs
->ib
[IB_MAIN
];
732 cs
->ib
[IB_CONST
].flags
= AMDGPU_IB_FLAG_CE
;
733 cs
->ib
[IB_CONST_PREAMBLE
].flags
= AMDGPU_IB_FLAG_CE
|
734 AMDGPU_IB_FLAG_PREAMBLE
;
739 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
743 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
744 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
745 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
747 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
748 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
749 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
751 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
752 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
753 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
756 cs
->num_real_buffers
= 0;
757 cs
->num_slab_buffers
= 0;
758 cs
->num_sparse_buffers
= 0;
759 amdgpu_fence_reference(&cs
->fence
, NULL
);
761 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
762 cs
->last_added_bo
= NULL
;
765 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
767 amdgpu_cs_context_cleanup(cs
);
769 FREE(cs
->real_buffers
);
771 FREE(cs
->slab_buffers
);
772 FREE(cs
->sparse_buffers
);
773 FREE(cs
->request
.dependencies
);
777 static struct radeon_winsys_cs
*
778 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
779 enum ring_type ring_type
,
780 void (*flush
)(void *ctx
, unsigned flags
,
781 struct pipe_fence_handle
**fence
),
784 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
785 struct amdgpu_cs
*cs
;
787 cs
= CALLOC_STRUCT(amdgpu_cs
);
792 util_queue_fence_init(&cs
->flush_completed
);
795 cs
->flush_cs
= flush
;
796 cs
->flush_data
= flush_ctx
;
797 cs
->ring_type
= ring_type
;
799 cs
->main
.ib_type
= IB_MAIN
;
800 cs
->const_ib
.ib_type
= IB_CONST
;
801 cs
->const_preamble_ib
.ib_type
= IB_CONST_PREAMBLE
;
803 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
808 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
809 amdgpu_destroy_cs_context(&cs
->csc1
);
814 /* Set the first submission context as current. */
818 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
819 amdgpu_destroy_cs_context(&cs
->csc2
);
820 amdgpu_destroy_cs_context(&cs
->csc1
);
825 p_atomic_inc(&ctx
->ws
->num_cs
);
826 return &cs
->main
.base
;
829 static struct radeon_winsys_cs
*
830 amdgpu_cs_add_const_ib(struct radeon_winsys_cs
*rcs
)
832 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
833 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
835 /* only one const IB can be added */
836 if (cs
->ring_type
!= RING_GFX
|| cs
->const_ib
.ib_mapped
)
839 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
))
842 cs
->csc
->request
.number_of_ibs
= 2;
843 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST
];
845 cs
->cst
->request
.number_of_ibs
= 2;
846 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST
];
848 return &cs
->const_ib
.base
;
851 static struct radeon_winsys_cs
*
852 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs
*rcs
)
854 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
855 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
857 /* only one const preamble IB can be added and only when the const IB has
858 * also been mapped */
859 if (cs
->ring_type
!= RING_GFX
|| !cs
->const_ib
.ib_mapped
||
860 cs
->const_preamble_ib
.ib_mapped
)
863 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
))
866 cs
->csc
->request
.number_of_ibs
= 3;
867 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST_PREAMBLE
];
869 cs
->cst
->request
.number_of_ibs
= 3;
870 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST_PREAMBLE
];
872 return &cs
->const_preamble_ib
.base
;
875 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
880 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
882 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
883 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
884 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
886 uint32_t *new_ptr_ib_size
;
888 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
890 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
893 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
895 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
898 if (!amdgpu_cs_has_chaining(cs
))
901 /* Allocate a new chunk */
902 if (rcs
->num_prev
>= rcs
->max_prev
) {
903 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
904 struct radeon_winsys_cs_chunk
*new_prev
;
906 new_prev
= REALLOC(rcs
->prev
,
907 sizeof(*new_prev
) * rcs
->max_prev
,
908 sizeof(*new_prev
) * new_max_prev
);
912 rcs
->prev
= new_prev
;
913 rcs
->max_prev
= new_max_prev
;
916 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
))
919 assert(ib
->used_ib_space
== 0);
920 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
922 /* This space was originally reserved. */
923 rcs
->current
.max_dw
+= 4;
924 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
926 /* Pad with NOPs and add INDIRECT_BUFFER packet */
927 while ((rcs
->current
.cdw
& 7) != 4)
928 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
930 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
931 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
932 radeon_emit(rcs
, va
);
933 radeon_emit(rcs
, va
>> 32);
934 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
];
935 radeon_emit(rcs
, S_3F2_CHAIN(1) | S_3F2_VALID(1));
937 assert((rcs
->current
.cdw
& 7) == 0);
938 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
940 *ib
->ptr_ib_size
|= rcs
->current
.cdw
;
941 ib
->ptr_ib_size
= new_ptr_ib_size
;
943 /* Hook up the new chunk */
944 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
945 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
946 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
949 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
950 ib
->base
.current
.cdw
= 0;
952 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
953 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
955 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
956 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
961 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
962 struct radeon_bo_list_item
*list
)
964 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
968 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
969 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
970 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
971 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
974 return cs
->num_real_buffers
;
977 DEBUG_GET_ONCE_BOOL_OPTION(all_bos
, "RADEON_ALL_BOS", false)
979 static void amdgpu_add_fence_dependency(struct amdgpu_cs
*acs
,
980 struct amdgpu_cs_buffer
*buffer
)
982 struct amdgpu_cs_context
*cs
= acs
->csc
;
983 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
984 struct amdgpu_cs_fence
*dep
;
985 unsigned new_num_fences
= 0;
987 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
988 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
991 if (bo_fence
->ctx
== acs
->ctx
&&
992 bo_fence
->fence
.ip_type
== cs
->request
.ip_type
&&
993 bo_fence
->fence
.ip_instance
== cs
->request
.ip_instance
&&
994 bo_fence
->fence
.ring
== cs
->request
.ring
)
997 if (amdgpu_fence_wait((void *)bo_fence
, 0, false))
1000 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1003 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1006 if (bo_fence
->submission_in_progress
)
1007 os_wait_until_zero(&bo_fence
->submission_in_progress
,
1008 PIPE_TIMEOUT_INFINITE
);
1010 idx
= cs
->request
.number_of_dependencies
++;
1011 if (idx
>= cs
->max_dependencies
) {
1014 cs
->max_dependencies
= idx
+ 8;
1015 size
= cs
->max_dependencies
* sizeof(struct amdgpu_cs_fence
);
1016 cs
->request
.dependencies
= realloc(cs
->request
.dependencies
, size
);
1019 dep
= &cs
->request
.dependencies
[idx
];
1020 memcpy(dep
, &bo_fence
->fence
, sizeof(*dep
));
1023 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1024 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1026 bo
->num_fences
= new_num_fences
;
1029 /* Add the given list of fences to the buffer's fence list.
1031 * Must be called with the winsys bo_fence_lock held.
1033 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1034 unsigned num_fences
,
1035 struct pipe_fence_handle
**fences
)
1037 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1038 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1039 struct pipe_fence_handle
**new_fences
=
1041 bo
->num_fences
* sizeof(*new_fences
),
1042 new_max_fences
* sizeof(*new_fences
));
1043 if (likely(new_fences
)) {
1044 bo
->fences
= new_fences
;
1045 bo
->max_fences
= new_max_fences
;
1049 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1050 if (!bo
->num_fences
)
1053 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1054 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1056 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1062 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1063 bo
->fences
[bo
->num_fences
] = NULL
;
1064 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1069 static void amdgpu_add_fence_dependencies_list(struct amdgpu_cs
*acs
,
1070 struct pipe_fence_handle
*fence
,
1071 unsigned num_buffers
,
1072 struct amdgpu_cs_buffer
*buffers
)
1074 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1075 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1076 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1078 amdgpu_add_fence_dependency(acs
, buffer
);
1079 p_atomic_inc(&bo
->num_active_ioctls
);
1080 amdgpu_add_fences(bo
, 1, &fence
);
1084 /* Since the kernel driver doesn't synchronize execution between different
1085 * rings automatically, we have to add fence dependencies manually.
1087 static void amdgpu_add_fence_dependencies(struct amdgpu_cs
*acs
)
1089 struct amdgpu_cs_context
*cs
= acs
->csc
;
1091 cs
->request
.number_of_dependencies
= 0;
1093 amdgpu_add_fence_dependencies_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1094 amdgpu_add_fence_dependencies_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1095 amdgpu_add_fence_dependencies_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1098 /* Add backing of sparse buffers to the buffer list.
1100 * This is done late, during submission, to keep the buffer list short before
1101 * submit, and to avoid managing fences for the backing buffers.
1103 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1105 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1106 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1107 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1109 mtx_lock(&bo
->u
.sparse
.commit_lock
);
1111 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1112 /* We can directly add the buffer here, because we know that each
1113 * backing buffer occurs only once.
1115 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1117 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1118 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1122 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1123 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1124 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1127 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1133 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1135 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1136 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1137 struct amdgpu_cs_context
*cs
= acs
->cst
;
1140 cs
->request
.fence_info
.handle
= NULL
;
1141 if (amdgpu_cs_has_user_fence(cs
)) {
1142 cs
->request
.fence_info
.handle
= acs
->ctx
->user_fence_bo
;
1143 cs
->request
.fence_info
.offset
= acs
->ring_type
;
1146 /* Create the buffer list.
1147 * Use a buffer list containing all allocated buffers if requested.
1149 if (debug_get_option_all_bos()) {
1150 struct amdgpu_winsys_bo
*bo
;
1151 amdgpu_bo_handle
*handles
;
1154 mtx_lock(&ws
->global_bo_list_lock
);
1156 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
1158 mtx_unlock(&ws
->global_bo_list_lock
);
1159 amdgpu_cs_context_cleanup(cs
);
1160 cs
->error_code
= -ENOMEM
;
1164 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1165 assert(num
< ws
->num_buffers
);
1166 handles
[num
++] = bo
->bo
;
1169 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1171 &cs
->request
.resources
);
1173 mtx_unlock(&ws
->global_bo_list_lock
);
1175 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1180 if (cs
->max_real_submit
< cs
->num_real_buffers
) {
1184 cs
->handles
= MALLOC(sizeof(*cs
->handles
) * cs
->num_real_buffers
);
1185 cs
->flags
= MALLOC(sizeof(*cs
->flags
) * cs
->num_real_buffers
);
1187 if (!cs
->handles
|| !cs
->flags
) {
1188 cs
->max_real_submit
= 0;
1194 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1195 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1197 assert(buffer
->u
.real
.priority_usage
!= 0);
1199 cs
->handles
[i
] = buffer
->bo
->bo
;
1200 cs
->flags
[i
] = (util_last_bit64(buffer
->u
.real
.priority_usage
) - 1) / 4;
1203 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_real_buffers
,
1204 cs
->handles
, cs
->flags
,
1205 &cs
->request
.resources
);
1210 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1211 cs
->request
.resources
= NULL
;
1212 amdgpu_fence_signalled(cs
->fence
);
1217 if (acs
->ctx
->num_rejected_cs
)
1220 r
= amdgpu_cs_submit(acs
->ctx
->ctx
, 0, &cs
->request
, 1);
1225 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1226 else if (r
== -ECANCELED
)
1227 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1229 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1230 "see dmesg for more information (%i).\n", r
);
1232 amdgpu_fence_signalled(cs
->fence
);
1234 acs
->ctx
->num_rejected_cs
++;
1235 ws
->num_total_rejected_cs
++;
1238 uint64_t *user_fence
= NULL
;
1239 if (amdgpu_cs_has_user_fence(cs
))
1240 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+
1241 cs
->request
.fence_info
.offset
;
1242 amdgpu_fence_submitted(cs
->fence
, &cs
->request
, user_fence
);
1246 if (cs
->request
.resources
)
1247 amdgpu_bo_list_destroy(cs
->request
.resources
);
1250 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1251 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1252 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1253 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1254 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1255 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1257 amdgpu_cs_context_cleanup(cs
);
1260 /* Make sure the previous submission is completed. */
1261 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
1263 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1265 /* Wait for any pending ioctl of this CS to complete. */
1266 util_queue_fence_wait(&cs
->flush_completed
);
1269 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
1271 struct pipe_fence_handle
**fence
)
1273 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1274 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1277 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1279 switch (cs
->ring_type
) {
1281 /* pad DMA ring to 8 DWs */
1282 if (ws
->info
.chip_class
<= SI
) {
1283 while (rcs
->current
.cdw
& 7)
1284 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1286 while (rcs
->current
.cdw
& 7)
1287 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1291 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1292 if (ws
->info
.gfx_ib_pad_with_type2
) {
1293 while (rcs
->current
.cdw
& 7)
1294 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1296 while (rcs
->current
.cdw
& 7)
1297 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1300 /* Also pad the const IB. */
1301 if (cs
->const_ib
.ib_mapped
)
1302 while (!cs
->const_ib
.base
.current
.cdw
|| (cs
->const_ib
.base
.current
.cdw
& 7))
1303 radeon_emit(&cs
->const_ib
.base
, 0xffff1000); /* type3 nop packet */
1305 if (cs
->const_preamble_ib
.ib_mapped
)
1306 while (!cs
->const_preamble_ib
.base
.current
.cdw
|| (cs
->const_preamble_ib
.base
.current
.cdw
& 7))
1307 radeon_emit(&cs
->const_preamble_ib
.base
, 0xffff1000);
1310 while (rcs
->current
.cdw
& 15)
1311 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1314 while (rcs
->current
.cdw
& 15)
1315 radeon_emit(rcs
, 0x81ff); /* nop packet */
1321 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1322 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1325 /* If the CS is not empty or overflowed.... */
1326 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1327 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1328 !debug_get_option_noop())) {
1329 struct amdgpu_cs_context
*cur
= cs
->csc
;
1332 amdgpu_ib_finalize(&cs
->main
);
1334 if (cs
->const_ib
.ib_mapped
)
1335 amdgpu_ib_finalize(&cs
->const_ib
);
1337 if (cs
->const_preamble_ib
.ib_mapped
)
1338 amdgpu_ib_finalize(&cs
->const_preamble_ib
);
1340 /* Create a fence. */
1341 amdgpu_fence_reference(&cur
->fence
, NULL
);
1342 if (cs
->next_fence
) {
1343 /* just move the reference */
1344 cur
->fence
= cs
->next_fence
;
1345 cs
->next_fence
= NULL
;
1347 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1348 cur
->request
.ip_type
,
1349 cur
->request
.ip_instance
,
1353 amdgpu_fence_reference(fence
, cur
->fence
);
1355 amdgpu_cs_sync_flush(rcs
);
1359 * This fence must be held until the submission is queued to ensure
1360 * that the order of fence dependency updates matches the order of
1363 mtx_lock(&ws
->bo_fence_lock
);
1364 amdgpu_add_fence_dependencies(cs
);
1366 /* Swap command streams. "cst" is going to be submitted. */
1371 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1372 amdgpu_cs_submit_ib
, NULL
);
1373 /* The submission has been queued, unlock the fence now. */
1374 mtx_unlock(&ws
->bo_fence_lock
);
1376 if (!(flags
& RADEON_FLUSH_ASYNC
)) {
1377 amdgpu_cs_sync_flush(rcs
);
1378 error_code
= cur
->error_code
;
1381 amdgpu_cs_context_cleanup(cs
->csc
);
1384 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1385 if (cs
->const_ib
.ib_mapped
)
1386 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
);
1387 if (cs
->const_preamble_ib
.ib_mapped
)
1388 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
);
1390 cs
->main
.base
.used_gart
= 0;
1391 cs
->main
.base
.used_vram
= 0;
1393 if (cs
->ring_type
== RING_GFX
)
1395 else if (cs
->ring_type
== RING_DMA
)
1401 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1403 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1405 amdgpu_cs_sync_flush(rcs
);
1406 util_queue_fence_destroy(&cs
->flush_completed
);
1407 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1408 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1409 FREE(cs
->main
.base
.prev
);
1410 pb_reference(&cs
->const_ib
.big_ib_buffer
, NULL
);
1411 FREE(cs
->const_ib
.base
.prev
);
1412 pb_reference(&cs
->const_preamble_ib
.big_ib_buffer
, NULL
);
1413 FREE(cs
->const_preamble_ib
.base
.prev
);
1414 amdgpu_destroy_cs_context(&cs
->csc1
);
1415 amdgpu_destroy_cs_context(&cs
->csc2
);
1416 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1420 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1421 struct pb_buffer
*_buf
,
1422 enum radeon_bo_usage usage
)
1424 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1425 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1427 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1430 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1432 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1433 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1434 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1435 ws
->base
.cs_create
= amdgpu_cs_create
;
1436 ws
->base
.cs_add_const_ib
= amdgpu_cs_add_const_ib
;
1437 ws
->base
.cs_add_const_preamble_ib
= amdgpu_cs_add_const_preamble_ib
;
1438 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1439 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1440 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1441 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1442 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1443 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1444 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1445 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1446 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1447 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1448 ws
->base
.fence_reference
= amdgpu_fence_reference
;