2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
30 * Marek Olšák <maraeo@gmail.com>
33 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
36 #include <amdgpu_drm.h>
38 #include "amd/common/sid.h"
40 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
44 static struct pipe_fence_handle
*
45 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
46 unsigned ip_instance
, unsigned ring
)
48 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
50 fence
->reference
.count
= 1;
52 fence
->fence
.context
= ctx
->ctx
;
53 fence
->fence
.ip_type
= ip_type
;
54 fence
->fence
.ip_instance
= ip_instance
;
55 fence
->fence
.ring
= ring
;
56 fence
->submission_in_progress
= true;
57 p_atomic_inc(&ctx
->refcount
);
58 return (struct pipe_fence_handle
*)fence
;
61 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
62 struct amdgpu_cs_request
* request
,
63 uint64_t *user_fence_cpu_address
)
65 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
67 rfence
->fence
.fence
= request
->seq_no
;
68 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
69 rfence
->submission_in_progress
= false;
72 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
74 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
76 rfence
->signalled
= true;
77 rfence
->submission_in_progress
= false;
80 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
83 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
86 uint64_t *user_fence_cpu
;
89 if (rfence
->signalled
)
93 abs_timeout
= timeout
;
95 abs_timeout
= os_time_get_absolute_timeout(timeout
);
97 /* The fence might not have a number assigned if its IB is being
98 * submitted in the other thread right now. Wait until the submission
100 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
104 user_fence_cpu
= rfence
->user_fence_cpu_address
;
105 if (user_fence_cpu
) {
106 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
107 rfence
->signalled
= true;
111 /* No timeout, just query: no need for the ioctl. */
112 if (!absolute
&& !timeout
)
116 /* Now use the libdrm query. */
117 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
119 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
122 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
127 /* This variable can only transition from false to true, so it doesn't
128 * matter if threads race for it. */
129 rfence
->signalled
= true;
135 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
136 struct pipe_fence_handle
*fence
,
139 return amdgpu_fence_wait(fence
, timeout
, false);
142 static struct pipe_fence_handle
*
143 amdgpu_cs_get_next_fence(struct radeon_winsys_cs
*rcs
)
145 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
146 struct pipe_fence_handle
*fence
= NULL
;
148 if (debug_get_option_noop())
151 if (cs
->next_fence
) {
152 amdgpu_fence_reference(&fence
, cs
->next_fence
);
156 fence
= amdgpu_fence_create(cs
->ctx
,
157 cs
->csc
->request
.ip_type
,
158 cs
->csc
->request
.ip_instance
,
159 cs
->csc
->request
.ring
);
163 amdgpu_fence_reference(&cs
->next_fence
, fence
);
169 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
171 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
173 struct amdgpu_bo_alloc_request alloc_buffer
= {};
174 amdgpu_bo_handle buf_handle
;
179 ctx
->ws
= amdgpu_winsys(ws
);
181 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
183 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
185 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
189 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
190 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
191 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
193 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
195 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
196 goto error_user_fence_alloc
;
199 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
201 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
202 goto error_user_fence_map
;
205 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
206 ctx
->user_fence_bo
= buf_handle
;
208 return (struct radeon_winsys_ctx
*)ctx
;
210 error_user_fence_map
:
211 amdgpu_bo_free(buf_handle
);
212 error_user_fence_alloc
:
213 amdgpu_cs_ctx_free(ctx
->ctx
);
219 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
221 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
224 static enum pipe_reset_status
225 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
227 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
228 uint32_t result
, hangs
;
231 /* Return a failure due to a rejected command submission. */
232 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
233 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
234 PIPE_INNOCENT_CONTEXT_RESET
;
237 /* Return a failure due to a GPU hang. */
238 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
240 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
241 return PIPE_NO_RESET
;
245 case AMDGPU_CTX_GUILTY_RESET
:
246 return PIPE_GUILTY_CONTEXT_RESET
;
247 case AMDGPU_CTX_INNOCENT_RESET
:
248 return PIPE_INNOCENT_CONTEXT_RESET
;
249 case AMDGPU_CTX_UNKNOWN_RESET
:
250 return PIPE_UNKNOWN_CONTEXT_RESET
;
251 case AMDGPU_CTX_NO_RESET
:
253 return PIPE_NO_RESET
;
257 /* COMMAND SUBMISSION */
259 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
261 return cs
->request
.ip_type
!= AMDGPU_HW_IP_UVD
&&
262 cs
->request
.ip_type
!= AMDGPU_HW_IP_VCE
;
265 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
267 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
268 cs
->ring_type
== RING_GFX
;
271 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
273 if (ring_type
== RING_GFX
)
274 return 4; /* for chaining */
279 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
281 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
282 int i
= cs
->buffer_indices_hashlist
[hash
];
283 struct amdgpu_cs_buffer
*buffers
;
287 buffers
= cs
->real_buffers
;
288 num_buffers
= cs
->num_real_buffers
;
290 buffers
= cs
->slab_buffers
;
291 num_buffers
= cs
->num_slab_buffers
;
294 /* not found or found */
295 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
298 /* Hash collision, look for the BO in the list of buffers linearly. */
299 for (i
= num_buffers
- 1; i
>= 0; i
--) {
300 if (buffers
[i
].bo
== bo
) {
301 /* Put this buffer in the hash list.
302 * This will prevent additional hash collisions if there are
303 * several consecutive lookup_buffer calls for the same buffer.
305 * Example: Assuming buffers A,B,C collide in the hash list,
306 * the following sequence of buffers:
307 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
308 * will collide here: ^ and here: ^,
309 * meaning that we should get very few collisions in the end. */
310 cs
->buffer_indices_hashlist
[hash
] = i
;
318 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
320 struct amdgpu_cs_buffer
*buffer
;
323 /* New buffer, check if the backing array is large enough. */
324 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
326 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
327 struct amdgpu_cs_buffer
*new_buffers
;
329 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
332 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
337 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
339 FREE(cs
->real_buffers
);
341 cs
->max_real_buffers
= new_max
;
342 cs
->real_buffers
= new_buffers
;
345 idx
= cs
->num_real_buffers
;
346 buffer
= &cs
->real_buffers
[idx
];
348 memset(buffer
, 0, sizeof(*buffer
));
349 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
350 p_atomic_inc(&bo
->num_cs_references
);
351 cs
->num_real_buffers
++;
357 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
359 struct amdgpu_cs_context
*cs
= acs
->csc
;
361 int idx
= amdgpu_lookup_buffer(cs
, bo
);
366 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
368 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
369 cs
->buffer_indices_hashlist
[hash
] = idx
;
371 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
372 acs
->main
.base
.used_vram
+= bo
->base
.size
;
373 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
374 acs
->main
.base
.used_gart
+= bo
->base
.size
;
379 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
380 struct amdgpu_winsys_bo
*bo
)
382 struct amdgpu_cs_context
*cs
= acs
->csc
;
383 struct amdgpu_cs_buffer
*buffer
;
385 int idx
= amdgpu_lookup_buffer(cs
, bo
);
391 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
395 /* New buffer, check if the backing array is large enough. */
396 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
398 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
399 struct amdgpu_cs_buffer
*new_buffers
;
401 new_buffers
= REALLOC(cs
->slab_buffers
,
402 cs
->max_slab_buffers
* sizeof(*new_buffers
),
403 new_max
* sizeof(*new_buffers
));
405 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
409 cs
->max_slab_buffers
= new_max
;
410 cs
->slab_buffers
= new_buffers
;
413 idx
= cs
->num_slab_buffers
;
414 buffer
= &cs
->slab_buffers
[idx
];
416 memset(buffer
, 0, sizeof(*buffer
));
417 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
418 buffer
->u
.slab
.real_idx
= real_idx
;
419 p_atomic_inc(&bo
->num_cs_references
);
420 cs
->num_slab_buffers
++;
422 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
423 cs
->buffer_indices_hashlist
[hash
] = idx
;
428 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
429 struct pb_buffer
*buf
,
430 enum radeon_bo_usage usage
,
431 enum radeon_bo_domain domains
,
432 enum radeon_bo_priority priority
)
434 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
435 * the buffer placement during command submission.
437 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
438 struct amdgpu_cs_context
*cs
= acs
->csc
;
439 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
440 struct amdgpu_cs_buffer
*buffer
;
443 /* Fast exit for no-op calls.
444 * This is very effective with suballocators and linear uploaders that
445 * are outside of the winsys.
447 if (bo
== cs
->last_added_bo
&&
448 (usage
& cs
->last_added_bo_usage
) == usage
&&
449 (1ull << priority
) & cs
->last_added_bo_priority_usage
)
450 return cs
->last_added_bo_index
;
453 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
457 buffer
= &cs
->slab_buffers
[index
];
458 buffer
->usage
|= usage
;
460 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
461 index
= buffer
->u
.slab
.real_idx
;
463 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
468 buffer
= &cs
->real_buffers
[index
];
469 buffer
->u
.real
.priority_usage
|= 1llu << priority
;
470 buffer
->usage
|= usage
;
472 cs
->last_added_bo
= bo
;
473 cs
->last_added_bo_index
= index
;
474 cs
->last_added_bo_usage
= buffer
->usage
;
475 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
479 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
481 struct pb_buffer
*pb
;
483 unsigned buffer_size
;
485 /* Always create a buffer that is at least as large as the maximum seen IB
486 * size, aligned to a power of two (and multiplied by 4 to reduce internal
487 * fragmentation if chaining is not available). Limit to 512k dwords, which
488 * is the largest power of two that fits into the size field of the
489 * INDIRECT_BUFFER packet.
491 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
492 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
494 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
496 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
498 switch (ib
->ib_type
) {
499 case IB_CONST_PREAMBLE
:
500 buffer_size
= MAX2(buffer_size
, 4 * 1024);
503 buffer_size
= MAX2(buffer_size
, 16 * 1024 * 4);
506 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
509 unreachable("unhandled IB type");
512 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
513 ws
->info
.gart_page_size
,
515 RADEON_FLAG_CPU_ACCESS
);
519 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
521 pb_reference(&pb
, NULL
);
525 pb_reference(&ib
->big_ib_buffer
, pb
);
526 pb_reference(&pb
, NULL
);
528 ib
->ib_mapped
= mapped
;
529 ib
->used_ib_space
= 0;
534 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
538 /* Smaller submits means the GPU gets busy sooner and there is less
539 * waiting for buffers and fences. Proof:
540 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
543 case IB_CONST_PREAMBLE
:
545 /* There isn't really any reason to limit CE IB size beyond the natural
546 * limit implied by the main IB, except perhaps GTT size. Just return
547 * an extremely large value that we never get anywhere close to.
549 return 16 * 1024 * 1024;
551 unreachable("bad ib_type");
555 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
556 enum ib_type ib_type
)
558 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
559 /* Small IBs are better than big IBs, because the GPU goes idle quicker
560 * and there is less waiting for buffers and fences. Proof:
561 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
563 struct amdgpu_ib
*ib
= NULL
;
564 struct amdgpu_cs_ib_info
*info
= &cs
->csc
->ib
[ib_type
];
565 unsigned ib_size
= 0;
568 case IB_CONST_PREAMBLE
:
569 ib
= &cs
->const_preamble_ib
;
574 ib_size
= 8 * 1024 * 4;
578 ib_size
= 4 * 1024 * 4;
581 unreachable("unhandled IB type");
584 if (!amdgpu_cs_has_chaining(cs
)) {
585 ib_size
= MAX2(ib_size
,
586 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
587 amdgpu_ib_max_submit_dwords(ib_type
)));
590 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
592 ib
->base
.prev_dw
= 0;
593 ib
->base
.num_prev
= 0;
594 ib
->base
.current
.cdw
= 0;
595 ib
->base
.current
.buf
= NULL
;
597 /* Allocate a new buffer for IBs if the current buffer is all used. */
598 if (!ib
->big_ib_buffer
||
599 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
600 if (!amdgpu_ib_new_buffer(aws
, ib
))
604 info
->ib_mc_address
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+
607 ib
->ptr_ib_size
= &info
->size
;
609 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
610 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
612 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
614 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
615 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
619 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
621 *ib
->ptr_ib_size
|= ib
->base
.current
.cdw
;
622 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
623 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
626 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
627 enum ring_type ring_type
)
633 cs
->request
.ip_type
= AMDGPU_HW_IP_DMA
;
637 cs
->request
.ip_type
= AMDGPU_HW_IP_UVD
;
641 cs
->request
.ip_type
= AMDGPU_HW_IP_VCE
;
645 cs
->request
.ip_type
= AMDGPU_HW_IP_COMPUTE
;
650 cs
->request
.ip_type
= AMDGPU_HW_IP_GFX
;
654 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
655 cs
->buffer_indices_hashlist
[i
] = -1;
657 cs
->last_added_bo
= NULL
;
659 cs
->request
.number_of_ibs
= 1;
660 cs
->request
.ibs
= &cs
->ib
[IB_MAIN
];
662 cs
->ib
[IB_CONST
].flags
= AMDGPU_IB_FLAG_CE
;
663 cs
->ib
[IB_CONST_PREAMBLE
].flags
= AMDGPU_IB_FLAG_CE
|
664 AMDGPU_IB_FLAG_PREAMBLE
;
669 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
673 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
674 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
675 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
677 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
678 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
679 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
682 cs
->num_real_buffers
= 0;
683 cs
->num_slab_buffers
= 0;
684 amdgpu_fence_reference(&cs
->fence
, NULL
);
686 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
687 cs
->buffer_indices_hashlist
[i
] = -1;
689 cs
->last_added_bo
= NULL
;
692 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
694 amdgpu_cs_context_cleanup(cs
);
696 FREE(cs
->real_buffers
);
698 FREE(cs
->slab_buffers
);
699 FREE(cs
->request
.dependencies
);
703 static struct radeon_winsys_cs
*
704 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
705 enum ring_type ring_type
,
706 void (*flush
)(void *ctx
, unsigned flags
,
707 struct pipe_fence_handle
**fence
),
710 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
711 struct amdgpu_cs
*cs
;
713 cs
= CALLOC_STRUCT(amdgpu_cs
);
718 util_queue_fence_init(&cs
->flush_completed
);
721 cs
->flush_cs
= flush
;
722 cs
->flush_data
= flush_ctx
;
723 cs
->ring_type
= ring_type
;
725 cs
->main
.ib_type
= IB_MAIN
;
726 cs
->const_ib
.ib_type
= IB_CONST
;
727 cs
->const_preamble_ib
.ib_type
= IB_CONST_PREAMBLE
;
729 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
734 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
735 amdgpu_destroy_cs_context(&cs
->csc1
);
740 /* Set the first submission context as current. */
744 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
745 amdgpu_destroy_cs_context(&cs
->csc2
);
746 amdgpu_destroy_cs_context(&cs
->csc1
);
751 p_atomic_inc(&ctx
->ws
->num_cs
);
752 return &cs
->main
.base
;
755 static struct radeon_winsys_cs
*
756 amdgpu_cs_add_const_ib(struct radeon_winsys_cs
*rcs
)
758 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
759 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
761 /* only one const IB can be added */
762 if (cs
->ring_type
!= RING_GFX
|| cs
->const_ib
.ib_mapped
)
765 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
))
768 cs
->csc
->request
.number_of_ibs
= 2;
769 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST
];
771 cs
->cst
->request
.number_of_ibs
= 2;
772 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST
];
774 return &cs
->const_ib
.base
;
777 static struct radeon_winsys_cs
*
778 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs
*rcs
)
780 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
781 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
783 /* only one const preamble IB can be added and only when the const IB has
784 * also been mapped */
785 if (cs
->ring_type
!= RING_GFX
|| !cs
->const_ib
.ib_mapped
||
786 cs
->const_preamble_ib
.ib_mapped
)
789 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
))
792 cs
->csc
->request
.number_of_ibs
= 3;
793 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST_PREAMBLE
];
795 cs
->cst
->request
.number_of_ibs
= 3;
796 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST_PREAMBLE
];
798 return &cs
->const_preamble_ib
.base
;
801 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
806 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
808 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
809 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
810 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
812 uint32_t *new_ptr_ib_size
;
814 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
816 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
819 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
821 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
824 if (!amdgpu_cs_has_chaining(cs
))
827 /* Allocate a new chunk */
828 if (rcs
->num_prev
>= rcs
->max_prev
) {
829 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
830 struct radeon_winsys_cs_chunk
*new_prev
;
832 new_prev
= REALLOC(rcs
->prev
,
833 sizeof(*new_prev
) * rcs
->max_prev
,
834 sizeof(*new_prev
) * new_max_prev
);
838 rcs
->prev
= new_prev
;
839 rcs
->max_prev
= new_max_prev
;
842 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
))
845 assert(ib
->used_ib_space
== 0);
846 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
848 /* This space was originally reserved. */
849 rcs
->current
.max_dw
+= 4;
850 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
852 /* Pad with NOPs and add INDIRECT_BUFFER packet */
853 while ((rcs
->current
.cdw
& 7) != 4)
854 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
856 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
857 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
858 radeon_emit(rcs
, va
);
859 radeon_emit(rcs
, va
>> 32);
860 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
];
861 radeon_emit(rcs
, S_3F2_CHAIN(1) | S_3F2_VALID(1));
863 assert((rcs
->current
.cdw
& 7) == 0);
864 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
866 *ib
->ptr_ib_size
|= rcs
->current
.cdw
;
867 ib
->ptr_ib_size
= new_ptr_ib_size
;
869 /* Hook up the new chunk */
870 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
871 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
872 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
875 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
876 ib
->base
.current
.cdw
= 0;
878 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
879 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
881 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
882 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
887 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
888 struct radeon_bo_list_item
*list
)
890 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
894 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
895 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
896 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
897 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
900 return cs
->num_real_buffers
;
903 DEBUG_GET_ONCE_BOOL_OPTION(all_bos
, "RADEON_ALL_BOS", false)
905 static void amdgpu_add_fence_dependency(struct amdgpu_cs
*acs
,
906 struct amdgpu_cs_buffer
*buffer
)
908 struct amdgpu_cs_context
*cs
= acs
->csc
;
909 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
910 struct amdgpu_cs_fence
*dep
;
911 unsigned new_num_fences
= 0;
913 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
914 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
917 if (bo_fence
->ctx
== acs
->ctx
&&
918 bo_fence
->fence
.ip_type
== cs
->request
.ip_type
&&
919 bo_fence
->fence
.ip_instance
== cs
->request
.ip_instance
&&
920 bo_fence
->fence
.ring
== cs
->request
.ring
)
923 if (amdgpu_fence_wait((void *)bo_fence
, 0, false))
926 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
929 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
932 if (bo_fence
->submission_in_progress
)
933 os_wait_until_zero(&bo_fence
->submission_in_progress
,
934 PIPE_TIMEOUT_INFINITE
);
936 idx
= cs
->request
.number_of_dependencies
++;
937 if (idx
>= cs
->max_dependencies
) {
940 cs
->max_dependencies
= idx
+ 8;
941 size
= cs
->max_dependencies
* sizeof(struct amdgpu_cs_fence
);
942 cs
->request
.dependencies
= realloc(cs
->request
.dependencies
, size
);
945 dep
= &cs
->request
.dependencies
[idx
];
946 memcpy(dep
, &bo_fence
->fence
, sizeof(*dep
));
949 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
950 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
952 bo
->num_fences
= new_num_fences
;
955 static void amdgpu_add_fence(struct amdgpu_winsys_bo
*bo
,
956 struct pipe_fence_handle
*fence
)
958 if (bo
->num_fences
>= bo
->max_fences
) {
959 unsigned new_max_fences
= MAX2(1, bo
->max_fences
* 2);
960 struct pipe_fence_handle
**new_fences
=
962 bo
->num_fences
* sizeof(*new_fences
),
963 new_max_fences
* sizeof(*new_fences
));
965 bo
->fences
= new_fences
;
966 bo
->max_fences
= new_max_fences
;
968 fprintf(stderr
, "amdgpu_add_fence: allocation failure, dropping fence\n");
972 bo
->num_fences
--; /* prefer to keep a more recent fence if possible */
973 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
977 bo
->fences
[bo
->num_fences
] = NULL
;
978 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fence
);
982 static void amdgpu_add_fence_dependencies_list(struct amdgpu_cs
*acs
,
983 struct pipe_fence_handle
*fence
,
984 unsigned num_buffers
,
985 struct amdgpu_cs_buffer
*buffers
)
987 for (unsigned i
= 0; i
< num_buffers
; i
++) {
988 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
989 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
991 amdgpu_add_fence_dependency(acs
, buffer
);
992 p_atomic_inc(&bo
->num_active_ioctls
);
993 amdgpu_add_fence(bo
, fence
);
997 /* Since the kernel driver doesn't synchronize execution between different
998 * rings automatically, we have to add fence dependencies manually.
1000 static void amdgpu_add_fence_dependencies(struct amdgpu_cs
*acs
)
1002 struct amdgpu_cs_context
*cs
= acs
->csc
;
1004 cs
->request
.number_of_dependencies
= 0;
1006 amdgpu_add_fence_dependencies_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1007 amdgpu_add_fence_dependencies_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1010 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1012 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1013 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1014 struct amdgpu_cs_context
*cs
= acs
->cst
;
1017 cs
->request
.fence_info
.handle
= NULL
;
1018 if (amdgpu_cs_has_user_fence(cs
)) {
1019 cs
->request
.fence_info
.handle
= acs
->ctx
->user_fence_bo
;
1020 cs
->request
.fence_info
.offset
= acs
->ring_type
;
1023 /* Create the buffer list.
1024 * Use a buffer list containing all allocated buffers if requested.
1026 if (debug_get_option_all_bos()) {
1027 struct amdgpu_winsys_bo
*bo
;
1028 amdgpu_bo_handle
*handles
;
1031 mtx_lock(&ws
->global_bo_list_lock
);
1033 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
1035 mtx_unlock(&ws
->global_bo_list_lock
);
1036 amdgpu_cs_context_cleanup(cs
);
1037 cs
->error_code
= -ENOMEM
;
1041 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1042 assert(num
< ws
->num_buffers
);
1043 handles
[num
++] = bo
->bo
;
1046 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1048 &cs
->request
.resources
);
1050 mtx_unlock(&ws
->global_bo_list_lock
);
1052 if (cs
->max_real_submit
< cs
->num_real_buffers
) {
1056 cs
->handles
= MALLOC(sizeof(*cs
->handles
) * cs
->num_real_buffers
);
1057 cs
->flags
= MALLOC(sizeof(*cs
->flags
) * cs
->num_real_buffers
);
1059 if (!cs
->handles
|| !cs
->flags
) {
1060 cs
->max_real_submit
= 0;
1066 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1067 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1069 assert(buffer
->u
.real
.priority_usage
!= 0);
1071 cs
->handles
[i
] = buffer
->bo
->bo
;
1072 cs
->flags
[i
] = (util_last_bit64(buffer
->u
.real
.priority_usage
) - 1) / 4;
1075 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_real_buffers
,
1076 cs
->handles
, cs
->flags
,
1077 &cs
->request
.resources
);
1082 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1083 cs
->request
.resources
= NULL
;
1084 amdgpu_fence_signalled(cs
->fence
);
1089 if (acs
->ctx
->num_rejected_cs
)
1092 r
= amdgpu_cs_submit(acs
->ctx
->ctx
, 0, &cs
->request
, 1);
1097 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1098 else if (r
== -ECANCELED
)
1099 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1101 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1102 "see dmesg for more information (%i).\n", r
);
1104 amdgpu_fence_signalled(cs
->fence
);
1106 acs
->ctx
->num_rejected_cs
++;
1107 ws
->num_total_rejected_cs
++;
1110 uint64_t *user_fence
= NULL
;
1111 if (amdgpu_cs_has_user_fence(cs
))
1112 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+
1113 cs
->request
.fence_info
.offset
;
1114 amdgpu_fence_submitted(cs
->fence
, &cs
->request
, user_fence
);
1118 if (cs
->request
.resources
)
1119 amdgpu_bo_list_destroy(cs
->request
.resources
);
1122 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1123 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1124 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1125 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1127 amdgpu_cs_context_cleanup(cs
);
1130 /* Make sure the previous submission is completed. */
1131 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
1133 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1135 /* Wait for any pending ioctl of this CS to complete. */
1136 util_queue_fence_wait(&cs
->flush_completed
);
1139 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
1141 struct pipe_fence_handle
**fence
)
1143 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1144 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1147 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1149 switch (cs
->ring_type
) {
1151 /* pad DMA ring to 8 DWs */
1152 if (ws
->info
.chip_class
<= SI
) {
1153 while (rcs
->current
.cdw
& 7)
1154 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1156 while (rcs
->current
.cdw
& 7)
1157 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1161 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1162 if (ws
->info
.gfx_ib_pad_with_type2
) {
1163 while (rcs
->current
.cdw
& 7)
1164 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1166 while (rcs
->current
.cdw
& 7)
1167 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1170 /* Also pad the const IB. */
1171 if (cs
->const_ib
.ib_mapped
)
1172 while (!cs
->const_ib
.base
.current
.cdw
|| (cs
->const_ib
.base
.current
.cdw
& 7))
1173 radeon_emit(&cs
->const_ib
.base
, 0xffff1000); /* type3 nop packet */
1175 if (cs
->const_preamble_ib
.ib_mapped
)
1176 while (!cs
->const_preamble_ib
.base
.current
.cdw
|| (cs
->const_preamble_ib
.base
.current
.cdw
& 7))
1177 radeon_emit(&cs
->const_preamble_ib
.base
, 0xffff1000);
1180 while (rcs
->current
.cdw
& 15)
1181 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1187 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1188 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1191 /* If the CS is not empty or overflowed.... */
1192 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1193 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1194 !debug_get_option_noop())) {
1195 struct amdgpu_cs_context
*cur
= cs
->csc
;
1198 amdgpu_ib_finalize(&cs
->main
);
1200 if (cs
->const_ib
.ib_mapped
)
1201 amdgpu_ib_finalize(&cs
->const_ib
);
1203 if (cs
->const_preamble_ib
.ib_mapped
)
1204 amdgpu_ib_finalize(&cs
->const_preamble_ib
);
1206 /* Create a fence. */
1207 amdgpu_fence_reference(&cur
->fence
, NULL
);
1208 if (cs
->next_fence
) {
1209 /* just move the reference */
1210 cur
->fence
= cs
->next_fence
;
1211 cs
->next_fence
= NULL
;
1213 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1214 cur
->request
.ip_type
,
1215 cur
->request
.ip_instance
,
1219 amdgpu_fence_reference(fence
, cur
->fence
);
1221 amdgpu_cs_sync_flush(rcs
);
1225 * This fence must be held until the submission is queued to ensure
1226 * that the order of fence dependency updates matches the order of
1229 mtx_lock(&ws
->bo_fence_lock
);
1230 amdgpu_add_fence_dependencies(cs
);
1232 /* Swap command streams. "cst" is going to be submitted. */
1237 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1238 amdgpu_cs_submit_ib
, NULL
);
1239 /* The submission has been queued, unlock the fence now. */
1240 mtx_unlock(&ws
->bo_fence_lock
);
1242 if (!(flags
& RADEON_FLUSH_ASYNC
)) {
1243 amdgpu_cs_sync_flush(rcs
);
1244 error_code
= cur
->error_code
;
1247 amdgpu_cs_context_cleanup(cs
->csc
);
1250 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1251 if (cs
->const_ib
.ib_mapped
)
1252 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
);
1253 if (cs
->const_preamble_ib
.ib_mapped
)
1254 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
);
1256 cs
->main
.base
.used_gart
= 0;
1257 cs
->main
.base
.used_vram
= 0;
1259 if (cs
->ring_type
== RING_GFX
)
1261 else if (cs
->ring_type
== RING_DMA
)
1267 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1269 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1271 amdgpu_cs_sync_flush(rcs
);
1272 util_queue_fence_destroy(&cs
->flush_completed
);
1273 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1274 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1275 FREE(cs
->main
.base
.prev
);
1276 pb_reference(&cs
->const_ib
.big_ib_buffer
, NULL
);
1277 FREE(cs
->const_ib
.base
.prev
);
1278 pb_reference(&cs
->const_preamble_ib
.big_ib_buffer
, NULL
);
1279 FREE(cs
->const_preamble_ib
.base
.prev
);
1280 amdgpu_destroy_cs_context(&cs
->csc1
);
1281 amdgpu_destroy_cs_context(&cs
->csc2
);
1282 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1286 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1287 struct pb_buffer
*_buf
,
1288 enum radeon_bo_usage usage
)
1290 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1291 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1293 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1296 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1298 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1299 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1300 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1301 ws
->base
.cs_create
= amdgpu_cs_create
;
1302 ws
->base
.cs_add_const_ib
= amdgpu_cs_add_const_ib
;
1303 ws
->base
.cs_add_const_preamble_ib
= amdgpu_cs_add_const_preamble_ib
;
1304 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1305 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1306 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1307 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1308 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1309 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1310 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1311 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1312 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1313 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1314 ws
->base
.fence_reference
= amdgpu_fence_reference
;