2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
34 #include "amd/common/sid.h"
36 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
40 static struct pipe_fence_handle
*
41 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
42 unsigned ip_instance
, unsigned ring
)
44 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
46 fence
->reference
.count
= 1;
49 fence
->fence
.context
= ctx
->ctx
;
50 fence
->fence
.ip_type
= ip_type
;
51 fence
->fence
.ip_instance
= ip_instance
;
52 fence
->fence
.ring
= ring
;
53 util_queue_fence_init(&fence
->submitted
);
54 util_queue_fence_reset(&fence
->submitted
);
55 p_atomic_inc(&ctx
->refcount
);
56 return (struct pipe_fence_handle
*)fence
;
59 static struct pipe_fence_handle
*
60 amdgpu_fence_import_syncobj(struct radeon_winsys
*rws
, int fd
)
62 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
63 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
69 pipe_reference_init(&fence
->reference
, 1);
72 r
= amdgpu_cs_import_syncobj(ws
->dev
, fd
, &fence
->syncobj
);
78 util_queue_fence_init(&fence
->submitted
);
80 assert(amdgpu_fence_is_syncobj(fence
));
81 return (struct pipe_fence_handle
*)fence
;
84 static struct pipe_fence_handle
*
85 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
87 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
88 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
93 pipe_reference_init(&fence
->reference
, 1);
95 /* fence->ctx == NULL means that the fence is syncobj-based. */
97 /* Convert sync_file into syncobj. */
98 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
104 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
106 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
111 util_queue_fence_init(&fence
->submitted
);
113 return (struct pipe_fence_handle
*)fence
;
116 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
117 struct pipe_fence_handle
*pfence
)
119 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
120 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
122 if (amdgpu_fence_is_syncobj(fence
)) {
125 /* Convert syncobj into sync_file. */
126 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
130 util_queue_fence_wait(&fence
->submitted
);
132 /* Convert the amdgpu fence into a fence FD. */
134 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
135 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
142 static int amdgpu_export_signalled_sync_file(struct radeon_winsys
*rws
)
144 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
148 int r
= amdgpu_cs_create_syncobj2(ws
->dev
, DRM_SYNCOBJ_CREATE_SIGNALED
,
154 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, &fd
);
159 amdgpu_cs_destroy_syncobj(ws
->dev
, syncobj
);
163 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
165 uint64_t *user_fence_cpu_address
)
167 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
169 afence
->fence
.fence
= seq_no
;
170 afence
->user_fence_cpu_address
= user_fence_cpu_address
;
171 util_queue_fence_signal(&afence
->submitted
);
174 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
176 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
178 afence
->signalled
= true;
179 util_queue_fence_signal(&afence
->submitted
);
182 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
185 struct amdgpu_fence
*afence
= (struct amdgpu_fence
*)fence
;
188 uint64_t *user_fence_cpu
;
191 if (afence
->signalled
)
194 /* Handle syncobjs. */
195 if (amdgpu_fence_is_syncobj(afence
)) {
196 /* Absolute timeouts are only be used by BO fences, which aren't
197 * backed by syncobjs.
201 if (amdgpu_cs_syncobj_wait(afence
->ws
->dev
, &afence
->syncobj
, 1,
205 afence
->signalled
= true;
210 abs_timeout
= timeout
;
212 abs_timeout
= os_time_get_absolute_timeout(timeout
);
214 /* The fence might not have a number assigned if its IB is being
215 * submitted in the other thread right now. Wait until the submission
217 if (!util_queue_fence_wait_timeout(&afence
->submitted
, abs_timeout
))
220 user_fence_cpu
= afence
->user_fence_cpu_address
;
221 if (user_fence_cpu
) {
222 if (*user_fence_cpu
>= afence
->fence
.fence
) {
223 afence
->signalled
= true;
227 /* No timeout, just query: no need for the ioctl. */
228 if (!absolute
&& !timeout
)
232 /* Now use the libdrm query. */
233 r
= amdgpu_cs_query_fence_status(&afence
->fence
,
235 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
238 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
243 /* This variable can only transition from false to true, so it doesn't
244 * matter if threads race for it. */
245 afence
->signalled
= true;
251 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
252 struct pipe_fence_handle
*fence
,
255 return amdgpu_fence_wait(fence
, timeout
, false);
258 static struct pipe_fence_handle
*
259 amdgpu_cs_get_next_fence(struct radeon_cmdbuf
*rcs
)
261 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
262 struct pipe_fence_handle
*fence
= NULL
;
264 if (debug_get_option_noop())
267 if (cs
->next_fence
) {
268 amdgpu_fence_reference(&fence
, cs
->next_fence
);
272 fence
= amdgpu_fence_create(cs
->ctx
,
273 cs
->csc
->ib
[IB_MAIN
].ip_type
,
274 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
275 cs
->csc
->ib
[IB_MAIN
].ring
);
279 amdgpu_fence_reference(&cs
->next_fence
, fence
);
285 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
287 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
289 struct amdgpu_bo_alloc_request alloc_buffer
= {};
290 amdgpu_bo_handle buf_handle
;
295 ctx
->ws
= amdgpu_winsys(ws
);
297 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
299 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
301 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
305 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
306 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
307 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
309 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
311 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
312 goto error_user_fence_alloc
;
315 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
317 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
318 goto error_user_fence_map
;
321 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
322 ctx
->user_fence_bo
= buf_handle
;
324 return (struct radeon_winsys_ctx
*)ctx
;
326 error_user_fence_map
:
327 amdgpu_bo_free(buf_handle
);
328 error_user_fence_alloc
:
329 amdgpu_cs_ctx_free(ctx
->ctx
);
335 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
337 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
340 static enum pipe_reset_status
341 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
343 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
344 uint32_t result
, hangs
;
347 /* Return a failure due to a rejected command submission. */
348 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
349 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
350 PIPE_INNOCENT_CONTEXT_RESET
;
353 /* Return a failure due to a GPU hang. */
354 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
356 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
357 return PIPE_NO_RESET
;
361 case AMDGPU_CTX_GUILTY_RESET
:
362 return PIPE_GUILTY_CONTEXT_RESET
;
363 case AMDGPU_CTX_INNOCENT_RESET
:
364 return PIPE_INNOCENT_CONTEXT_RESET
;
365 case AMDGPU_CTX_UNKNOWN_RESET
:
366 return PIPE_UNKNOWN_CONTEXT_RESET
;
367 case AMDGPU_CTX_NO_RESET
:
369 return PIPE_NO_RESET
;
373 /* COMMAND SUBMISSION */
375 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
377 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
378 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
379 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD_ENC
&&
380 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
&&
381 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_ENC
;
384 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
386 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
387 cs
->ring_type
== RING_GFX
;
390 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
392 if (ring_type
== RING_GFX
)
393 return 4; /* for chaining */
398 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
400 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
401 int i
= cs
->buffer_indices_hashlist
[hash
];
402 struct amdgpu_cs_buffer
*buffers
;
406 buffers
= cs
->real_buffers
;
407 num_buffers
= cs
->num_real_buffers
;
408 } else if (!bo
->sparse
) {
409 buffers
= cs
->slab_buffers
;
410 num_buffers
= cs
->num_slab_buffers
;
412 buffers
= cs
->sparse_buffers
;
413 num_buffers
= cs
->num_sparse_buffers
;
416 /* not found or found */
417 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
420 /* Hash collision, look for the BO in the list of buffers linearly. */
421 for (i
= num_buffers
- 1; i
>= 0; i
--) {
422 if (buffers
[i
].bo
== bo
) {
423 /* Put this buffer in the hash list.
424 * This will prevent additional hash collisions if there are
425 * several consecutive lookup_buffer calls for the same buffer.
427 * Example: Assuming buffers A,B,C collide in the hash list,
428 * the following sequence of buffers:
429 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
430 * will collide here: ^ and here: ^,
431 * meaning that we should get very few collisions in the end. */
432 cs
->buffer_indices_hashlist
[hash
] = i
;
440 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
442 struct amdgpu_cs_buffer
*buffer
;
445 /* New buffer, check if the backing array is large enough. */
446 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
448 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
449 struct amdgpu_cs_buffer
*new_buffers
;
451 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
454 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
459 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
461 FREE(cs
->real_buffers
);
463 cs
->max_real_buffers
= new_max
;
464 cs
->real_buffers
= new_buffers
;
467 idx
= cs
->num_real_buffers
;
468 buffer
= &cs
->real_buffers
[idx
];
470 memset(buffer
, 0, sizeof(*buffer
));
471 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
472 p_atomic_inc(&bo
->num_cs_references
);
473 cs
->num_real_buffers
++;
479 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
481 struct amdgpu_cs_context
*cs
= acs
->csc
;
483 int idx
= amdgpu_lookup_buffer(cs
, bo
);
488 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
490 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
491 cs
->buffer_indices_hashlist
[hash
] = idx
;
493 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
494 acs
->main
.base
.used_vram
+= bo
->base
.size
;
495 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
496 acs
->main
.base
.used_gart
+= bo
->base
.size
;
501 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
502 struct amdgpu_winsys_bo
*bo
)
504 struct amdgpu_cs_context
*cs
= acs
->csc
;
505 struct amdgpu_cs_buffer
*buffer
;
507 int idx
= amdgpu_lookup_buffer(cs
, bo
);
513 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
517 /* New buffer, check if the backing array is large enough. */
518 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
520 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
521 struct amdgpu_cs_buffer
*new_buffers
;
523 new_buffers
= REALLOC(cs
->slab_buffers
,
524 cs
->max_slab_buffers
* sizeof(*new_buffers
),
525 new_max
* sizeof(*new_buffers
));
527 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
531 cs
->max_slab_buffers
= new_max
;
532 cs
->slab_buffers
= new_buffers
;
535 idx
= cs
->num_slab_buffers
;
536 buffer
= &cs
->slab_buffers
[idx
];
538 memset(buffer
, 0, sizeof(*buffer
));
539 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
540 buffer
->u
.slab
.real_idx
= real_idx
;
541 p_atomic_inc(&bo
->num_cs_references
);
542 cs
->num_slab_buffers
++;
544 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
545 cs
->buffer_indices_hashlist
[hash
] = idx
;
550 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
551 struct amdgpu_winsys_bo
*bo
)
553 struct amdgpu_cs_context
*cs
= acs
->csc
;
554 struct amdgpu_cs_buffer
*buffer
;
556 int idx
= amdgpu_lookup_buffer(cs
, bo
);
561 /* New buffer, check if the backing array is large enough. */
562 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
564 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
565 struct amdgpu_cs_buffer
*new_buffers
;
567 new_buffers
= REALLOC(cs
->sparse_buffers
,
568 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
569 new_max
* sizeof(*new_buffers
));
571 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
575 cs
->max_sparse_buffers
= new_max
;
576 cs
->sparse_buffers
= new_buffers
;
579 idx
= cs
->num_sparse_buffers
;
580 buffer
= &cs
->sparse_buffers
[idx
];
582 memset(buffer
, 0, sizeof(*buffer
));
583 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
584 p_atomic_inc(&bo
->num_cs_references
);
585 cs
->num_sparse_buffers
++;
587 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
588 cs
->buffer_indices_hashlist
[hash
] = idx
;
590 /* We delay adding the backing buffers until we really have to. However,
591 * we cannot delay accounting for memory use.
593 simple_mtx_lock(&bo
->lock
);
595 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
596 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
597 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
598 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
599 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
602 simple_mtx_unlock(&bo
->lock
);
607 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf
*rcs
,
608 struct pb_buffer
*buf
,
609 enum radeon_bo_usage usage
,
610 enum radeon_bo_domain domains
,
611 enum radeon_bo_priority priority
)
613 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
614 * the buffer placement during command submission.
616 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
617 struct amdgpu_cs_context
*cs
= acs
->csc
;
618 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
619 struct amdgpu_cs_buffer
*buffer
;
622 /* Fast exit for no-op calls.
623 * This is very effective with suballocators and linear uploaders that
624 * are outside of the winsys.
626 if (bo
== cs
->last_added_bo
&&
627 (usage
& cs
->last_added_bo_usage
) == usage
&&
628 (1u << priority
) & cs
->last_added_bo_priority_usage
)
629 return cs
->last_added_bo_index
;
633 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
637 buffer
= &cs
->slab_buffers
[index
];
638 buffer
->usage
|= usage
;
640 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
641 index
= buffer
->u
.slab
.real_idx
;
643 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
648 buffer
= &cs
->real_buffers
[index
];
650 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
654 buffer
= &cs
->sparse_buffers
[index
];
657 buffer
->u
.real
.priority_usage
|= 1u << priority
;
658 buffer
->usage
|= usage
;
660 cs
->last_added_bo
= bo
;
661 cs
->last_added_bo_index
= index
;
662 cs
->last_added_bo_usage
= buffer
->usage
;
663 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
667 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
,
668 enum ring_type ring_type
)
670 struct pb_buffer
*pb
;
672 unsigned buffer_size
;
674 /* Always create a buffer that is at least as large as the maximum seen IB
675 * size, aligned to a power of two (and multiplied by 4 to reduce internal
676 * fragmentation if chaining is not available). Limit to 512k dwords, which
677 * is the largest power of two that fits into the size field of the
678 * INDIRECT_BUFFER packet.
680 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
681 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
683 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
685 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
687 switch (ib
->ib_type
) {
689 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
692 unreachable("unhandled IB type");
695 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
696 ws
->info
.gart_page_size
,
698 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
699 (ring_type
== RING_GFX
||
700 ring_type
== RING_COMPUTE
||
701 ring_type
== RING_DMA
?
702 RADEON_FLAG_READ_ONLY
| RADEON_FLAG_GTT_WC
: 0));
706 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
708 pb_reference(&pb
, NULL
);
712 pb_reference(&ib
->big_ib_buffer
, pb
);
713 pb_reference(&pb
, NULL
);
715 ib
->ib_mapped
= mapped
;
716 ib
->used_ib_space
= 0;
721 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
725 /* Smaller submits means the GPU gets busy sooner and there is less
726 * waiting for buffers and fences. Proof:
727 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
731 unreachable("bad ib_type");
735 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
736 enum ib_type ib_type
)
738 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
739 /* Small IBs are better than big IBs, because the GPU goes idle quicker
740 * and there is less waiting for buffers and fences. Proof:
741 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
743 struct amdgpu_ib
*ib
= NULL
;
744 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
745 unsigned ib_size
= 0;
750 ib_size
= 4 * 1024 * 4;
753 unreachable("unhandled IB type");
756 if (!amdgpu_cs_has_chaining(cs
)) {
757 ib_size
= MAX2(ib_size
,
758 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
759 amdgpu_ib_max_submit_dwords(ib_type
)));
762 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
764 ib
->base
.prev_dw
= 0;
765 ib
->base
.num_prev
= 0;
766 ib
->base
.current
.cdw
= 0;
767 ib
->base
.current
.buf
= NULL
;
769 /* Allocate a new buffer for IBs if the current buffer is all used. */
770 if (!ib
->big_ib_buffer
||
771 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
772 if (!amdgpu_ib_new_buffer(aws
, ib
, cs
->ring_type
))
776 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
778 /* ib_bytes is in dwords and the conversion to bytes will be done before
780 ib
->ptr_ib_size
= &info
->ib_bytes
;
781 ib
->ptr_ib_size_inside_ib
= false;
783 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
784 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
786 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
788 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
789 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
793 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
795 if (ib
->ptr_ib_size_inside_ib
) {
796 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
797 S_3F2_CHAIN(1) | S_3F2_VALID(1);
799 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
803 static void amdgpu_ib_finalize(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
805 amdgpu_set_ib_size(ib
);
806 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
807 ib
->used_ib_space
= align(ib
->used_ib_space
, ws
->info
.ib_start_alignment
);
808 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
811 static bool amdgpu_init_cs_context(struct amdgpu_winsys
*ws
,
812 struct amdgpu_cs_context
*cs
,
813 enum ring_type ring_type
)
817 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
821 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
825 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD_ENC
;
829 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
833 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
837 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_ENC
;
841 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_JPEG
;
846 cs
->ib
[IB_MAIN
].ip_type
= ring_type
== RING_GFX
? AMDGPU_HW_IP_GFX
:
847 AMDGPU_HW_IP_COMPUTE
;
849 /* The kernel shouldn't invalidate L2 and vL1. The proper place for cache
850 * invalidation is the beginning of IBs (the previous commit does that),
851 * because completion of an IB doesn't care about the state of GPU caches,
852 * but the beginning of an IB does. Draw calls from multiple IBs can be
853 * executed in parallel, so draw calls from the current IB can finish after
854 * the next IB starts drawing, and so the cache flush at the end of IB
857 if (ws
->info
.drm_minor
>= 26)
858 cs
->ib
[IB_MAIN
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
865 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
866 cs
->last_added_bo
= NULL
;
870 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
874 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
875 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
876 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
878 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
879 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
880 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
882 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
883 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
884 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
886 for (i
= 0; i
< cs
->num_fence_dependencies
; i
++)
887 amdgpu_fence_reference(&cs
->fence_dependencies
[i
], NULL
);
888 for (i
= 0; i
< cs
->num_syncobj_to_signal
; i
++)
889 amdgpu_fence_reference(&cs
->syncobj_to_signal
[i
], NULL
);
891 cs
->num_real_buffers
= 0;
892 cs
->num_slab_buffers
= 0;
893 cs
->num_sparse_buffers
= 0;
894 cs
->num_fence_dependencies
= 0;
895 cs
->num_syncobj_to_signal
= 0;
896 amdgpu_fence_reference(&cs
->fence
, NULL
);
898 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
899 cs
->last_added_bo
= NULL
;
902 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
904 amdgpu_cs_context_cleanup(cs
);
905 FREE(cs
->real_buffers
);
906 FREE(cs
->slab_buffers
);
907 FREE(cs
->sparse_buffers
);
908 FREE(cs
->fence_dependencies
);
909 FREE(cs
->syncobj_to_signal
);
913 static struct radeon_cmdbuf
*
914 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
915 enum ring_type ring_type
,
916 void (*flush
)(void *ctx
, unsigned flags
,
917 struct pipe_fence_handle
**fence
),
919 bool stop_exec_on_failure
)
921 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
922 struct amdgpu_cs
*cs
;
924 cs
= CALLOC_STRUCT(amdgpu_cs
);
929 util_queue_fence_init(&cs
->flush_completed
);
932 cs
->flush_cs
= flush
;
933 cs
->flush_data
= flush_ctx
;
934 cs
->ring_type
= ring_type
;
935 cs
->stop_exec_on_failure
= stop_exec_on_failure
;
937 struct amdgpu_cs_fence_info fence_info
;
938 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
939 fence_info
.offset
= cs
->ring_type
;
940 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
942 cs
->main
.ib_type
= IB_MAIN
;
944 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc1
, ring_type
)) {
949 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc2
, ring_type
)) {
950 amdgpu_destroy_cs_context(&cs
->csc1
);
955 /* Set the first submission context as current. */
959 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
960 amdgpu_destroy_cs_context(&cs
->csc2
);
961 amdgpu_destroy_cs_context(&cs
->csc1
);
966 p_atomic_inc(&ctx
->ws
->num_cs
);
967 return &cs
->main
.base
;
970 static bool amdgpu_cs_validate(struct radeon_cmdbuf
*rcs
)
975 static bool amdgpu_cs_check_space(struct radeon_cmdbuf
*rcs
, unsigned dw
)
977 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
978 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
979 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
981 uint32_t *new_ptr_ib_size
;
983 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
985 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
988 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
990 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
993 if (!amdgpu_cs_has_chaining(cs
))
996 /* Allocate a new chunk */
997 if (rcs
->num_prev
>= rcs
->max_prev
) {
998 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
999 struct radeon_cmdbuf_chunk
*new_prev
;
1001 new_prev
= REALLOC(rcs
->prev
,
1002 sizeof(*new_prev
) * rcs
->max_prev
,
1003 sizeof(*new_prev
) * new_max_prev
);
1007 rcs
->prev
= new_prev
;
1008 rcs
->max_prev
= new_max_prev
;
1011 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
1014 assert(ib
->used_ib_space
== 0);
1015 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
1017 /* This space was originally reserved. */
1018 rcs
->current
.max_dw
+= 4;
1019 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
1021 /* Pad with NOPs and add INDIRECT_BUFFER packet */
1022 while ((rcs
->current
.cdw
& 7) != 4)
1023 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1025 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
1026 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
1027 radeon_emit(rcs
, va
);
1028 radeon_emit(rcs
, va
>> 32);
1029 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
1031 assert((rcs
->current
.cdw
& 7) == 0);
1032 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1034 amdgpu_set_ib_size(ib
);
1035 ib
->ptr_ib_size
= new_ptr_ib_size
;
1036 ib
->ptr_ib_size_inside_ib
= true;
1038 /* Hook up the new chunk */
1039 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
1040 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
1041 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
1044 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
1045 ib
->base
.current
.cdw
= 0;
1047 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
1048 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
1050 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
1051 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
1056 static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf
*rcs
,
1057 struct radeon_bo_list_item
*list
)
1059 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
1063 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
1064 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
1065 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
1066 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
1069 return cs
->num_real_buffers
;
1072 static unsigned add_fence_dependency_entry(struct amdgpu_cs_context
*cs
)
1074 unsigned idx
= cs
->num_fence_dependencies
++;
1076 if (idx
>= cs
->max_fence_dependencies
) {
1078 const unsigned increment
= 8;
1080 cs
->max_fence_dependencies
= idx
+ increment
;
1081 size
= cs
->max_fence_dependencies
* sizeof(cs
->fence_dependencies
[0]);
1082 cs
->fence_dependencies
= realloc(cs
->fence_dependencies
, size
);
1083 /* Clear the newly-allocated elements. */
1084 memset(cs
->fence_dependencies
+ idx
, 0,
1085 increment
* sizeof(cs
->fence_dependencies
[0]));
1090 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1091 struct amdgpu_fence
*fence
)
1093 struct amdgpu_cs_context
*cs
= acs
->csc
;
1095 if (!amdgpu_fence_is_syncobj(fence
) &&
1096 fence
->ctx
== acs
->ctx
&&
1097 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1098 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1099 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1102 return amdgpu_fence_wait((void *)fence
, 0, false);
1105 static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf
*rws
,
1106 struct pipe_fence_handle
*pfence
)
1108 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1109 struct amdgpu_cs_context
*cs
= acs
->csc
;
1110 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1112 util_queue_fence_wait(&fence
->submitted
);
1114 if (is_noop_fence_dependency(acs
, fence
))
1117 unsigned idx
= add_fence_dependency_entry(cs
);
1118 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1119 (struct pipe_fence_handle
*)fence
);
1122 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1123 struct amdgpu_cs_buffer
*buffer
)
1125 struct amdgpu_cs_context
*cs
= acs
->csc
;
1126 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1127 unsigned new_num_fences
= 0;
1129 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1130 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1132 if (is_noop_fence_dependency(acs
, bo_fence
))
1135 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1138 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1141 unsigned idx
= add_fence_dependency_entry(cs
);
1142 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1143 (struct pipe_fence_handle
*)bo_fence
);
1146 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1147 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1149 bo
->num_fences
= new_num_fences
;
1152 /* Add the given list of fences to the buffer's fence list.
1154 * Must be called with the winsys bo_fence_lock held.
1156 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1157 unsigned num_fences
,
1158 struct pipe_fence_handle
**fences
)
1160 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1161 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1162 struct pipe_fence_handle
**new_fences
=
1164 bo
->num_fences
* sizeof(*new_fences
),
1165 new_max_fences
* sizeof(*new_fences
));
1166 if (likely(new_fences
)) {
1167 bo
->fences
= new_fences
;
1168 bo
->max_fences
= new_max_fences
;
1172 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1173 if (!bo
->num_fences
)
1176 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1177 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1179 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1185 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1186 bo
->fences
[bo
->num_fences
] = NULL
;
1187 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1192 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1193 struct pipe_fence_handle
*fence
,
1194 unsigned num_buffers
,
1195 struct amdgpu_cs_buffer
*buffers
)
1197 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1198 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1199 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1201 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1202 p_atomic_inc(&bo
->num_active_ioctls
);
1203 amdgpu_add_fences(bo
, 1, &fence
);
1207 /* Since the kernel driver doesn't synchronize execution between different
1208 * rings automatically, we have to add fence dependencies manually.
1210 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1212 struct amdgpu_cs_context
*cs
= acs
->csc
;
1214 cs
->num_fence_dependencies
= 0;
1216 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1217 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1218 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1221 static unsigned add_syncobj_to_signal_entry(struct amdgpu_cs_context
*cs
)
1223 unsigned idx
= cs
->num_syncobj_to_signal
++;
1225 if (idx
>= cs
->max_syncobj_to_signal
) {
1227 const unsigned increment
= 8;
1229 cs
->max_syncobj_to_signal
= idx
+ increment
;
1230 size
= cs
->max_syncobj_to_signal
* sizeof(cs
->syncobj_to_signal
[0]);
1231 cs
->syncobj_to_signal
= realloc(cs
->syncobj_to_signal
, size
);
1232 /* Clear the newly-allocated elements. */
1233 memset(cs
->syncobj_to_signal
+ idx
, 0,
1234 increment
* sizeof(cs
->syncobj_to_signal
[0]));
1239 static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf
*rws
,
1240 struct pipe_fence_handle
*fence
)
1242 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1243 struct amdgpu_cs_context
*cs
= acs
->csc
;
1245 assert(amdgpu_fence_is_syncobj((struct amdgpu_fence
*)fence
));
1247 unsigned idx
= add_syncobj_to_signal_entry(cs
);
1248 amdgpu_fence_reference(&cs
->syncobj_to_signal
[idx
], fence
);
1251 /* Add backing of sparse buffers to the buffer list.
1253 * This is done late, during submission, to keep the buffer list short before
1254 * submit, and to avoid managing fences for the backing buffers.
1256 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1258 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1259 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1260 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1262 simple_mtx_lock(&bo
->lock
);
1264 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1265 /* We can directly add the buffer here, because we know that each
1266 * backing buffer occurs only once.
1268 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1270 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1271 simple_mtx_unlock(&bo
->lock
);
1275 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1276 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1277 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1280 simple_mtx_unlock(&bo
->lock
);
1286 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1288 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1289 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1290 struct amdgpu_cs_context
*cs
= acs
->cst
;
1292 uint32_t bo_list
= 0;
1293 uint64_t seq_no
= 0;
1294 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1295 bool use_bo_list_create
= ws
->info
.drm_minor
< 27;
1296 struct drm_amdgpu_bo_list_in bo_list_in
;
1298 /* Prepare the buffer list. */
1299 if (ws
->debug_all_bos
) {
1300 /* The buffer list contains all buffers. This is a slow path that
1301 * ensures that no buffer is missing in the BO list.
1303 unsigned num_handles
= 0;
1304 struct drm_amdgpu_bo_list_entry
*list
=
1305 alloca(ws
->num_buffers
* sizeof(struct drm_amdgpu_bo_list_entry
));
1306 struct amdgpu_winsys_bo
*bo
;
1308 simple_mtx_lock(&ws
->global_bo_list_lock
);
1309 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1313 list
[num_handles
].bo_handle
= bo
->u
.real
.kms_handle
;
1314 list
[num_handles
].bo_priority
= 0;
1318 r
= amdgpu_bo_list_create_raw(ws
->dev
, ws
->num_buffers
, list
, &bo_list
);
1319 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1321 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1325 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1326 fprintf(stderr
, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n");
1331 struct drm_amdgpu_bo_list_entry
*list
=
1332 alloca(cs
->num_real_buffers
* sizeof(struct drm_amdgpu_bo_list_entry
));
1334 unsigned num_handles
= 0;
1335 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1336 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1338 if (buffer
->bo
->is_local
)
1341 assert(buffer
->u
.real
.priority_usage
!= 0);
1343 list
[num_handles
].bo_handle
= buffer
->bo
->u
.real
.kms_handle
;
1344 list
[num_handles
].bo_priority
= (util_last_bit(buffer
->u
.real
.priority_usage
) - 1) / 2;
1348 if (use_bo_list_create
) {
1349 /* Legacy path creating the buffer list handle and passing it to the CS ioctl. */
1350 r
= amdgpu_bo_list_create_raw(ws
->dev
, num_handles
, list
, &bo_list
);
1352 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1356 /* Standard path passing the buffer list via the CS ioctl. */
1357 bo_list_in
.operation
= ~0;
1358 bo_list_in
.list_handle
= ~0;
1359 bo_list_in
.bo_number
= num_handles
;
1360 bo_list_in
.bo_info_size
= sizeof(struct drm_amdgpu_bo_list_entry
);
1361 bo_list_in
.bo_info_ptr
= (uint64_t)(uintptr_t)list
;
1365 if (acs
->ring_type
== RING_GFX
)
1366 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1368 if (acs
->stop_exec_on_failure
&& acs
->ctx
->num_rejected_cs
) {
1371 struct drm_amdgpu_cs_chunk chunks
[6];
1372 unsigned num_chunks
= 0;
1374 /* Convert from dwords to bytes. */
1375 cs
->ib
[IB_MAIN
].ib_bytes
*= 4;
1378 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1379 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1380 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1384 if (has_user_fence
) {
1385 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1386 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1387 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1392 unsigned num_dependencies
= cs
->num_fence_dependencies
;
1393 unsigned num_syncobj_dependencies
= 0;
1395 if (num_dependencies
) {
1396 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1397 alloca(num_dependencies
* sizeof(*dep_chunk
));
1400 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1401 struct amdgpu_fence
*fence
=
1402 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1404 if (amdgpu_fence_is_syncobj(fence
)) {
1405 num_syncobj_dependencies
++;
1409 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1410 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[num
++]);
1413 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1414 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num
;
1415 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1419 /* Syncobj dependencies. */
1420 if (num_syncobj_dependencies
) {
1421 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1422 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1425 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1426 struct amdgpu_fence
*fence
=
1427 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1429 if (!amdgpu_fence_is_syncobj(fence
))
1432 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1433 sem_chunk
[num
++].handle
= fence
->syncobj
;
1436 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1437 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num
;
1438 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1442 /* Syncobj sygnals. */
1443 if (cs
->num_syncobj_to_signal
) {
1444 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1445 alloca(cs
->num_syncobj_to_signal
* sizeof(sem_chunk
[0]));
1447 for (unsigned i
= 0; i
< cs
->num_syncobj_to_signal
; i
++) {
1448 struct amdgpu_fence
*fence
=
1449 (struct amdgpu_fence
*)cs
->syncobj_to_signal
[i
];
1451 assert(amdgpu_fence_is_syncobj(fence
));
1452 sem_chunk
[i
].handle
= fence
->syncobj
;
1455 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_OUT
;
1456 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4
1457 * cs
->num_syncobj_to_signal
;
1458 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1463 if (!use_bo_list_create
) {
1464 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_BO_HANDLES
;
1465 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_bo_list_in
) / 4;
1466 chunks
[num_chunks
].chunk_data
= (uintptr_t)&bo_list_in
;
1470 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1472 r
= amdgpu_cs_submit_raw2(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1473 num_chunks
, chunks
, &seq_no
);
1478 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1479 else if (r
== -ECANCELED
)
1480 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1482 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1483 "see dmesg for more information (%i).\n", r
);
1485 acs
->ctx
->num_rejected_cs
++;
1486 ws
->num_total_rejected_cs
++;
1489 uint64_t *user_fence
= NULL
;
1492 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1493 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1498 amdgpu_bo_list_destroy_raw(ws
->dev
, bo_list
);
1501 /* If there was an error, signal the fence, because it won't be signalled
1502 * by the hardware. */
1504 amdgpu_fence_signalled(cs
->fence
);
1508 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1509 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1510 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1511 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1512 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1513 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1515 amdgpu_cs_context_cleanup(cs
);
1518 /* Make sure the previous submission is completed. */
1519 void amdgpu_cs_sync_flush(struct radeon_cmdbuf
*rcs
)
1521 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1523 /* Wait for any pending ioctl of this CS to complete. */
1524 util_queue_fence_wait(&cs
->flush_completed
);
1527 static int amdgpu_cs_flush(struct radeon_cmdbuf
*rcs
,
1529 struct pipe_fence_handle
**fence
)
1531 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1532 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1535 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1537 switch (cs
->ring_type
) {
1539 /* pad DMA ring to 8 DWs */
1540 if (ws
->info
.chip_class
<= SI
) {
1541 while (rcs
->current
.cdw
& 7)
1542 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1544 while (rcs
->current
.cdw
& 7)
1545 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1550 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1551 if (ws
->info
.gfx_ib_pad_with_type2
) {
1552 while (rcs
->current
.cdw
& 7)
1553 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1555 while (rcs
->current
.cdw
& 7)
1556 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1558 if (cs
->ring_type
== RING_GFX
)
1559 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1563 while (rcs
->current
.cdw
& 15)
1564 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1567 if (rcs
->current
.cdw
% 2)
1569 while (rcs
->current
.cdw
& 15) {
1570 radeon_emit(rcs
, 0x60000000); /* nop packet */
1571 radeon_emit(rcs
, 0x00000000);
1575 while (rcs
->current
.cdw
& 15)
1576 radeon_emit(rcs
, 0x81ff); /* nop packet */
1582 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1583 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1586 /* If the CS is not empty or overflowed.... */
1587 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1588 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1589 !debug_get_option_noop())) {
1590 struct amdgpu_cs_context
*cur
= cs
->csc
;
1593 amdgpu_ib_finalize(ws
, &cs
->main
);
1595 /* Create a fence. */
1596 amdgpu_fence_reference(&cur
->fence
, NULL
);
1597 if (cs
->next_fence
) {
1598 /* just move the reference */
1599 cur
->fence
= cs
->next_fence
;
1600 cs
->next_fence
= NULL
;
1602 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1603 cur
->ib
[IB_MAIN
].ip_type
,
1604 cur
->ib
[IB_MAIN
].ip_instance
,
1605 cur
->ib
[IB_MAIN
].ring
);
1608 amdgpu_fence_reference(fence
, cur
->fence
);
1610 amdgpu_cs_sync_flush(rcs
);
1614 * This fence must be held until the submission is queued to ensure
1615 * that the order of fence dependency updates matches the order of
1618 simple_mtx_lock(&ws
->bo_fence_lock
);
1619 amdgpu_add_fence_dependencies_bo_lists(cs
);
1621 /* Swap command streams. "cst" is going to be submitted. */
1626 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1627 amdgpu_cs_submit_ib
, NULL
);
1628 /* The submission has been queued, unlock the fence now. */
1629 simple_mtx_unlock(&ws
->bo_fence_lock
);
1631 if (!(flags
& PIPE_FLUSH_ASYNC
)) {
1632 amdgpu_cs_sync_flush(rcs
);
1633 error_code
= cur
->error_code
;
1636 amdgpu_cs_context_cleanup(cs
->csc
);
1639 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1641 cs
->main
.base
.used_gart
= 0;
1642 cs
->main
.base
.used_vram
= 0;
1644 if (cs
->ring_type
== RING_GFX
)
1646 else if (cs
->ring_type
== RING_DMA
)
1652 static void amdgpu_cs_destroy(struct radeon_cmdbuf
*rcs
)
1654 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1656 amdgpu_cs_sync_flush(rcs
);
1657 util_queue_fence_destroy(&cs
->flush_completed
);
1658 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1659 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1660 FREE(cs
->main
.base
.prev
);
1661 amdgpu_destroy_cs_context(&cs
->csc1
);
1662 amdgpu_destroy_cs_context(&cs
->csc2
);
1663 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1667 static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf
*rcs
,
1668 struct pb_buffer
*_buf
,
1669 enum radeon_bo_usage usage
)
1671 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1672 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1674 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1677 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1679 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1680 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1681 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1682 ws
->base
.cs_create
= amdgpu_cs_create
;
1683 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1684 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1685 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1686 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1687 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1688 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1689 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1690 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1691 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1692 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1693 ws
->base
.cs_add_syncobj_signal
= amdgpu_cs_add_syncobj_signal
;
1694 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1695 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1696 ws
->base
.fence_import_syncobj
= amdgpu_fence_import_syncobj
;
1697 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1698 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;
1699 ws
->base
.export_signalled_sync_file
= amdgpu_export_signalled_sync_file
;