34ea2a6bacb7708c5a88ef3d660b89fd30cf072a
[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <pipe/p_compiler.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include <pipebuffer/pb_bufmgr.h>
35 #include "xf86drm.h"
36 #include "radeon_drm.h"
37 #include "r600_priv.h"
38 #include "bof.h"
39 #include "r600d.h"
40
41 #define GROUP_FORCE_NEW_BLOCK 0
42
43 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
44 {
45 for (int i = 0; i < ctx->creloc; i++) {
46 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
47 LIST_DELINIT(&ctx->bo[i]->fencedlist);
48 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
49 ctx->bo[i]->fence = ctx->radeon->fence;
50 ctx->bo[i]->ctx = ctx;
51 }
52 }
53
54 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
55 {
56 struct radeon_bo *bo = NULL;
57 struct radeon_bo *tmp;
58
59 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
60 if (bo->fence <= *ctx->radeon->cfence) {
61 LIST_DELINIT(&bo->fencedlist);
62 bo->fence = 0;
63 } else {
64 bo->fence = fence;
65 }
66 }
67 }
68
69 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
70 {
71 struct r600_block *block;
72 struct r600_range *range;
73 int offset;
74
75 for (unsigned i = 0, n = 0; i < nreg; i += n) {
76 u32 j;
77
78 /* ignore new block balise */
79 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
80 n = 1;
81 continue;
82 }
83
84 /* register that need relocation are in their own group */
85 /* find number of consecutive registers */
86 n = 0;
87 offset = reg[i].offset;
88 while (reg[i + n].offset == offset) {
89 n++;
90 offset += 4;
91 if ((n + i) >= nreg)
92 break;
93 if (n >= (R600_BLOCK_MAX_REG - 2))
94 break;
95 }
96
97 /* allocate new block */
98 block = calloc(1, sizeof(struct r600_block));
99 if (block == NULL) {
100 return -ENOMEM;
101 }
102 ctx->nblocks++;
103 for (int j = 0; j < n; j++) {
104 range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)];
105 range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block;
106 }
107
108 /* initialize block */
109 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
110 block->start_offset = reg[i].offset;
111 block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n, 0);
112 block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2;
113 block->reg = &block->pm4[block->pm4_ndwords];
114 block->pm4_ndwords += n;
115 block->nreg = n;
116 block->nreg_dirty = n;
117 block->flags = 0;
118 LIST_INITHEAD(&block->list);
119
120 for (j = 0; j < n; j++) {
121 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
122 block->flags |= REG_FLAG_DIRTY_ALWAYS;
123 }
124 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
125 block->nbo++;
126 assert(block->nbo < R600_BLOCK_MAX_BO);
127 block->pm4_bo_index[j] = block->nbo;
128 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
129 block->pm4[block->pm4_ndwords++] = 0x00000000;
130 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
131 block->reloc[block->nbo].flush_flags = 0;
132 block->reloc[block->nbo].flush_mask = 0;
133 } else {
134 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
135 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
136 }
137 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
138 }
139 if ((ctx->radeon->family > CHIP_R600) &&
140 (ctx->radeon->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
141 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
142 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
143 }
144 }
145 for (j = 0; j < n; j++) {
146 if (reg[i+j].flush_flags) {
147 block->pm4_flush_ndwords += 7;
148 }
149 }
150 /* check that we stay in limit */
151 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
152 }
153 return 0;
154 }
155
156 /* R600/R700 configuration */
157 static const struct r600_reg r600_config_reg_list[] = {
158 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
159 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0},
160 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
161 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
162 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
163 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
164 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
165 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
166 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0},
167 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0},
168 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0},
169 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0},
170 };
171
172 static const struct r600_reg r600_ctl_const_list[] = {
173 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
174 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
175 };
176
177 static const struct r600_reg r600_context_reg_list[] = {
178 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0},
179 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
180 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
181 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
182 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
183 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
184 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
185 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
186 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
187 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
188 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
189 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
190 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0},
191 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
192 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
193 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
194 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
195 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
196 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
197 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
198 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
199 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
200 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
201 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0},
202 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
203 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
204 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
205 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
206 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
207 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
208 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
209 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
210 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
211 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
212 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
213 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0},
214 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0},
215 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
216 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
217 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
218 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
219 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0},
220 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
221 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
222 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
223 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
224 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0},
225 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0},
226 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
227 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
228 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
229 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
230 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0},
231 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
232 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
233 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
234 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
235 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0},
236 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0},
237 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
238 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
239 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
240 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
241 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0},
242 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
243 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
244 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
245 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
246 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
247 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
248 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
249 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
250 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
251 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
252 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0},
253 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
254 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
255 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
256 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
257 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0},
258 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0},
259 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
260 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
261 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
262 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
263 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0},
264 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
265 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
266 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
267 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
268 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0},
269 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0},
270 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
271 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
272 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
273 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
274 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0},
275 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
276 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
277 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0},
278 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0},
279 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
280 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
281 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
282 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
283 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0},
284 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
285 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
286 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
287 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
288 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
289 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
290 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
291 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
292 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0},
293 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0},
294 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0},
295 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0},
296 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
297 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
298 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
299 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
300 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
301 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0},
302 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0},
303 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
304 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0},
305 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0},
306 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0},
307 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0},
308 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0},
309 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0},
310 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0},
311 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0},
312 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
313 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0},
314 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
315 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
316 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
317 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
318 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
319 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
320 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
321 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
322 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
323 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
324 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
325 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
326 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
327 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0},
328 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0},
329 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
330 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
331 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
332 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
333 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
334 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
335 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0},
336 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
337 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0},
338 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
339 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
340 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
341 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0},
342 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0},
343 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
344 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
345 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
346 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
347 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
348 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
349 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
350 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
351 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
352 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
353 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
354 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
355 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
356 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
357 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
358 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
359 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
360 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
361 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
362 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
363 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
364 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0},
365 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
366 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
367 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
368 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
369 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
370 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
371 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
372 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
373 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
374 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
375 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
376 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
377 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
378 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
379 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
380 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
381 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
382 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
383 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
384 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
385 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
386 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
387 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
388 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
389 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
390 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
391 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
392 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
393 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
394 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
395 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
396 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
397 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
398 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
399 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
400 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0},
401 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
402 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
403 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
404 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0},
405 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
406 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
407 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
408 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0},
409 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
410 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
411 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
412 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0},
413 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
414 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
415 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
416 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0},
417 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
418 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
419 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
420 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0},
421 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
422 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
423 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
424 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
425 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
426 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
427 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
428 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
429 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
430 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
431 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
432 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
433 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
434 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
435 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
436 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
437 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
438 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
439 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
440 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
441 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
442 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
443 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
444 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
445 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
446 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
447 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
448 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
449 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
450 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
451 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
452 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
453 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
454 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
455 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
456 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
457 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
458 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
459 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
460 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
461 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
462 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
463 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
464 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
465 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
466 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
467 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
468 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
469 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
470 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
471 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
472 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
473 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
474 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
475 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
476 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
477 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
478 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
479 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
480 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
481 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
482 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
483 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
484 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
485 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
486 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
487 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
488 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
489 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
490 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
491 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
492 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
493 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
494 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
495 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
496 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
497 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
498 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
499 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
500 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
501 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
502 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
503 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
504 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
505 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
506 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
507 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
508 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
509 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
510 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
511 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0},
512 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
513 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
514 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
515 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
516 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
517 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
518 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
519 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
520 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0},
521 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
522 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
523 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
524 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
525 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
526 };
527
528 /* SHADER RESOURCE R600/R700 */
529 static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
530 {
531 struct r600_reg r600_shader_resource[] = {
532 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0},
533 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0},
534 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
535 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
536 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0},
537 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0},
538 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0},
539 };
540 unsigned nreg = Elements(r600_shader_resource);
541
542 for (int i = 0; i < nreg; i++) {
543 r600_shader_resource[i].offset += offset;
544 }
545 return r600_context_add_block(ctx, r600_shader_resource, nreg);
546 }
547
548 /* SHADER SAMPLER R600/R700 */
549 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
550 {
551 struct r600_reg r600_shader_sampler[] = {
552 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
553 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
554 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
555 };
556 unsigned nreg = Elements(r600_shader_sampler);
557
558 for (int i = 0; i < nreg; i++) {
559 r600_shader_sampler[i].offset += offset;
560 }
561 return r600_context_add_block(ctx, r600_shader_sampler, nreg);
562 }
563
564 /* SHADER SAMPLER BORDER R600/R700 */
565 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
566 {
567 struct r600_reg r600_shader_sampler_border[] = {
568 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
569 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
570 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
571 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
572 };
573 unsigned nreg = Elements(r600_shader_sampler_border);
574
575 for (int i = 0; i < nreg; i++) {
576 r600_shader_sampler_border[i].offset += offset;
577 }
578 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
579 }
580
581 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
582 {
583 unsigned nreg = 32;
584 struct r600_reg r600_loop_consts[32];
585 int i;
586
587 for (i = 0; i < nreg; i++) {
588 r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST;
589 r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET;
590 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
591 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
592 r600_loop_consts[i].flush_flags = 0;
593 r600_loop_consts[i].flush_mask = 0;
594 }
595 return r600_context_add_block(ctx, r600_loop_consts, nreg);
596 }
597
598 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
599 {
600 struct radeon_bo *bo, *tmp;
601
602 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
603 LIST_DELINIT(&bo->fencedlist);
604 bo->fence = 0;
605 bo->ctx = NULL;
606 }
607 }
608
609 /* initialize */
610 void r600_context_fini(struct r600_context *ctx)
611 {
612 struct r600_block *block;
613 struct r600_range *range;
614
615 for (int i = 0; i < 256; i++) {
616 for (int j = 0; j < (1 << ctx->hash_shift); j++) {
617 block = ctx->range[i].blocks[j];
618 if (block) {
619 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
620 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
621 range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL;
622 }
623 for (int k = 1; k <= block->nbo; k++) {
624 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
625 }
626 free(block);
627 }
628 }
629 free(ctx->range[i].blocks);
630 }
631 free(ctx->blocks);
632 free(ctx->reloc);
633 free(ctx->bo);
634 free(ctx->pm4);
635
636 r600_context_clear_fenced_bo(ctx);
637 memset(ctx, 0, sizeof(struct r600_context));
638 }
639
640 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
641 {
642 int r;
643
644 memset(ctx, 0, sizeof(struct r600_context));
645 ctx->radeon = radeon;
646 LIST_INITHEAD(&ctx->query_list);
647
648 /* initialize hash */
649 ctx->hash_size = 19;
650 ctx->hash_shift = 11;
651 for (int i = 0; i < 256; i++) {
652 ctx->range[i].start_offset = i << ctx->hash_shift;
653 ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1;
654 ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*));
655 if (ctx->range[i].blocks == NULL) {
656 r = -ENOMEM;
657 goto out_err;
658 }
659 }
660
661 /* add blocks */
662 r = r600_context_add_block(ctx, r600_config_reg_list,
663 Elements(r600_config_reg_list));
664 if (r)
665 goto out_err;
666 r = r600_context_add_block(ctx, r600_context_reg_list,
667 Elements(r600_context_reg_list));
668 if (r)
669 goto out_err;
670 r = r600_context_add_block(ctx, r600_ctl_const_list,
671 Elements(r600_ctl_const_list));
672 if (r)
673 goto out_err;
674
675 /* PS SAMPLER BORDER */
676 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
677 r = r600_state_sampler_border_init(ctx, offset);
678 if (r)
679 goto out_err;
680 }
681
682 /* VS SAMPLER BORDER */
683 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
684 r = r600_state_sampler_border_init(ctx, offset);
685 if (r)
686 goto out_err;
687 }
688 /* PS SAMPLER */
689 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
690 r = r600_state_sampler_init(ctx, offset);
691 if (r)
692 goto out_err;
693 }
694 /* VS SAMPLER */
695 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
696 r = r600_state_sampler_init(ctx, offset);
697 if (r)
698 goto out_err;
699 }
700 /* PS RESOURCE */
701 for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
702 r = r600_state_resource_init(ctx, offset);
703 if (r)
704 goto out_err;
705 }
706 /* VS RESOURCE */
707 for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
708 r = r600_state_resource_init(ctx, offset);
709 if (r)
710 goto out_err;
711 }
712 /* FS RESOURCE */
713 for (int j = 0, offset = 0x2300; j < 16; j++, offset += 0x1C) {
714 r = r600_state_resource_init(ctx, offset);
715 if (r)
716 goto out_err;
717 }
718
719 /* PS loop const */
720 r600_loop_const_init(ctx, 0);
721 /* VS loop const */
722 r600_loop_const_init(ctx, 32);
723
724 /* setup block table */
725 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
726 for (int i = 0, c = 0; i < 256; i++) {
727 for (int j = 0, add; j < (1 << ctx->hash_shift); j++) {
728 if (ctx->range[i].blocks[j]) {
729 add = 1;
730 for (int k = 0; k < c; k++) {
731 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
732 add = 0;
733 break;
734 }
735 }
736 if (add) {
737 assert(c < ctx->nblocks);
738 ctx->blocks[c++] = ctx->range[i].blocks[j];
739 j += (ctx->range[i].blocks[j]->nreg << 2) - 1;
740 }
741 }
742 }
743 }
744
745 /* allocate cs variables */
746 ctx->nreloc = RADEON_CTX_MAX_PM4;
747 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
748 if (ctx->reloc == NULL) {
749 r = -ENOMEM;
750 goto out_err;
751 }
752 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
753 if (ctx->bo == NULL) {
754 r = -ENOMEM;
755 goto out_err;
756 }
757 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
758 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
759 if (ctx->pm4 == NULL) {
760 r = -ENOMEM;
761 goto out_err;
762 }
763 /* save 16dwords space for fence mecanism */
764 ctx->pm4_ndwords -= 16;
765
766 LIST_INITHEAD(&ctx->fenced_bo);
767
768 /* init dirty list */
769 LIST_INITHEAD(&ctx->dirty);
770
771 ctx->max_db = 4;
772
773 return 0;
774 out_err:
775 r600_context_fini(ctx);
776 return r;
777 }
778
779 /* Flushes all surfaces */
780 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
781 {
782 unsigned ndwords = 5;
783
784 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
785 /* need to flush */
786 r600_context_flush(ctx);
787 }
788
789 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
790 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
791 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
792 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
793 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
794 }
795
796 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
797 unsigned flush_mask, struct r600_bo *rbo)
798 {
799 struct radeon_bo *bo;
800
801 bo = rbo->bo;
802 /* if bo has already been flushed */
803 if (!(~bo->last_flush & flush_flags)) {
804 bo->last_flush &= flush_mask;
805 return;
806 }
807
808 if ((ctx->radeon->family < CHIP_RV770) &&
809 (G_0085F0_CB_ACTION_ENA(flush_flags) ||
810 G_0085F0_DB_ACTION_ENA(flush_flags))) {
811 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
812 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
813 if (ctx->radeon->family == CHIP_RV670) {
814 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
815 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
816 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
817 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
818 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
819 }
820
821 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing);
822 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
823 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
824 }
825 } else {
826 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
827 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
828 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
829 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
830 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
831 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
832 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
833 }
834 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
835 }
836
837 void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
838 {
839 struct radeon_bo *bo;
840
841 bo = rbo->bo;
842 assert(bo != NULL);
843 if (bo->reloc) {
844 *pm4 = bo->reloc_id;
845 return;
846 }
847 bo->reloc = &ctx->reloc[ctx->creloc];
848 bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
849 ctx->reloc[ctx->creloc].handle = bo->handle;
850 ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
851 ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
852 ctx->reloc[ctx->creloc].flags = 0;
853 radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
854 rbo->fence = ctx->radeon->fence;
855 ctx->creloc++;
856 /* set PKT3 to point to proper reloc */
857 *pm4 = bo->reloc_id;
858 }
859
860 void r600_context_reg(struct r600_context *ctx,
861 unsigned offset, unsigned value,
862 unsigned mask)
863 {
864 struct r600_range *range;
865 struct r600_block *block;
866 unsigned id;
867 unsigned new_val;
868 int dirty;
869
870 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
871 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
872 id = (offset - block->start_offset) >> 2;
873
874 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
875
876 new_val = block->reg[id];
877 new_val &= ~mask;
878 new_val |= value;
879 if (new_val != block->reg[id]) {
880 dirty |= R600_BLOCK_STATUS_DIRTY;
881 block->reg[id] = new_val;
882 }
883 r600_context_dirty_block(ctx, block, dirty, id);
884 }
885
886 void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
887 int dirty, int index)
888 {
889 if (dirty && (index + 1) > block->nreg_dirty)
890 block->nreg_dirty = index + 1;
891
892 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
893
894 block->status |= R600_BLOCK_STATUS_ENABLED;
895 block->status |= R600_BLOCK_STATUS_DIRTY;
896 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
897 LIST_ADDTAIL(&block->list,&ctx->dirty);
898 }
899 }
900
901 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
902 {
903 struct r600_range *range;
904 struct r600_block *block;
905 unsigned new_val;
906 int dirty;
907 for (int i = 0; i < state->nregs; i++) {
908 unsigned id, reloc_id;
909
910 range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)];
911 block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)];
912 id = (state->regs[i].offset - block->start_offset) >> 2;
913
914 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
915
916 new_val = block->reg[id];
917 new_val &= ~state->regs[i].mask;
918 new_val |= state->regs[i].value;
919 if (new_val != block->reg[id]) {
920 block->reg[id] = new_val;
921 dirty |= R600_BLOCK_STATUS_DIRTY;
922 }
923 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
924 dirty |= R600_BLOCK_STATUS_DIRTY;
925 if (block->pm4_bo_index[id] && state->regs[i].bo) {
926 /* find relocation */
927 reloc_id = block->pm4_bo_index[id];
928 r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, state->regs[i].bo);
929 state->regs[i].bo->fence = ctx->radeon->fence;
930 /* always force dirty for relocs for now */
931 dirty |= R600_BLOCK_STATUS_DIRTY;
932 }
933
934 r600_context_dirty_block(ctx, block, dirty, id);
935 }
936 }
937
938 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
939 {
940 struct r600_range *range;
941 struct r600_block *block;
942 int i;
943 int dirty;
944 int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
945
946 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
947 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
948 if (state == NULL) {
949 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
950 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
951 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
952 LIST_DELINIT(&block->list);
953 return;
954 }
955
956 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
957
958 for (i = 0; i < num_regs; i++) {
959 if (block->reg[i] != state->regs[i].value) {
960 dirty |= R600_BLOCK_STATUS_DIRTY;
961 block->reg[i] = state->regs[i].value;
962 }
963 }
964
965 /* if no BOs on block, force dirty */
966 if (!block->reloc[1].bo || !block->reloc[2].bo)
967 dirty |= R600_BLOCK_STATUS_DIRTY;
968
969 if (!dirty) {
970 if (state->regs[0].bo) {
971 if ((block->reloc[1].bo->bo->handle != state->regs[0].bo->bo->handle) ||
972 (block->reloc[2].bo->bo->handle != state->regs[0].bo->bo->handle))
973 dirty |= R600_BLOCK_STATUS_DIRTY;
974 } else {
975 if ((block->reloc[1].bo->bo->handle != state->regs[2].bo->bo->handle) ||
976 (block->reloc[2].bo->bo->handle != state->regs[3].bo->bo->handle))
977 dirty |= R600_BLOCK_STATUS_DIRTY;
978 }
979 }
980 if (!dirty) {
981 if (state->regs[0].bo)
982 state->regs[0].bo->fence = ctx->radeon->fence;
983 else {
984 state->regs[2].bo->fence = ctx->radeon->fence;
985 state->regs[3].bo->fence = ctx->radeon->fence;
986 }
987 } else {
988 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
989 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
990 if (state->regs[0].bo) {
991 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
992 * we have single case btw VERTEX & TEXTURE resource
993 */
994 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
995 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
996 state->regs[0].bo->fence = ctx->radeon->fence;
997 } else {
998 /* TEXTURE RESOURCE */
999 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
1000 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
1001 state->regs[2].bo->fence = ctx->radeon->fence;
1002 state->regs[3].bo->fence = ctx->radeon->fence;
1003 }
1004 }
1005 r600_context_dirty_block(ctx, block, dirty, num_regs - 1);
1006 }
1007
1008 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
1009 {
1010 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
1011
1012 r600_context_pipe_state_set_resource(ctx, state, offset);
1013 }
1014
1015 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
1016 {
1017 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
1018
1019 r600_context_pipe_state_set_resource(ctx, state, offset);
1020 }
1021
1022 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
1023 {
1024 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x2300 + 0x1C * rid;
1025
1026 r600_context_pipe_state_set_resource(ctx, state, offset);
1027 }
1028
1029 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1030 {
1031 struct r600_range *range;
1032 struct r600_block *block;
1033 int i;
1034 int dirty;
1035
1036 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
1037 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
1038 if (state == NULL) {
1039 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1040 LIST_DELINIT(&block->list);
1041 return;
1042 }
1043 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1044 for (i = 0; i < 3; i++) {
1045 if (block->reg[i] != state->regs[i].value) {
1046 block->reg[i] = state->regs[i].value;
1047 dirty |= R600_BLOCK_STATUS_DIRTY;
1048 }
1049 }
1050
1051 r600_context_dirty_block(ctx, block, dirty, 2);
1052 }
1053
1054 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
1055 {
1056 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
1057 return;
1058
1059 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1060 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1061
1062 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
1063 }
1064
1065 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1066 {
1067 struct r600_range *range;
1068 struct r600_block *block;
1069 int i;
1070 int dirty;
1071
1072 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
1073 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
1074 if (state == NULL) {
1075 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1076 LIST_DELINIT(&block->list);
1077 return;
1078 }
1079 if (state->nregs <= 3) {
1080 return;
1081 }
1082 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1083 for (i = 0; i < 4; i++) {
1084 if (block->reg[i] != state->regs[i + 3].value) {
1085 block->reg[i] = state->regs[i + 3].value;
1086 dirty |= R600_BLOCK_STATUS_DIRTY;
1087 }
1088 }
1089
1090 /* We have to flush the shaders before we change the border color
1091 * registers, or previous draw commands that haven't completed yet
1092 * will end up using the new border color. */
1093 if (dirty & R600_BLOCK_STATUS_DIRTY)
1094 r600_context_ps_partial_flush(ctx);
1095
1096 r600_context_dirty_block(ctx, block, dirty, 3);
1097 }
1098
1099 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1100 {
1101 unsigned offset;
1102
1103 offset = 0x0003C000 + id * 0xc;
1104 r600_context_pipe_state_set_sampler(ctx, state, offset);
1105 offset = 0x0000A400 + id * 0x10;
1106 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1107 }
1108
1109 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1110 {
1111 unsigned offset;
1112
1113 offset = 0x0003C0D8 + id * 0xc;
1114 r600_context_pipe_state_set_sampler(ctx, state, offset);
1115 offset = 0x0000A600 + id * 0x10;
1116 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1117 }
1118
1119 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1120 {
1121 struct r600_range *range;
1122 struct r600_block *block;
1123 unsigned id;
1124
1125 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
1126 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
1127 offset -= block->start_offset;
1128 id = block->pm4_bo_index[offset >> 2];
1129 if (block->reloc[id].bo) {
1130 return block->reloc[id].bo;
1131 }
1132 return NULL;
1133 }
1134
1135 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1136 {
1137 int id;
1138
1139 if (block->nreg_dirty == 0 && block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS)) {
1140 goto out;
1141 }
1142
1143 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1144 for (int j = 0; j < block->nreg; j++) {
1145 if (block->pm4_bo_index[j]) {
1146 /* find relocation */
1147 id = block->pm4_bo_index[j];
1148 if (block->reloc[id].bo) {
1149 r600_context_bo_reloc(ctx,
1150 &block->pm4[block->reloc[id].bo_pm4_index],
1151 block->reloc[id].bo);
1152 r600_context_bo_flush(ctx,
1153 block->reloc[id].flush_flags,
1154 block->reloc[id].flush_mask,
1155 block->reloc[id].bo);
1156 }
1157 }
1158 }
1159 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1160 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4);
1161 ctx->pm4_cdwords += block->pm4_ndwords;
1162
1163 if (block->nreg_dirty != block->nreg && block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS)) {
1164 int new_dwords = block->nreg_dirty;
1165 uint32_t oldword, newword;
1166 ctx->pm4_cdwords -= block->pm4_ndwords;
1167 newword = oldword = ctx->pm4[ctx->pm4_cdwords];
1168 newword &= PKT_COUNT_C;
1169 newword |= PKT_COUNT_S(new_dwords);
1170 ctx->pm4[ctx->pm4_cdwords] = newword;
1171 ctx->pm4_cdwords += new_dwords + 2;
1172 }
1173 out:
1174 block->status ^= R600_BLOCK_STATUS_DIRTY;
1175 block->nreg_dirty = 0;
1176 LIST_DELINIT(&block->list);
1177 }
1178
1179 void r600_context_flush_dest_caches(struct r600_context *ctx)
1180 {
1181 struct r600_bo *cb[8];
1182 struct r600_bo *db;
1183 int i;
1184
1185 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1186 return;
1187
1188 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1189 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1190 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1191 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1192 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1193 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1194 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1195 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1196 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1197
1198 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1199 /* flush the color buffers */
1200 for (i = 0; i < 8; i++) {
1201 if (!cb[i])
1202 continue;
1203
1204 r600_context_bo_flush(ctx,
1205 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1206 S_0085F0_CB_ACTION_ENA(1),
1207 0, cb[i]);
1208 }
1209 if (db) {
1210 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1), 0, db);
1211 }
1212 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1213 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1214 }
1215
1216 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1217 {
1218 unsigned ndwords = 7;
1219 struct r600_block *dirty_block = NULL;
1220 struct r600_block *next_block;
1221
1222 if (draw->indices) {
1223 ndwords = 11;
1224 /* make sure there is enough relocation space before scheduling draw */
1225 if (ctx->creloc >= (ctx->nreloc - 1)) {
1226 r600_context_flush(ctx);
1227 }
1228 }
1229
1230 /* queries need some special values */
1231 if (ctx->num_query_running) {
1232 if (ctx->radeon->family >= CHIP_RV770) {
1233 r600_context_reg(ctx,
1234 R_028D0C_DB_RENDER_CONTROL,
1235 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1236 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1237 }
1238 r600_context_reg(ctx,
1239 R_028D10_DB_RENDER_OVERRIDE,
1240 S_028D10_NOOP_CULL_DISABLE(1),
1241 S_028D10_NOOP_CULL_DISABLE(1));
1242 }
1243
1244 /* update the max dword count to make sure we have enough space
1245 * reserved for flushing the destination caches */
1246 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4 - ctx->num_dest_buffers * 7 - 16;
1247
1248 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1249 /* need to flush */
1250 r600_context_flush(ctx);
1251 }
1252 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1253 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1254 R600_ERR("context is too big to be scheduled\n");
1255 return;
1256 }
1257 /* enough room to copy packet */
1258 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1259 r600_context_block_emit_dirty(ctx, dirty_block);
1260 }
1261
1262 /* draw packet */
1263 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1264 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
1265 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1266 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
1267 if (draw->indices) {
1268 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1269 ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1270 ctx->pm4[ctx->pm4_cdwords++] = 0;
1271 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1272 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1273 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1274 ctx->pm4[ctx->pm4_cdwords++] = 0;
1275 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
1276 } else {
1277 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1278 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1279 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1280 }
1281
1282 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1283
1284 /* all dirty state have been scheduled in current cs */
1285 ctx->pm4_dirty_cdwords = 0;
1286 }
1287
1288 void r600_context_flush(struct r600_context *ctx)
1289 {
1290 struct drm_radeon_cs drmib = {};
1291 struct drm_radeon_cs_chunk chunks[2];
1292 uint64_t chunk_array[2];
1293 unsigned fence;
1294 int r;
1295
1296 if (!ctx->pm4_cdwords)
1297 return;
1298
1299 /* suspend queries */
1300 r600_context_queries_suspend(ctx);
1301
1302 if (ctx->radeon->family >= CHIP_CEDAR)
1303 evergreen_context_flush_dest_caches(ctx);
1304 else
1305 r600_context_flush_dest_caches(ctx);
1306
1307 /* partial flush is needed to avoid lockups on some chips with user fences */
1308 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1309 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1310 /* emit fence */
1311 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1312 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1313 ctx->pm4[ctx->pm4_cdwords++] = 0;
1314 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1315 ctx->pm4[ctx->pm4_cdwords++] = ctx->radeon->fence;
1316 ctx->pm4[ctx->pm4_cdwords++] = 0;
1317 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1318 ctx->pm4[ctx->pm4_cdwords++] = 0;
1319 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->radeon->fence_bo);
1320
1321 #if 1
1322 /* emit cs */
1323 drmib.num_chunks = 2;
1324 drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1325 chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1326 chunks[0].length_dw = ctx->pm4_cdwords;
1327 chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1328 chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1329 chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1330 chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1331 chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1332 chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1333 r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1334 sizeof(struct drm_radeon_cs));
1335 #else
1336 *ctx->radeon->cfence = ctx->radeon->fence;
1337 #endif
1338
1339 r600_context_update_fenced_list(ctx);
1340
1341 fence = ctx->radeon->fence + 1;
1342 if (fence < ctx->radeon->fence) {
1343 /* wrap around */
1344 fence = 1;
1345 r600_context_fence_wraparound(ctx, fence);
1346 }
1347 ctx->radeon->fence = fence;
1348
1349 /* restart */
1350 for (int i = 0; i < ctx->creloc; i++) {
1351 ctx->bo[i]->reloc = NULL;
1352 ctx->bo[i]->last_flush = 0;
1353 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1354 }
1355 ctx->creloc = 0;
1356 ctx->pm4_dirty_cdwords = 0;
1357 ctx->pm4_cdwords = 0;
1358 ctx->flags = 0;
1359
1360 /* resume queries */
1361 r600_context_queries_resume(ctx);
1362
1363 /* set all valid group as dirty so they get reemited on
1364 * next draw command
1365 */
1366 for (int i = 0; i < ctx->nblocks; i++) {
1367 if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) {
1368 if(!(ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY)) {
1369 LIST_ADDTAIL(&ctx->blocks[i]->list,&ctx->dirty);
1370 }
1371 ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords + ctx->blocks[i]->pm4_flush_ndwords;
1372 ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY;
1373 ctx->blocks[i]->nreg_dirty = ctx->blocks[i]->nreg;
1374 }
1375 }
1376 }
1377
1378 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence_bo, unsigned offset, unsigned value)
1379 {
1380 unsigned ndwords = 10;
1381
1382 if (((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) ||
1383 (ctx->creloc >= (ctx->nreloc - 1))) {
1384 /* need to flush */
1385 r600_context_flush(ctx);
1386 }
1387
1388 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1389 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1390 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1391 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1392 ctx->pm4[ctx->pm4_cdwords++] = offset << 2; /* ADDRESS_LO */
1393 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */
1394 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */
1395 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */
1396 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1397 ctx->pm4[ctx->pm4_cdwords++] = 0;
1398 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], fence_bo);
1399 }
1400
1401 void r600_context_dump_bof(struct r600_context *ctx, const char *file)
1402 {
1403 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
1404 unsigned i;
1405
1406 root = device_id = bcs = blob = array = bo = size = handle = NULL;
1407 root = bof_object();
1408 if (root == NULL)
1409 goto out_err;
1410 device_id = bof_int32(ctx->radeon->device);
1411 if (device_id == NULL)
1412 goto out_err;
1413 if (bof_object_set(root, "device_id", device_id))
1414 goto out_err;
1415 bof_decref(device_id);
1416 device_id = NULL;
1417 /* dump relocs */
1418 blob = bof_blob(ctx->creloc * 16, ctx->reloc);
1419 if (blob == NULL)
1420 goto out_err;
1421 if (bof_object_set(root, "reloc", blob))
1422 goto out_err;
1423 bof_decref(blob);
1424 blob = NULL;
1425 /* dump cs */
1426 blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
1427 if (blob == NULL)
1428 goto out_err;
1429 if (bof_object_set(root, "pm4", blob))
1430 goto out_err;
1431 bof_decref(blob);
1432 blob = NULL;
1433 /* dump bo */
1434 array = bof_array();
1435 if (array == NULL)
1436 goto out_err;
1437 for (i = 0; i < ctx->creloc; i++) {
1438 struct radeon_bo *rbo = ctx->bo[i];
1439 bo = bof_object();
1440 if (bo == NULL)
1441 goto out_err;
1442 size = bof_int32(rbo->size);
1443 if (size == NULL)
1444 goto out_err;
1445 if (bof_object_set(bo, "size", size))
1446 goto out_err;
1447 bof_decref(size);
1448 size = NULL;
1449 handle = bof_int32(rbo->handle);
1450 if (handle == NULL)
1451 goto out_err;
1452 if (bof_object_set(bo, "handle", handle))
1453 goto out_err;
1454 bof_decref(handle);
1455 handle = NULL;
1456 radeon_bo_map(ctx->radeon, rbo);
1457 blob = bof_blob(rbo->size, rbo->data);
1458 radeon_bo_unmap(ctx->radeon, rbo);
1459 if (blob == NULL)
1460 goto out_err;
1461 if (bof_object_set(bo, "data", blob))
1462 goto out_err;
1463 bof_decref(blob);
1464 blob = NULL;
1465 if (bof_array_append(array, bo))
1466 goto out_err;
1467 bof_decref(bo);
1468 bo = NULL;
1469 }
1470 if (bof_object_set(root, "bo", array))
1471 goto out_err;
1472 bof_dump_file(root, file);
1473 out_err:
1474 bof_decref(blob);
1475 bof_decref(array);
1476 bof_decref(bo);
1477 bof_decref(size);
1478 bof_decref(handle);
1479 bof_decref(device_id);
1480 bof_decref(root);
1481 }
1482
1483 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1484 {
1485 u64 start, end;
1486 u32 *results;
1487 int i;
1488 int size;
1489
1490 if (wait)
1491 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_CPU_READ, NULL);
1492 else
1493 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_READ, NULL);
1494 if (!results)
1495 return FALSE;
1496
1497 size = query->num_results * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1498 for (i = 0; i < size; i += 4) {
1499 start = (u64)results[i] | (u64)results[i + 1] << 32;
1500 end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
1501 if (((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))
1502 || query->type == PIPE_QUERY_TIME_ELAPSED) {
1503 query->result += end - start;
1504 }
1505 }
1506 r600_bo_unmap(ctx->radeon, query->buffer);
1507 query->num_results = 0;
1508
1509 return TRUE;
1510 }
1511
1512 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1513 {
1514 unsigned required_space;
1515 int num_backends = r600_get_num_backends(ctx->radeon);
1516
1517 /* query request needs 6/8 dwords for begin + 6/8 dwords for end */
1518 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1519 required_space = 16;
1520 else
1521 required_space = 12;
1522
1523 if ((required_space + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1524 /* need to flush */
1525 r600_context_flush(ctx);
1526 }
1527
1528 /* if query buffer is full force a flush */
1529 if (query->num_results*4 >= query->buffer_size - 16) {
1530 r600_context_flush(ctx);
1531 r600_query_result(ctx, query, TRUE);
1532 }
1533
1534 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER &&
1535 num_backends > 0 && num_backends < ctx->max_db) {
1536 /* as per info on ZPASS the driver must set the unusued DB top bits */
1537 u32 *results;
1538 int i;
1539
1540 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_WRITE, NULL);
1541 if (results) {
1542 memset(results + (query->num_results * 4), 0, ctx->max_db * 4 * 4);
1543
1544 for (i = num_backends; i < ctx->max_db; i++) {
1545 results[(i * 4)+1] = 0x80000000;
1546 results[(i * 4)+3] = 0x80000000;
1547 }
1548 r600_bo_unmap(ctx->radeon, query->buffer);
1549 }
1550 }
1551
1552 /* emit begin query */
1553 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1554 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1555 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1556 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1557 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1558 ctx->pm4[ctx->pm4_cdwords++] = 0;
1559 ctx->pm4[ctx->pm4_cdwords++] = 0;
1560 } else {
1561 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1562 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1563 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1564 ctx->pm4[ctx->pm4_cdwords++] = 0;
1565 }
1566 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1567 ctx->pm4[ctx->pm4_cdwords++] = 0;
1568 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1569
1570 query->state |= R600_QUERY_STATE_STARTED;
1571 query->state ^= R600_QUERY_STATE_ENDED;
1572 ctx->num_query_running++;
1573 }
1574
1575 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1576 {
1577 /* emit begin query */
1578 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1579 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1580 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1581 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1582 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1583 ctx->pm4[ctx->pm4_cdwords++] = 0;
1584 ctx->pm4[ctx->pm4_cdwords++] = 0;
1585 } else {
1586 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1587 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1588 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1589 ctx->pm4[ctx->pm4_cdwords++] = 0;
1590 }
1591 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1592 ctx->pm4[ctx->pm4_cdwords++] = 0;
1593 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1594
1595 query->num_results += 4 * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1596 query->state ^= R600_QUERY_STATE_STARTED;
1597 query->state |= R600_QUERY_STATE_ENDED;
1598 ctx->num_query_running--;
1599 }
1600
1601 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1602 int flag_wait)
1603 {
1604 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1605
1606 if (operation == PREDICATION_OP_CLEAR) {
1607 ctx->pm4[ctx->pm4_cdwords++] = 0;
1608 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1609 } else {
1610 int results_base = query->num_results - (4 * ctx->max_db);
1611
1612 if (results_base < 0)
1613 results_base = 0;
1614
1615 ctx->pm4[ctx->pm4_cdwords++] = results_base*4 + r600_bo_offset(query->buffer);
1616 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(operation) | (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW) | PREDICATION_DRAW_VISIBLE;
1617 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1618 ctx->pm4[ctx->pm4_cdwords++] = 0;
1619 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1620 }
1621 }
1622
1623 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1624 {
1625 struct r600_query *query;
1626
1627 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER && query_type != PIPE_QUERY_TIME_ELAPSED)
1628 return NULL;
1629
1630 query = calloc(1, sizeof(struct r600_query));
1631 if (query == NULL)
1632 return NULL;
1633
1634 query->type = query_type;
1635 query->buffer_size = 4096;
1636
1637 /* As of GL4, query buffers are normally read by the CPU after
1638 * being written by the gpu, hence staging is probably a good
1639 * usage pattern.
1640 */
1641 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1642 PIPE_USAGE_STAGING);
1643 if (!query->buffer) {
1644 free(query);
1645 return NULL;
1646 }
1647
1648 LIST_ADDTAIL(&query->list, &ctx->query_list);
1649
1650 return query;
1651 }
1652
1653 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1654 {
1655 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1656 LIST_DELINIT(&query->list);
1657 free(query);
1658 }
1659
1660 boolean r600_context_query_result(struct r600_context *ctx,
1661 struct r600_query *query,
1662 boolean wait, void *vresult)
1663 {
1664 uint64_t *result = (uint64_t*)vresult;
1665
1666 if (query->num_results) {
1667 r600_context_flush(ctx);
1668 }
1669 if (!r600_query_result(ctx, query, wait))
1670 return FALSE;
1671 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1672 *result = (1000000*query->result)/r600_get_clock_crystal_freq(ctx->radeon);
1673 else
1674 *result = query->result;
1675 query->result = 0;
1676 return TRUE;
1677 }
1678
1679 void r600_context_queries_suspend(struct r600_context *ctx)
1680 {
1681 struct r600_query *query;
1682
1683 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1684 if (query->state & R600_QUERY_STATE_STARTED) {
1685 r600_query_end(ctx, query);
1686 query->state |= R600_QUERY_STATE_SUSPENDED;
1687 }
1688 }
1689 }
1690
1691 void r600_context_queries_resume(struct r600_context *ctx)
1692 {
1693 struct r600_query *query;
1694
1695 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1696 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1697 r600_query_begin(ctx, query);
1698 query->state ^= R600_QUERY_STATE_SUSPENDED;
1699 }
1700 }
1701 }