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[g3dvl] move zscan into shaders
[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <pipe/p_compiler.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include <pipebuffer/pb_bufmgr.h>
35 #include "xf86drm.h"
36 #include "radeon_drm.h"
37 #include "r600_priv.h"
38 #include "bof.h"
39 #include "r600d.h"
40
41 #define GROUP_FORCE_NEW_BLOCK 0
42
43 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
44 {
45 for (int i = 0; i < ctx->creloc; i++) {
46 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
47 LIST_DELINIT(&ctx->bo[i]->fencedlist);
48 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
49 ctx->bo[i]->fence = ctx->radeon->fence;
50 ctx->bo[i]->ctx = ctx;
51 }
52 }
53
54 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
55 {
56 struct radeon_bo *bo = NULL;
57 struct radeon_bo *tmp;
58
59 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
60 if (bo->fence <= *ctx->radeon->cfence) {
61 LIST_DELINIT(&bo->fencedlist);
62 bo->fence = 0;
63 } else {
64 bo->fence = fence;
65 }
66 }
67 }
68
69 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
70 {
71 struct r600_block *block;
72 struct r600_range *range;
73 int offset;
74
75 for (unsigned i = 0, n = 0; i < nreg; i += n) {
76 u32 j;
77
78 /* ignore new block balise */
79 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
80 n = 1;
81 continue;
82 }
83
84 /* register that need relocation are in their own group */
85 /* find number of consecutive registers */
86 n = 0;
87 offset = reg[i].offset;
88 while (reg[i + n].offset == offset) {
89 n++;
90 offset += 4;
91 if ((n + i) >= nreg)
92 break;
93 if (n >= (R600_BLOCK_MAX_REG - 2))
94 break;
95 }
96
97 /* allocate new block */
98 block = calloc(1, sizeof(struct r600_block));
99 if (block == NULL) {
100 return -ENOMEM;
101 }
102 ctx->nblocks++;
103 for (int j = 0; j < n; j++) {
104 range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)];
105 range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block;
106 }
107
108 /* initialize block */
109 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
110 block->start_offset = reg[i].offset;
111 block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n, 0);
112 block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2;
113 block->reg = &block->pm4[block->pm4_ndwords];
114 block->pm4_ndwords += n;
115 block->nreg = n;
116 block->nreg_dirty = n;
117 block->flags = 0;
118 LIST_INITHEAD(&block->list);
119
120 for (j = 0; j < n; j++) {
121 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
122 block->flags |= REG_FLAG_DIRTY_ALWAYS;
123 }
124 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
125 block->nbo++;
126 assert(block->nbo < R600_BLOCK_MAX_BO);
127 block->pm4_bo_index[j] = block->nbo;
128 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
129 block->pm4[block->pm4_ndwords++] = 0x00000000;
130 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
131 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
132 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
133 }
134 }
135 for (j = 0; j < n; j++) {
136 if (reg[i+j].flush_flags) {
137 block->pm4_flush_ndwords += 7;
138 }
139 }
140 /* check that we stay in limit */
141 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
142 }
143 return 0;
144 }
145
146 /* R600/R700 configuration */
147 static const struct r600_reg r600_config_reg_list[] = {
148 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
149 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0},
150 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
151 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
152 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
153 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
154 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
155 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
156 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0},
157 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0},
158 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0},
159 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0},
160 };
161
162 static const struct r600_reg r600_ctl_const_list[] = {
163 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
164 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
165 };
166
167 static const struct r600_reg r600_context_reg_list[] = {
168 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0},
169 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
170 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
171 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
172 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
173 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
174 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
175 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
176 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
177 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
178 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
179 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
180 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0},
181 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
182 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
183 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
184 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
185 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
186 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
187 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
188 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
189 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
190 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
191 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0},
192 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
193 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
194 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
195 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
196 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
197 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
198 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
199 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
200 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0},
201 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
202 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
203 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0},
204 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0},
205 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
206 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
207 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
208 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
209 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0},
210 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
211 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0},
212 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
213 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
214 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0},
215 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0},
216 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
217 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
218 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
219 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
220 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0},
221 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
222 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0},
223 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
224 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
225 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0},
226 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0},
227 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
228 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
229 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
230 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
231 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0},
232 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
233 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0},
234 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
235 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
236 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
237 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
238 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
239 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
240 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
241 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
242 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0},
243 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
244 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0},
245 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
246 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
247 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0},
248 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0},
249 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
250 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
251 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
252 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
253 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0},
254 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
255 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0},
256 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
257 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
258 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0},
259 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0},
260 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
261 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
262 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
263 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
264 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0},
265 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0},
266 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
267 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0},
268 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0},
269 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
270 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
271 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
272 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
273 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0},
274 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
275 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0},
276 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
277 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
278 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
279 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
280 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
281 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
282 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0},
283 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0},
284 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0},
285 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0},
286 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
287 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
288 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
289 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
290 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
291 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0},
292 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0},
293 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
294 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0},
295 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0},
296 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0},
297 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0},
298 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0},
299 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0},
300 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0},
301 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0},
302 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
303 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0},
304 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
305 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
306 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
307 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
308 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
309 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
310 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
311 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
312 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
313 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
314 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
315 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
316 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
317 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0},
318 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0},
319 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
320 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
321 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
322 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
323 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
324 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
325 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0},
326 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
327 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0},
328 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
329 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
330 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO, 0, 0},
331 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0},
332 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0},
333 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
334 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
335 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
336 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
337 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
338 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
339 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
340 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
341 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
342 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
343 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
344 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
345 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
346 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
347 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
348 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
349 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
350 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
351 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
352 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
353 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
354 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0},
355 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
356 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
357 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
358 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
359 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
360 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
361 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
362 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
363 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
364 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
365 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
366 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
367 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
368 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
369 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
370 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
371 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
372 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
373 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
374 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
375 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
376 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
377 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
378 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
379 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
380 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
381 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
382 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
383 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
384 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
385 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
386 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
387 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
388 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
389 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
390 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0},
391 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
392 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
393 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
394 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0},
395 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
396 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
397 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
398 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0},
399 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
400 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
401 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
402 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0},
403 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
404 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
405 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
406 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0},
407 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
408 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
409 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
410 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0},
411 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
412 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
413 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
414 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
415 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
416 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
417 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
418 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
419 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
420 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
421 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
422 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
423 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
424 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
425 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
426 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
427 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
428 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
429 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
430 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
431 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
432 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
433 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
434 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
435 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
436 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
437 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
438 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
439 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
440 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
441 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
442 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
443 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
444 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
445 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
446 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
447 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
448 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
449 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
450 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
451 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
452 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
453 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
454 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
455 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
456 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
457 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
458 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
459 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
460 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
461 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
462 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
463 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
464 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
465 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
466 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
467 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
468 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
469 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
470 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
471 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
472 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
473 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
474 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
475 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
476 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
477 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
478 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
479 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
480 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
481 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
482 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
483 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
484 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
485 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
486 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
487 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
488 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
489 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
490 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
491 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
492 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
493 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
494 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
495 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
496 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
497 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
498 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
499 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
500 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
501 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0},
502 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
503 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
504 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
505 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
506 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
507 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
508 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
509 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
510 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0},
511 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
512 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
513 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
514 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
515 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
516 };
517
518 /* SHADER RESOURCE R600/R700 */
519 static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
520 {
521 struct r600_reg r600_shader_resource[] = {
522 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0},
523 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0},
524 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
525 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
526 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0},
527 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0},
528 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0},
529 };
530 unsigned nreg = Elements(r600_shader_resource);
531
532 for (int i = 0; i < nreg; i++) {
533 r600_shader_resource[i].offset += offset;
534 }
535 return r600_context_add_block(ctx, r600_shader_resource, nreg);
536 }
537
538 /* SHADER SAMPLER R600/R700 */
539 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
540 {
541 struct r600_reg r600_shader_sampler[] = {
542 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
543 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
544 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
545 };
546 unsigned nreg = Elements(r600_shader_sampler);
547
548 for (int i = 0; i < nreg; i++) {
549 r600_shader_sampler[i].offset += offset;
550 }
551 return r600_context_add_block(ctx, r600_shader_sampler, nreg);
552 }
553
554 /* SHADER SAMPLER BORDER R600/R700 */
555 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
556 {
557 struct r600_reg r600_shader_sampler_border[] = {
558 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
559 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
560 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
561 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
562 };
563 unsigned nreg = Elements(r600_shader_sampler_border);
564
565 for (int i = 0; i < nreg; i++) {
566 r600_shader_sampler_border[i].offset += offset;
567 }
568 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
569 }
570
571 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
572 {
573 unsigned nreg = 32;
574 struct r600_reg r600_loop_consts[32];
575 int i;
576
577 for (i = 0; i < nreg; i++) {
578 r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST;
579 r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET;
580 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
581 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
582 r600_loop_consts[i].flush_flags = 0;
583 r600_loop_consts[i].flush_mask = 0;
584 }
585 return r600_context_add_block(ctx, r600_loop_consts, nreg);
586 }
587
588 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
589 {
590 struct radeon_bo *bo, *tmp;
591
592 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
593 LIST_DELINIT(&bo->fencedlist);
594 bo->fence = 0;
595 bo->ctx = NULL;
596 }
597 }
598
599 /* initialize */
600 void r600_context_fini(struct r600_context *ctx)
601 {
602 struct r600_block *block;
603 struct r600_range *range;
604
605 for (int i = 0; i < 256; i++) {
606 for (int j = 0; j < (1 << ctx->hash_shift); j++) {
607 block = ctx->range[i].blocks[j];
608 if (block) {
609 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
610 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
611 range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL;
612 }
613 for (int k = 1; k <= block->nbo; k++) {
614 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
615 }
616 free(block);
617 }
618 }
619 free(ctx->range[i].blocks);
620 }
621 free(ctx->blocks);
622 free(ctx->reloc);
623 free(ctx->bo);
624 free(ctx->pm4);
625
626 r600_context_clear_fenced_bo(ctx);
627 memset(ctx, 0, sizeof(struct r600_context));
628 }
629
630 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
631 {
632 int r;
633
634 memset(ctx, 0, sizeof(struct r600_context));
635 ctx->radeon = radeon;
636 LIST_INITHEAD(&ctx->query_list);
637
638 /* initialize hash */
639 ctx->hash_size = 19;
640 ctx->hash_shift = 11;
641 for (int i = 0; i < 256; i++) {
642 ctx->range[i].start_offset = i << ctx->hash_shift;
643 ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1;
644 ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*));
645 if (ctx->range[i].blocks == NULL) {
646 r = -ENOMEM;
647 goto out_err;
648 }
649 }
650
651 /* add blocks */
652 r = r600_context_add_block(ctx, r600_config_reg_list,
653 Elements(r600_config_reg_list));
654 if (r)
655 goto out_err;
656 r = r600_context_add_block(ctx, r600_context_reg_list,
657 Elements(r600_context_reg_list));
658 if (r)
659 goto out_err;
660 r = r600_context_add_block(ctx, r600_ctl_const_list,
661 Elements(r600_ctl_const_list));
662 if (r)
663 goto out_err;
664
665 /* PS SAMPLER BORDER */
666 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
667 r = r600_state_sampler_border_init(ctx, offset);
668 if (r)
669 goto out_err;
670 }
671
672 /* VS SAMPLER BORDER */
673 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
674 r = r600_state_sampler_border_init(ctx, offset);
675 if (r)
676 goto out_err;
677 }
678 /* PS SAMPLER */
679 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
680 r = r600_state_sampler_init(ctx, offset);
681 if (r)
682 goto out_err;
683 }
684 /* VS SAMPLER */
685 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
686 r = r600_state_sampler_init(ctx, offset);
687 if (r)
688 goto out_err;
689 }
690 /* PS RESOURCE */
691 for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
692 r = r600_state_resource_init(ctx, offset);
693 if (r)
694 goto out_err;
695 }
696 /* VS RESOURCE */
697 for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
698 r = r600_state_resource_init(ctx, offset);
699 if (r)
700 goto out_err;
701 }
702 /* FS RESOURCE */
703 for (int j = 0, offset = 0x2300; j < 16; j++, offset += 0x1C) {
704 r = r600_state_resource_init(ctx, offset);
705 if (r)
706 goto out_err;
707 }
708
709 /* PS loop const */
710 r600_loop_const_init(ctx, 0);
711 /* VS loop const */
712 r600_loop_const_init(ctx, 32);
713
714 /* setup block table */
715 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
716 for (int i = 0, c = 0; i < 256; i++) {
717 for (int j = 0, add; j < (1 << ctx->hash_shift); j++) {
718 if (ctx->range[i].blocks[j]) {
719 add = 1;
720 for (int k = 0; k < c; k++) {
721 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
722 add = 0;
723 break;
724 }
725 }
726 if (add) {
727 assert(c < ctx->nblocks);
728 ctx->blocks[c++] = ctx->range[i].blocks[j];
729 j += (ctx->range[i].blocks[j]->nreg << 2) - 1;
730 }
731 }
732 }
733 }
734
735 /* allocate cs variables */
736 ctx->nreloc = RADEON_CTX_MAX_PM4;
737 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
738 if (ctx->reloc == NULL) {
739 r = -ENOMEM;
740 goto out_err;
741 }
742 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
743 if (ctx->bo == NULL) {
744 r = -ENOMEM;
745 goto out_err;
746 }
747 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
748 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
749 if (ctx->pm4 == NULL) {
750 r = -ENOMEM;
751 goto out_err;
752 }
753 /* save 16dwords space for fence mecanism */
754 ctx->pm4_ndwords -= 16;
755
756 LIST_INITHEAD(&ctx->fenced_bo);
757
758 /* init dirty list */
759 LIST_INITHEAD(&ctx->dirty);
760
761 ctx->max_db = 4;
762
763 return 0;
764 out_err:
765 r600_context_fini(ctx);
766 return r;
767 }
768
769 static void rv6xx_context_surface_base_update(struct r600_context *ctx,
770 unsigned base_update_flags)
771 {
772 /* need to emit surface base update on rv6xx */
773 if ((ctx->radeon->family > CHIP_R600) &&
774 (ctx->radeon->family < CHIP_RV770)) {
775 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
776 ctx->pm4[ctx->pm4_cdwords++] = base_update_flags;
777 }
778 }
779
780 /* Flushes all surfaces */
781 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
782 {
783 unsigned ndwords = 5;
784
785 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
786 /* need to flush */
787 r600_context_flush(ctx);
788 }
789
790 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
791 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
792 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
793 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
794 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
795 }
796
797 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
798 unsigned flush_mask, struct r600_bo *rbo)
799 {
800 struct radeon_bo *bo;
801 bo = r600_bo_get_bo(rbo);
802 /* if bo has already been flushed */
803 if (!(~bo->last_flush & flush_flags)) {
804 bo->last_flush &= flush_mask;
805 return;
806 }
807 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
808 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
809 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
810 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
811 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
812 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
813 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
814 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
815 }
816
817 void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
818 {
819 struct radeon_bo *bo;
820
821 bo = r600_bo_get_bo(rbo);
822 assert(bo != NULL);
823 if (bo->reloc) {
824 *pm4 = bo->reloc_id;
825 return;
826 }
827 bo->reloc = &ctx->reloc[ctx->creloc];
828 bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
829 ctx->reloc[ctx->creloc].handle = bo->handle;
830 ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
831 ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
832 ctx->reloc[ctx->creloc].flags = 0;
833 radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
834 rbo->fence = ctx->radeon->fence;
835 ctx->creloc++;
836 /* set PKT3 to point to proper reloc */
837 *pm4 = bo->reloc_id;
838 }
839
840 void r600_context_reg(struct r600_context *ctx,
841 unsigned offset, unsigned value,
842 unsigned mask)
843 {
844 struct r600_range *range;
845 struct r600_block *block;
846 unsigned id;
847 unsigned new_val;
848 int dirty;
849
850 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
851 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
852 id = (offset - block->start_offset) >> 2;
853
854 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
855
856 new_val = block->reg[id];
857 new_val &= ~mask;
858 new_val |= value;
859 if (new_val != block->reg[id]) {
860 dirty |= R600_BLOCK_STATUS_DIRTY;
861 block->reg[id] = new_val;
862 }
863 r600_context_dirty_block(ctx, block, dirty, id);
864 }
865
866 void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
867 int dirty, int index)
868 {
869 if (dirty && (index + 1) > block->nreg_dirty)
870 block->nreg_dirty = index + 1;
871
872 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
873
874 block->status |= R600_BLOCK_STATUS_ENABLED;
875 block->status |= R600_BLOCK_STATUS_DIRTY;
876 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
877 LIST_ADDTAIL(&block->list,&ctx->dirty);
878 }
879 }
880
881 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
882 {
883 struct r600_range *range;
884 struct r600_block *block;
885 unsigned new_val;
886 int dirty;
887 for (int i = 0; i < state->nregs; i++) {
888 unsigned id, reloc_id;
889
890 range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)];
891 block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)];
892 id = (state->regs[i].offset - block->start_offset) >> 2;
893
894 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
895
896 new_val = block->reg[id];
897 new_val &= ~state->regs[i].mask;
898 new_val |= state->regs[i].value;
899 if (new_val != block->reg[id]) {
900 block->reg[id] = new_val;
901 dirty |= R600_BLOCK_STATUS_DIRTY;
902 }
903 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
904 dirty |= R600_BLOCK_STATUS_DIRTY;
905 if (block->pm4_bo_index[id] && state->regs[i].bo) {
906 /* find relocation */
907 reloc_id = block->pm4_bo_index[id];
908 r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, state->regs[i].bo);
909 state->regs[i].bo->fence = ctx->radeon->fence;
910 /* always force dirty for relocs for now */
911 dirty |= R600_BLOCK_STATUS_DIRTY;
912 }
913
914 r600_context_dirty_block(ctx, block, dirty, id);
915 }
916 }
917
918 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
919 {
920 struct r600_range *range;
921 struct r600_block *block;
922 int i;
923 int dirty;
924 int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
925
926 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
927 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
928 if (state == NULL) {
929 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
930 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
931 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
932 LIST_DELINIT(&block->list);
933 return;
934 }
935
936 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
937
938 for (i = 0; i < num_regs; i++) {
939 if (block->reg[i] != state->regs[i].value) {
940 dirty |= R600_BLOCK_STATUS_DIRTY;
941 block->reg[i] = state->regs[i].value;
942 }
943 }
944
945 /* if no BOs on block, force dirty */
946 if (!block->reloc[1].bo || !block->reloc[2].bo)
947 dirty |= R600_BLOCK_STATUS_DIRTY;
948
949 if (!dirty) {
950 if (state->regs[0].bo) {
951 if ((block->reloc[1].bo->bo->handle != state->regs[0].bo->bo->handle) ||
952 (block->reloc[2].bo->bo->handle != state->regs[0].bo->bo->handle))
953 dirty |= R600_BLOCK_STATUS_DIRTY;
954 } else {
955 if ((block->reloc[1].bo->bo->handle != state->regs[2].bo->bo->handle) ||
956 (block->reloc[2].bo->bo->handle != state->regs[3].bo->bo->handle))
957 dirty |= R600_BLOCK_STATUS_DIRTY;
958 }
959 }
960 if (!dirty) {
961 if (state->regs[0].bo)
962 state->regs[0].bo->fence = ctx->radeon->fence;
963 else {
964 state->regs[2].bo->fence = ctx->radeon->fence;
965 state->regs[3].bo->fence = ctx->radeon->fence;
966 }
967 } else {
968 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
969 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
970 if (state->regs[0].bo) {
971 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
972 * we have single case btw VERTEX & TEXTURE resource
973 */
974 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
975 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
976 state->regs[0].bo->fence = ctx->radeon->fence;
977 } else {
978 /* TEXTURE RESOURCE */
979 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
980 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
981 state->regs[2].bo->fence = ctx->radeon->fence;
982 state->regs[3].bo->fence = ctx->radeon->fence;
983 }
984 }
985 r600_context_dirty_block(ctx, block, dirty, num_regs - 1);
986 }
987
988 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
989 {
990 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
991
992 r600_context_pipe_state_set_resource(ctx, state, offset);
993 }
994
995 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
996 {
997 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
998
999 r600_context_pipe_state_set_resource(ctx, state, offset);
1000 }
1001
1002 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
1003 {
1004 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x2300 + 0x1C * rid;
1005
1006 r600_context_pipe_state_set_resource(ctx, state, offset);
1007 }
1008
1009 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1010 {
1011 struct r600_range *range;
1012 struct r600_block *block;
1013 int i;
1014 int dirty;
1015
1016 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
1017 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
1018 if (state == NULL) {
1019 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1020 LIST_DELINIT(&block->list);
1021 return;
1022 }
1023 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1024 for (i = 0; i < 3; i++) {
1025 if (block->reg[i] != state->regs[i].value) {
1026 block->reg[i] = state->regs[i].value;
1027 dirty |= R600_BLOCK_STATUS_DIRTY;
1028 }
1029 }
1030
1031 r600_context_dirty_block(ctx, block, dirty, 2);
1032 }
1033
1034 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
1035 {
1036 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
1037 return;
1038
1039 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1040 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1041
1042 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
1043 }
1044
1045 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1046 {
1047 struct r600_range *range;
1048 struct r600_block *block;
1049 int i;
1050 int dirty;
1051
1052 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
1053 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
1054 if (state == NULL) {
1055 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1056 LIST_DELINIT(&block->list);
1057 return;
1058 }
1059 if (state->nregs <= 3) {
1060 return;
1061 }
1062 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1063 for (i = 0; i < 4; i++) {
1064 if (block->reg[i] != state->regs[i + 3].value) {
1065 block->reg[i] = state->regs[i + 3].value;
1066 dirty |= R600_BLOCK_STATUS_DIRTY;
1067 }
1068 }
1069
1070 /* We have to flush the shaders before we change the border color
1071 * registers, or previous draw commands that haven't completed yet
1072 * will end up using the new border color. */
1073 if (dirty & R600_BLOCK_STATUS_DIRTY)
1074 r600_context_ps_partial_flush(ctx);
1075
1076 r600_context_dirty_block(ctx, block, dirty, 3);
1077 }
1078
1079 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1080 {
1081 unsigned offset;
1082
1083 offset = 0x0003C000 + id * 0xc;
1084 r600_context_pipe_state_set_sampler(ctx, state, offset);
1085 offset = 0x0000A400 + id * 0x10;
1086 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1087 }
1088
1089 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1090 {
1091 unsigned offset;
1092
1093 offset = 0x0003C0D8 + id * 0xc;
1094 r600_context_pipe_state_set_sampler(ctx, state, offset);
1095 offset = 0x0000A600 + id * 0x10;
1096 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1097 }
1098
1099 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1100 {
1101 struct r600_range *range;
1102 struct r600_block *block;
1103 unsigned id;
1104
1105 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
1106 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
1107 offset -= block->start_offset;
1108 id = block->pm4_bo_index[offset >> 2];
1109 if (block->reloc[id].bo) {
1110 return block->reloc[id].bo;
1111 }
1112 return NULL;
1113 }
1114
1115 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1116 {
1117 int id;
1118
1119 if (block->nreg_dirty == 0 && block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS)) {
1120 goto out;
1121 }
1122
1123 for (int j = 0; j < block->nreg; j++) {
1124 if (block->pm4_bo_index[j]) {
1125 /* find relocation */
1126 id = block->pm4_bo_index[j];
1127 if (block->reloc[id].bo) {
1128 r600_context_bo_reloc(ctx,
1129 &block->pm4[block->reloc[id].bo_pm4_index],
1130 block->reloc[id].bo);
1131 r600_context_bo_flush(ctx,
1132 block->reloc[id].flush_flags,
1133 block->reloc[id].flush_mask,
1134 block->reloc[id].bo);
1135 }
1136 }
1137 }
1138 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4);
1139 ctx->pm4_cdwords += block->pm4_ndwords;
1140
1141 if (block->nreg_dirty != block->nreg && block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS)) {
1142 int new_dwords = block->nreg_dirty;
1143 uint32_t oldword, newword;
1144 ctx->pm4_cdwords -= block->pm4_ndwords;
1145 newword = oldword = ctx->pm4[ctx->pm4_cdwords];
1146 newword &= PKT_COUNT_C;
1147 newword |= PKT_COUNT_S(new_dwords);
1148 ctx->pm4[ctx->pm4_cdwords] = newword;
1149 ctx->pm4_cdwords += new_dwords + 2;
1150 }
1151 out:
1152 block->status ^= R600_BLOCK_STATUS_DIRTY;
1153 block->nreg_dirty = 0;
1154 LIST_DELINIT(&block->list);
1155 }
1156
1157 void r600_context_flush_dest_caches(struct r600_context *ctx)
1158 {
1159 struct r600_bo *cb[8];
1160 struct r600_bo *db;
1161
1162 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1163 return;
1164
1165 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1166 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1167 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1168 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1169 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1170 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1171 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1172 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1173 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1174
1175 /* flush the color buffers */
1176 for (int i = 0; i < 8; i++) {
1177 if (!cb[i])
1178 continue;
1179
1180 r600_context_bo_flush(ctx,
1181 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1182 S_0085F0_CB_ACTION_ENA(1),
1183 0, cb[i]);
1184 }
1185 if (db) {
1186 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1), 0, db);
1187 }
1188
1189 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1190 }
1191
1192 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1193 {
1194 unsigned ndwords = 7;
1195 struct r600_block *dirty_block = NULL;
1196 struct r600_block *next_block;
1197 unsigned rv6xx_surface_base_update = 0;
1198
1199 if (draw->indices) {
1200 ndwords = 11;
1201 /* make sure there is enough relocation space before scheduling draw */
1202 if (ctx->creloc >= (ctx->nreloc - 1)) {
1203 r600_context_flush(ctx);
1204 }
1205 }
1206
1207 /* rv6xx surface base update */
1208 if ((ctx->radeon->family > CHIP_R600) &&
1209 (ctx->radeon->family < CHIP_RV770)) {
1210 struct r600_bo *cb[8];
1211 struct r600_bo *db;
1212
1213 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1214 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1215 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1216 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1217 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1218 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1219 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1220 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1221 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1222 for (int i = 0; i < 8; i++) {
1223 if (cb[i]) {
1224 rv6xx_surface_base_update |= SURFACE_BASE_UPDATE_COLOR(i);
1225 }
1226 }
1227 if (db) {
1228 rv6xx_surface_base_update |= SURFACE_BASE_UPDATE_DEPTH;
1229 }
1230 }
1231
1232 /* XXX also need to update SURFACE_BASE_UPDATE_STRMOUT when we support it */
1233
1234 /* queries need some special values */
1235 if (ctx->num_query_running) {
1236 if (ctx->radeon->family >= CHIP_RV770) {
1237 r600_context_reg(ctx,
1238 R_028D0C_DB_RENDER_CONTROL,
1239 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1240 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1241 }
1242 r600_context_reg(ctx,
1243 R_028D10_DB_RENDER_OVERRIDE,
1244 S_028D10_NOOP_CULL_DISABLE(1),
1245 S_028D10_NOOP_CULL_DISABLE(1));
1246 }
1247
1248 /* update the max dword count to make sure we have enough space
1249 * reserved for flushing the destination caches */
1250 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4 - ctx->num_dest_buffers * 7 - 16;
1251
1252 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1253 /* need to flush */
1254 r600_context_flush(ctx);
1255 }
1256 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1257 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1258 R600_ERR("context is too big to be scheduled\n");
1259 return;
1260 }
1261 /* enough room to copy packet */
1262 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1263 r600_context_block_emit_dirty(ctx, dirty_block);
1264 }
1265
1266 /* rv6xx surface base udpate */
1267 if (rv6xx_surface_base_update)
1268 rv6xx_context_surface_base_update(ctx, rv6xx_surface_base_update);
1269
1270 /* draw packet */
1271 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1272 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
1273 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1274 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
1275 if (draw->indices) {
1276 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1277 ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1278 ctx->pm4[ctx->pm4_cdwords++] = 0;
1279 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1280 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1281 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1282 ctx->pm4[ctx->pm4_cdwords++] = 0;
1283 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
1284 } else {
1285 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1286 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1287 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1288 }
1289
1290 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1291
1292 /* all dirty state have been scheduled in current cs */
1293 ctx->pm4_dirty_cdwords = 0;
1294 }
1295
1296 void r600_context_flush(struct r600_context *ctx)
1297 {
1298 struct drm_radeon_cs drmib = {};
1299 struct drm_radeon_cs_chunk chunks[2];
1300 uint64_t chunk_array[2];
1301 unsigned fence;
1302 int r;
1303
1304 if (!ctx->pm4_cdwords)
1305 return;
1306
1307 /* suspend queries */
1308 r600_context_queries_suspend(ctx);
1309
1310 if (ctx->radeon->family >= CHIP_CEDAR)
1311 evergreen_context_flush_dest_caches(ctx);
1312 else
1313 r600_context_flush_dest_caches(ctx);
1314
1315 /* partial flush is needed to avoid lockups on some chips with user fences */
1316 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1317 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1318 /* emit fence */
1319 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1320 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1321 ctx->pm4[ctx->pm4_cdwords++] = 0;
1322 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1323 ctx->pm4[ctx->pm4_cdwords++] = ctx->radeon->fence;
1324 ctx->pm4[ctx->pm4_cdwords++] = 0;
1325 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1326 ctx->pm4[ctx->pm4_cdwords++] = 0;
1327 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->radeon->fence_bo);
1328
1329 #if 1
1330 /* emit cs */
1331 drmib.num_chunks = 2;
1332 drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1333 chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1334 chunks[0].length_dw = ctx->pm4_cdwords;
1335 chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1336 chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1337 chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1338 chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1339 chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1340 chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1341 r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1342 sizeof(struct drm_radeon_cs));
1343 #else
1344 *ctx->radeon->cfence = ctx->radeon->fence;
1345 #endif
1346
1347 r600_context_update_fenced_list(ctx);
1348
1349 fence = ctx->radeon->fence + 1;
1350 if (fence < ctx->radeon->fence) {
1351 /* wrap around */
1352 fence = 1;
1353 r600_context_fence_wraparound(ctx, fence);
1354 }
1355 ctx->radeon->fence = fence;
1356
1357 /* restart */
1358 for (int i = 0; i < ctx->creloc; i++) {
1359 ctx->bo[i]->reloc = NULL;
1360 ctx->bo[i]->last_flush = 0;
1361 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1362 }
1363 ctx->creloc = 0;
1364 ctx->pm4_dirty_cdwords = 0;
1365 ctx->pm4_cdwords = 0;
1366 ctx->flags = 0;
1367
1368 /* resume queries */
1369 r600_context_queries_resume(ctx);
1370
1371 /* set all valid group as dirty so they get reemited on
1372 * next draw command
1373 */
1374 for (int i = 0; i < ctx->nblocks; i++) {
1375 if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) {
1376 if(!(ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY)) {
1377 LIST_ADDTAIL(&ctx->blocks[i]->list,&ctx->dirty);
1378 }
1379 ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords + ctx->blocks[i]->pm4_flush_ndwords;
1380 ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY;
1381 ctx->blocks[i]->nreg_dirty = ctx->blocks[i]->nreg;
1382 }
1383 }
1384 }
1385
1386 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence_bo, unsigned offset, unsigned value)
1387 {
1388 unsigned ndwords = 10;
1389
1390 if (((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) ||
1391 (ctx->creloc >= (ctx->nreloc - 1))) {
1392 /* need to flush */
1393 r600_context_flush(ctx);
1394 }
1395
1396 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1397 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1398 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1399 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1400 ctx->pm4[ctx->pm4_cdwords++] = offset << 2; /* ADDRESS_LO */
1401 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */
1402 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */
1403 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */
1404 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1405 ctx->pm4[ctx->pm4_cdwords++] = 0;
1406 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], fence_bo);
1407 }
1408
1409 void r600_context_dump_bof(struct r600_context *ctx, const char *file)
1410 {
1411 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
1412 unsigned i;
1413
1414 root = device_id = bcs = blob = array = bo = size = handle = NULL;
1415 root = bof_object();
1416 if (root == NULL)
1417 goto out_err;
1418 device_id = bof_int32(ctx->radeon->device);
1419 if (device_id == NULL)
1420 goto out_err;
1421 if (bof_object_set(root, "device_id", device_id))
1422 goto out_err;
1423 bof_decref(device_id);
1424 device_id = NULL;
1425 /* dump relocs */
1426 blob = bof_blob(ctx->creloc * 16, ctx->reloc);
1427 if (blob == NULL)
1428 goto out_err;
1429 if (bof_object_set(root, "reloc", blob))
1430 goto out_err;
1431 bof_decref(blob);
1432 blob = NULL;
1433 /* dump cs */
1434 blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
1435 if (blob == NULL)
1436 goto out_err;
1437 if (bof_object_set(root, "pm4", blob))
1438 goto out_err;
1439 bof_decref(blob);
1440 blob = NULL;
1441 /* dump bo */
1442 array = bof_array();
1443 if (array == NULL)
1444 goto out_err;
1445 for (i = 0; i < ctx->creloc; i++) {
1446 struct radeon_bo *rbo = ctx->bo[i];
1447 bo = bof_object();
1448 if (bo == NULL)
1449 goto out_err;
1450 size = bof_int32(rbo->size);
1451 if (size == NULL)
1452 goto out_err;
1453 if (bof_object_set(bo, "size", size))
1454 goto out_err;
1455 bof_decref(size);
1456 size = NULL;
1457 handle = bof_int32(rbo->handle);
1458 if (handle == NULL)
1459 goto out_err;
1460 if (bof_object_set(bo, "handle", handle))
1461 goto out_err;
1462 bof_decref(handle);
1463 handle = NULL;
1464 radeon_bo_map(ctx->radeon, rbo);
1465 blob = bof_blob(rbo->size, rbo->data);
1466 radeon_bo_unmap(ctx->radeon, rbo);
1467 if (blob == NULL)
1468 goto out_err;
1469 if (bof_object_set(bo, "data", blob))
1470 goto out_err;
1471 bof_decref(blob);
1472 blob = NULL;
1473 if (bof_array_append(array, bo))
1474 goto out_err;
1475 bof_decref(bo);
1476 bo = NULL;
1477 }
1478 if (bof_object_set(root, "bo", array))
1479 goto out_err;
1480 bof_dump_file(root, file);
1481 out_err:
1482 bof_decref(blob);
1483 bof_decref(array);
1484 bof_decref(bo);
1485 bof_decref(size);
1486 bof_decref(handle);
1487 bof_decref(device_id);
1488 bof_decref(root);
1489 }
1490
1491 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1492 {
1493 u64 start, end;
1494 u32 *results;
1495 int i;
1496 int size;
1497
1498 if (wait)
1499 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_CPU_READ, NULL);
1500 else
1501 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_READ, NULL);
1502 if (!results)
1503 return FALSE;
1504
1505 size = query->num_results * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1506 for (i = 0; i < size; i += 4) {
1507 start = (u64)results[i] | (u64)results[i + 1] << 32;
1508 end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
1509 if (((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))
1510 || query->type == PIPE_QUERY_TIME_ELAPSED) {
1511 query->result += end - start;
1512 }
1513 }
1514 r600_bo_unmap(ctx->radeon, query->buffer);
1515 query->num_results = 0;
1516
1517 return TRUE;
1518 }
1519
1520 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1521 {
1522 unsigned required_space;
1523 int num_backends = r600_get_num_backends(ctx->radeon);
1524
1525 /* query request needs 6/8 dwords for begin + 6/8 dwords for end */
1526 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1527 required_space = 16;
1528 else
1529 required_space = 12;
1530
1531 if ((required_space + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1532 /* need to flush */
1533 r600_context_flush(ctx);
1534 }
1535
1536 /* if query buffer is full force a flush */
1537 if (query->num_results*4 >= query->buffer_size - 16) {
1538 r600_context_flush(ctx);
1539 r600_query_result(ctx, query, TRUE);
1540 }
1541
1542 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER &&
1543 num_backends > 0 && num_backends < ctx->max_db) {
1544 /* as per info on ZPASS the driver must set the unusued DB top bits */
1545 u32 *results;
1546 int i;
1547
1548 results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_WRITE, NULL);
1549 if (results) {
1550 memset(results + (query->num_results * 4), 0, ctx->max_db * 4 * 4);
1551
1552 for (i = num_backends; i < ctx->max_db; i++) {
1553 results[(i * 4)+1] = 0x80000000;
1554 results[(i * 4)+3] = 0x80000000;
1555 }
1556 r600_bo_unmap(ctx->radeon, query->buffer);
1557 }
1558 }
1559
1560 /* emit begin query */
1561 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1562 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1563 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1564 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1565 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1566 ctx->pm4[ctx->pm4_cdwords++] = 0;
1567 ctx->pm4[ctx->pm4_cdwords++] = 0;
1568 } else {
1569 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1570 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1571 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + r600_bo_offset(query->buffer);
1572 ctx->pm4[ctx->pm4_cdwords++] = 0;
1573 }
1574 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1575 ctx->pm4[ctx->pm4_cdwords++] = 0;
1576 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1577
1578 query->state |= R600_QUERY_STATE_STARTED;
1579 query->state ^= R600_QUERY_STATE_ENDED;
1580 ctx->num_query_running++;
1581 }
1582
1583 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1584 {
1585 /* emit begin query */
1586 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1587 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1588 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1589 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1590 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1591 ctx->pm4[ctx->pm4_cdwords++] = 0;
1592 ctx->pm4[ctx->pm4_cdwords++] = 0;
1593 } else {
1594 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1595 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1596 ctx->pm4[ctx->pm4_cdwords++] = query->num_results*4 + 8 + r600_bo_offset(query->buffer);
1597 ctx->pm4[ctx->pm4_cdwords++] = 0;
1598 }
1599 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1600 ctx->pm4[ctx->pm4_cdwords++] = 0;
1601 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1602
1603 query->num_results += 4 * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
1604 query->state ^= R600_QUERY_STATE_STARTED;
1605 query->state |= R600_QUERY_STATE_ENDED;
1606 ctx->num_query_running--;
1607 }
1608
1609 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1610 int flag_wait)
1611 {
1612 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1613
1614 if (operation == PREDICATION_OP_CLEAR) {
1615 ctx->pm4[ctx->pm4_cdwords++] = 0;
1616 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1617 } else {
1618 int results_base = query->num_results - (4 * ctx->max_db);
1619
1620 if (results_base < 0)
1621 results_base = 0;
1622
1623 ctx->pm4[ctx->pm4_cdwords++] = results_base*4 + r600_bo_offset(query->buffer);
1624 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(operation) | (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW) | PREDICATION_DRAW_VISIBLE;
1625 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1626 ctx->pm4[ctx->pm4_cdwords++] = 0;
1627 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1628 }
1629 }
1630
1631 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1632 {
1633 struct r600_query *query;
1634
1635 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER && query_type != PIPE_QUERY_TIME_ELAPSED)
1636 return NULL;
1637
1638 query = calloc(1, sizeof(struct r600_query));
1639 if (query == NULL)
1640 return NULL;
1641
1642 query->type = query_type;
1643 query->buffer_size = 4096;
1644
1645 /* As of GL4, query buffers are normally read by the CPU after
1646 * being written by the gpu, hence staging is probably a good
1647 * usage pattern.
1648 */
1649 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1650 PIPE_USAGE_STAGING);
1651 if (!query->buffer) {
1652 free(query);
1653 return NULL;
1654 }
1655
1656 LIST_ADDTAIL(&query->list, &ctx->query_list);
1657
1658 return query;
1659 }
1660
1661 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1662 {
1663 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1664 LIST_DELINIT(&query->list);
1665 free(query);
1666 }
1667
1668 boolean r600_context_query_result(struct r600_context *ctx,
1669 struct r600_query *query,
1670 boolean wait, void *vresult)
1671 {
1672 uint64_t *result = (uint64_t*)vresult;
1673
1674 if (query->num_results) {
1675 r600_context_flush(ctx);
1676 }
1677 if (!r600_query_result(ctx, query, wait))
1678 return FALSE;
1679 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1680 *result = (1000000*query->result)/r600_get_clock_crystal_freq(ctx->radeon);
1681 else
1682 *result = query->result;
1683 query->result = 0;
1684 return TRUE;
1685 }
1686
1687 void r600_context_queries_suspend(struct r600_context *ctx)
1688 {
1689 struct r600_query *query;
1690
1691 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1692 if (query->state & R600_QUERY_STATE_STARTED) {
1693 r600_query_end(ctx, query);
1694 query->state |= R600_QUERY_STATE_SUSPENDED;
1695 }
1696 }
1697 }
1698
1699 void r600_context_queries_resume(struct r600_context *ctx)
1700 {
1701 struct r600_query *query;
1702
1703 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1704 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1705 r600_query_begin(ctx, query);
1706 query->state ^= R600_QUERY_STATE_SUSPENDED;
1707 }
1708 }
1709 }