src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #include "radeon_drm_bo.h"
  29 #include "radeon_drm_cs.h"
  30 #include "radeon_drm_public.h"
  31
  32 #include "util/u_cpu_detect.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_hash_table.h"
  35 #include "util/u_pointer.h"
  36
  37 #include <xf86drm.h>
  38 #include <stdio.h>
  39 #include <sys/types.h>
  40 #include <sys/stat.h>
  41 #include <unistd.h>
  42 #include <fcntl.h>
  43 #include <radeon_surface.h>
  44
  45 static struct hash_table *fd_tab = NULL;
  46 static mtx_t fd_tab_mutex = _MTX_INITIALIZER_NP;
  47
  48 /* Enable/disable feature access for one command stream.
  49  * If enable == true, return true on success.
  50  * Otherwise, return false.
  51  *
  52  * We basically do the same thing kernel does, because we have to deal
  53  * with multiple contexts (here command streams) backed by one winsys. */
  54 static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
  55                                  struct radeon_drm_cs **owner,
  56                                  mtx_t *mutex,
  57                                  unsigned request, const char *request_name,
  58                                  bool enable)
  59 {
  60    struct drm_radeon_info info;
  61    unsigned value = enable ? 1 : 0;
  62
  63    memset(&info, 0, sizeof(info));
  64
  65    mtx_lock(&*mutex);
  66
  67    /* Early exit if we are sure the request will fail. */
  68    if (enable) {
  69       if (*owner) {
  70          mtx_unlock(&*mutex);
  71          return false;
  72       }
  73    } else {
  74       if (*owner != applier) {
  75          mtx_unlock(&*mutex);
  76          return false;
  77       }
  78    }
  79
  80    /* Pass through the request to the kernel. */
  81    info.value = (unsigned long)&value;
  82    info.request = request;
  83    if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
  84                            &info, sizeof(info)) != 0) {
  85       mtx_unlock(&*mutex);
  86       return false;
  87    }
  88
  89    /* Update the rights in the winsys. */
  90    if (enable) {
  91       if (value) {
  92          *owner = applier;
  93          mtx_unlock(&*mutex);
  94          return true;
  95       }
  96    } else {
  97       *owner = NULL;
  98    }
  99
 100    mtx_unlock(&*mutex);
 101    return false;
 102 }
 103
 104 static bool radeon_get_drm_value(int fd, unsigned request,
 105                                  const char *errname, uint32_t *out)
 106 {
 107    struct drm_radeon_info info;
 108    int retval;
 109
 110    memset(&info, 0, sizeof(info));
 111
 112    info.value = (unsigned long)out;
 113    info.request = request;
 114
 115    retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 116    if (retval) {
 117       if (errname) {
 118          fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 119                  errname, retval);
 120       }
 121       return false;
 122    }
 123    return true;
 124 }
 125
 126 /* Helper function to do the ioctls needed for setup and init. */
 127 static bool do_winsys_init(struct radeon_drm_winsys *ws)
 128 {
 129    struct drm_radeon_gem_info gem_info;
 130    int retval;
 131    drmVersionPtr version;
 132
 133    memset(&gem_info, 0, sizeof(gem_info));
 134
 135    /* We do things in a specific order here.
 136     *
 137     * DRM version first. We need to be sure we're running on a KMS chipset.
 138     * This is also for some features.
 139     *
 140     * Then, the PCI ID. This is essential and should return usable numbers
 141     * for all Radeons. If this fails, we probably got handed an FD for some
 142     * non-Radeon card.
 143     *
 144     * The GEM info is actually bogus on the kernel side, as well as our side
 145     * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 146     * we don't actually use the info for anything yet.
 147     *
 148     * The GB and Z pipe requests should always succeed, but they might not
 149     * return sensical values for all chipsets, but that's alright because
 150     * the pipe drivers already know that.
 151     */
 152
 153    /* Get DRM version. */
 154    version = drmGetVersion(ws->fd);
 155    if (version->version_major != 2 ||
 156        version->version_minor < 12) {
 157       fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 158                       "only compatible with 2.12.0 (kernel 3.2) or later.\n",
 159               __FUNCTION__,
 160               version->version_major,
 161               version->version_minor,
 162               version->version_patchlevel);
 163       drmFreeVersion(version);
 164       return false;
 165    }
 166
 167    ws->info.drm_major = version->version_major;
 168    ws->info.drm_minor = version->version_minor;
 169    ws->info.drm_patchlevel = version->version_patchlevel;
 170    ws->info.is_amdgpu = false;
 171    drmFreeVersion(version);
 172
 173    /* Get PCI ID. */
 174    if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 175                              &ws->info.pci_id))
 176       return false;
 177
 178    /* Check PCI ID. */
 179    switch (ws->info.pci_id) {
 180 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 181 #include "pci_ids/r300_pci_ids.h"
 182 #undef CHIPSET
 183
 184 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 185 #include "pci_ids/r600_pci_ids.h"
 186 #undef CHIPSET
 187
 188 #define CHIPSET(pci_id, cfamily) \
 189    case pci_id: \
 190    ws->info.family = CHIP_##cfamily; \
 191    ws->info.name = #cfamily; \
 192    ws->gen = DRV_SI; \
 193    break;
 194 #include "pci_ids/radeonsi_pci_ids.h"
 195 #undef CHIPSET
 196
 197    default:
 198       fprintf(stderr, "radeon: Invalid PCI ID.\n");
 199       return false;
 200    }
 201
 202    switch (ws->info.family) {
 203    default:
 204    case CHIP_UNKNOWN:
 205       fprintf(stderr, "radeon: Unknown family.\n");
 206       return false;
 207    case CHIP_R300:
 208    case CHIP_R350:
 209    case CHIP_RV350:
 210    case CHIP_RV370:
 211    case CHIP_RV380:
 212    case CHIP_RS400:
 213    case CHIP_RC410:
 214    case CHIP_RS480:
 215       ws->info.chip_class = R300;
 216       break;
 217    case CHIP_R420:     /* R4xx-based cores. */
 218    case CHIP_R423:
 219    case CHIP_R430:
 220    case CHIP_R480:
 221    case CHIP_R481:
 222    case CHIP_RV410:
 223    case CHIP_RS600:
 224    case CHIP_RS690:
 225    case CHIP_RS740:
 226       ws->info.chip_class = R400;
 227       break;
 228    case CHIP_RV515:    /* R5xx-based cores. */
 229    case CHIP_R520:
 230    case CHIP_RV530:
 231    case CHIP_R580:
 232    case CHIP_RV560:
 233    case CHIP_RV570:
 234       ws->info.chip_class = R500;
 235       break;
 236    case CHIP_R600:
 237    case CHIP_RV610:
 238    case CHIP_RV630:
 239    case CHIP_RV670:
 240    case CHIP_RV620:
 241    case CHIP_RV635:
 242    case CHIP_RS780:
 243    case CHIP_RS880:
 244       ws->info.chip_class = R600;
 245       break;
 246    case CHIP_RV770:
 247    case CHIP_RV730:
 248    case CHIP_RV710:
 249    case CHIP_RV740:
 250       ws->info.chip_class = R700;
 251       break;
 252    case CHIP_CEDAR:
 253    case CHIP_REDWOOD:
 254    case CHIP_JUNIPER:
 255    case CHIP_CYPRESS:
 256    case CHIP_HEMLOCK:
 257    case CHIP_PALM:
 258    case CHIP_SUMO:
 259    case CHIP_SUMO2:
 260    case CHIP_BARTS:
 261    case CHIP_TURKS:
 262    case CHIP_CAICOS:
 263       ws->info.chip_class = EVERGREEN;
 264       break;
 265    case CHIP_CAYMAN:
 266    case CHIP_ARUBA:
 267       ws->info.chip_class = CAYMAN;
 268       break;
 269    case CHIP_TAHITI:
 270    case CHIP_PITCAIRN:
 271    case CHIP_VERDE:
 272    case CHIP_OLAND:
 273    case CHIP_HAINAN:
 274       ws->info.chip_class = GFX6;
 275       break;
 276    case CHIP_BONAIRE:
 277    case CHIP_KAVERI:
 278    case CHIP_KABINI:
 279    case CHIP_HAWAII:
 280       ws->info.chip_class = GFX7;
 281       break;
 282    }
 283
 284    /* Set which chips don't have dedicated VRAM. */
 285    switch (ws->info.family) {
 286    case CHIP_RS400:
 287    case CHIP_RC410:
 288    case CHIP_RS480:
 289    case CHIP_RS600:
 290    case CHIP_RS690:
 291    case CHIP_RS740:
 292    case CHIP_RS780:
 293    case CHIP_RS880:
 294    case CHIP_PALM:
 295    case CHIP_SUMO:
 296    case CHIP_SUMO2:
 297    case CHIP_ARUBA:
 298    case CHIP_KAVERI:
 299    case CHIP_KABINI:
 300       ws->info.has_dedicated_vram = false;
 301       break;
 302
 303    default:
 304       ws->info.has_dedicated_vram = true;
 305    }
 306
 307    ws->info.num_rings[RING_GFX] = 1;
 308    /* Check for dma */
 309    ws->info.num_rings[RING_DMA] = 0;
 310    /* DMA is disabled on R700. There is IB corruption and hangs. */
 311    if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 312       ws->info.num_rings[RING_DMA] = 1;
 313    }
 314
 315    /* Check for UVD and VCE */
 316    ws->info.has_hw_decode = false;
 317    ws->info.vce_fw_version = 0x00000000;
 318    if (ws->info.drm_minor >= 32) {
 319       uint32_t value = RADEON_CS_RING_UVD;
 320       if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 321                                "UVD Ring working", &value)) {
 322          ws->info.has_hw_decode = value;
 323          ws->info.num_rings[RING_UVD] = 1;
 324       }
 325
 326       value = RADEON_CS_RING_VCE;
 327       if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 328                                NULL, &value) && value) {
 329
 330          if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 331                                   "VCE FW version", &value)) {
 332             ws->info.vce_fw_version = value;
 333             ws->info.num_rings[RING_VCE] = 1;
 334          }
 335       }
 336    }
 337
 338    /* Check for userptr support. */
 339    {
 340       struct drm_radeon_gem_userptr args = {0};
 341
 342       /* If the ioctl doesn't exist, -EINVAL is returned.
 343        *
 344        * If the ioctl exists, it should return -EACCES
 345        * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 346        * aren't set.
 347        */
 348       ws->info.has_userptr =
 349             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 350                                 &args, sizeof(args)) == -EACCES;
 351    }
 352
 353    /* Get GEM info. */
 354    retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 355                                 &gem_info, sizeof(gem_info));
 356    if (retval) {
 357       fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 358               retval);
 359       return false;
 360    }
 361    ws->info.gart_size = gem_info.gart_size;
 362    ws->info.vram_size = gem_info.vram_size;
 363    ws->info.vram_vis_size = gem_info.vram_visible;
 364    /* Older versions of the kernel driver reported incorrect values, and
 365     * didn't support more than 256MB of visible VRAM anyway
 366     */
 367    if (ws->info.drm_minor < 49)
 368       ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);
 369
 370    /* Radeon allocates all buffers contiguously, which makes large allocations
 371     * unlikely to succeed. */
 372    if (ws->info.has_dedicated_vram)
 373       ws->info.max_alloc_size = ws->info.vram_size * 0.7;
 374    else
 375       ws->info.max_alloc_size = ws->info.gart_size * 0.7;
 376
 377    if (ws->info.drm_minor < 40)
 378       ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
 379    /* Both 32-bit and 64-bit address spaces only have 4GB. */
 380    ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 3ull*1024*1024*1024);
 381
 382    /* Get max clock frequency info and convert it to MHz */
 383    radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 384                         &ws->info.max_shader_clock);
 385    ws->info.max_shader_clock /= 1000;
 386
 387    ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 388
 389    /* Generation-specific queries. */
 390    if (ws->gen == DRV_R300) {
 391       if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 392                                 "GB pipe count",
 393                                 &ws->info.r300_num_gb_pipes))
 394          return false;
 395
 396       if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 397                                 "Z pipe count",
 398                                 &ws->info.r300_num_z_pipes))
 399          return false;
 400    }
 401    else if (ws->gen >= DRV_R600) {
 402       uint32_t tiling_config = 0;
 403
 404       if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 405                                 "num backends",
 406                                 &ws->info.num_render_backends))
 407          return false;
 408
 409       /* get the GPU counter frequency, failure is not fatal */
 410       radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 411                            &ws->info.clock_crystal_freq);
 412
 413       radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 414                            &tiling_config);
 415
 416       ws->info.r600_num_banks =
 417             ws->info.chip_class >= EVERGREEN ?
 418                4 << ((tiling_config & 0xf0) >> 4) :
 419                     4 << ((tiling_config & 0x30) >> 4);
 420
 421       ws->info.pipe_interleave_bytes =
 422             ws->info.chip_class >= EVERGREEN ?
 423                256 << ((tiling_config & 0xf00) >> 8) :
 424                       256 << ((tiling_config & 0xc0) >> 6);
 425
 426       if (!ws->info.pipe_interleave_bytes)
 427          ws->info.pipe_interleave_bytes =
 428                ws->info.chip_class >= EVERGREEN ? 512 : 256;
 429
 430       radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 431                            &ws->info.num_tile_pipes);
 432
 433       /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
 434        * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
 435        * reports a different value (12). Fix it by setting what's in the
 436        * GB_TILE_MODE array (8).
 437        */
 438       if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
 439          ws->info.num_tile_pipes = 8;
 440
 441       if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 442                                &ws->info.r600_gb_backend_map))
 443          ws->info.r600_gb_backend_map_valid = true;
 444
 445       /* Default value. */
 446       ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends);
 447       /*
 448        * This fails (silently) on non-GCN or older kernels, overwriting the
 449        * default enabled_rb_mask with the result of the last query.
 450        */
 451       if (ws->gen >= DRV_SI)
 452          radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 453                               &ws->info.enabled_rb_mask);
 454
 455       ws->info.r600_has_virtual_memory = false;
 456       if (ws->info.drm_minor >= 13) {
 457          uint32_t ib_vm_max_size;
 458
 459          ws->info.r600_has_virtual_memory = true;
 460          if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 461                                    &ws->va_start))
 462             ws->info.r600_has_virtual_memory = false;
 463          if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 464                                    &ib_vm_max_size))
 465             ws->info.r600_has_virtual_memory = false;
 466          radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 467                               &ws->va_unmap_working);
 468       }
 469       if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
 470          ws->info.r600_has_virtual_memory = false;
 471    }
 472
 473    /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 474     * chips have at least 2 pipes, so we use 2 as a default. */
 475    ws->info.r600_max_quad_pipes = 2;
 476    radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 477                         &ws->info.r600_max_quad_pipes);
 478
 479    /* All GPUs have at least one compute unit */
 480    ws->info.num_good_compute_units = 1;
 481    radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 482                         &ws->info.num_good_compute_units);
 483
 484    radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 485                         &ws->info.max_se);
 486
 487    switch (ws->info.family) {
 488    case CHIP_HAINAN:
 489    case CHIP_KABINI:
 490       ws->info.num_tcc_blocks = 2;
 491       break;
 492    case CHIP_VERDE:
 493    case CHIP_OLAND:
 494    case CHIP_BONAIRE:
 495    case CHIP_KAVERI:
 496       ws->info.num_tcc_blocks = 4;
 497       break;
 498    case CHIP_PITCAIRN:
 499       ws->info.num_tcc_blocks = 8;
 500       break;
 501    case CHIP_TAHITI:
 502       ws->info.num_tcc_blocks = 12;
 503       break;
 504    case CHIP_HAWAII:
 505       ws->info.num_tcc_blocks = 16;
 506       break;
 507    default:
 508       ws->info.num_tcc_blocks = 0;
 509       break;
 510    }
 511
 512    if (!ws->info.max_se) {
 513       switch (ws->info.family) {
 514       default:
 515          ws->info.max_se = 1;
 516          break;
 517       case CHIP_CYPRESS:
 518       case CHIP_HEMLOCK:
 519       case CHIP_BARTS:
 520       case CHIP_CAYMAN:
 521       case CHIP_TAHITI:
 522       case CHIP_PITCAIRN:
 523       case CHIP_BONAIRE:
 524          ws->info.max_se = 2;
 525          break;
 526       case CHIP_HAWAII:
 527          ws->info.max_se = 4;
 528          break;
 529       }
 530    }
 531
 532    radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 533                         &ws->info.max_sh_per_se);
 534    if (ws->gen == DRV_SI) {
 535       ws->info.max_good_cu_per_sa =
 536       ws->info.min_good_cu_per_sa = ws->info.num_good_compute_units /
 537                                     (ws->info.max_se * ws->info.max_sh_per_se);
 538    }
 539
 540    radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 541                         &ws->accel_working2);
 542    if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 543       fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 544                       "returned accel_working2 value %u is smaller than 2. "
 545                       "Please install a newer kernel.\n",
 546               ws->accel_working2);
 547       return false;
 548    }
 549
 550    if (ws->info.chip_class == GFX7) {
 551       if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 552                                 ws->info.cik_macrotile_mode_array)) {
 553          fprintf(stderr, "radeon: Kernel 3.13 is required for Sea Islands support.\n");
 554          return false;
 555       }
 556    }
 557
 558    if (ws->info.chip_class >= GFX6) {
 559       if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 560                                 ws->info.si_tile_mode_array)) {
 561          fprintf(stderr, "radeon: Kernel 3.10 is required for Southern Islands support.\n");
 562          return false;
 563       }
 564    }
 565
 566    /* Hawaii with old firmware needs type2 nop packet.
 567     * accel_working2 with value 3 indicates the new firmware.
 568     */
 569    ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= GFX6 ||
 570                                     (ws->info.family == CHIP_HAWAII &&
 571                                      ws->accel_working2 < 3);
 572    ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 573    ws->info.ib_alignment = 4096;
 574    ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
 575    /* HTILE is broken with 1D tiling on old kernels and GFX7. */
 576    ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != GFX7 ||
 577                                                                    ws->info.drm_minor >= 38;
 578    ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
 579    ws->info.has_bo_metadata = false;
 580    ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
 581    ws->info.has_eqaa_surface_allocator = false;
 582    ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
 583    ws->info.kernel_flushes_tc_l2_after_ib = true;
 584    /* Old kernels disallowed register writes via COPY_DATA
 585     * that are used for indirect compute dispatches. */
 586    ws->info.has_indirect_compute_dispatch = ws->info.chip_class == GFX7 ||
 587                                             (ws->info.chip_class == GFX6 &&
 588                                              ws->info.drm_minor >= 45);
 589    /* GFX6 doesn't support unaligned loads. */
 590    ws->info.has_unaligned_shader_loads = ws->info.chip_class == GFX7 &&
 591                                          ws->info.drm_minor >= 50;
 592    ws->info.has_sparse_vm_mappings = false;
 593    /* 2D tiling on GFX7 is supported since DRM 2.35.0 */
 594    ws->info.has_2d_tiling = ws->info.chip_class <= GFX6 || ws->info.drm_minor >= 35;
 595    ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
 596    ws->info.max_alignment = 1024*1024;
 597    ws->info.has_graphics = true;
 598    ws->info.cpdma_prefetch_writes_memory = true;
 599    ws->info.max_wave64_per_simd = 10;
 600    ws->info.num_physical_sgprs_per_simd = 512;
 601    ws->info.num_physical_wave64_vgprs_per_simd = 256;
 602    /* Potential hang on Kabini: */
 603    ws->info.use_late_alloc = ws->info.family != CHIP_KABINI;
 604
 605    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
 606                                                                             strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL;
 607
 608    return true;
 609 }
 610
 611 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 612 {
 613    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 614
 615    if (util_queue_is_initialized(&ws->cs_queue))
 616       util_queue_destroy(&ws->cs_queue);
 617
 618    mtx_destroy(&ws->hyperz_owner_mutex);
 619    mtx_destroy(&ws->cmask_owner_mutex);
 620
 621    if (ws->info.r600_has_virtual_memory)
 622       pb_slabs_deinit(&ws->bo_slabs);
 623    pb_cache_deinit(&ws->bo_cache);
 624
 625    if (ws->gen >= DRV_R600) {
 626       radeon_surface_manager_free(ws->surf_man);
 627    }
 628
 629    _mesa_hash_table_destroy(ws->bo_names, NULL);
 630    _mesa_hash_table_destroy(ws->bo_handles, NULL);
 631    _mesa_hash_table_destroy(ws->bo_vas, NULL);
 632    mtx_destroy(&ws->bo_handles_mutex);
 633    mtx_destroy(&ws->vm32.mutex);
 634    mtx_destroy(&ws->vm64.mutex);
 635    mtx_destroy(&ws->bo_fence_lock);
 636
 637    if (ws->fd >= 0)
 638       close(ws->fd);
 639
 640    FREE(rws);
 641 }
 642
 643 static void radeon_query_info(struct radeon_winsys *rws,
 644                               struct radeon_info *info)
 645 {
 646    *info = ((struct radeon_drm_winsys *)rws)->info;
 647 }
 648
 649 static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs,
 650                                       enum radeon_feature_id fid,
 651                                       bool enable)
 652 {
 653    struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 654
 655    switch (fid) {
 656    case RADEON_FID_R300_HYPERZ_ACCESS:
 657       return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 658                                   &cs->ws->hyperz_owner_mutex,
 659                                   RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 660                                   enable);
 661
 662    case RADEON_FID_R300_CMASK_ACCESS:
 663       return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 664                                   &cs->ws->cmask_owner_mutex,
 665                                   RADEON_INFO_WANT_CMASK, "AA optimizations",
 666                                   enable);
 667    }
 668    return false;
 669 }
 670
 671 uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws)
 672 {
 673    uint64_t retval = 0;
 674
 675    if (!ws->info.has_gpu_reset_status_query)
 676       return 0;
 677
 678    radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 679                         "gpu-reset-counter", (uint32_t*)&retval);
 680    return retval;
 681 }
 682
 683 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 684                                    enum radeon_value_id value)
 685 {
 686    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 687    uint64_t retval = 0;
 688
 689    switch (value) {
 690    case RADEON_REQUESTED_VRAM_MEMORY:
 691       return ws->allocated_vram;
 692    case RADEON_REQUESTED_GTT_MEMORY:
 693       return ws->allocated_gtt;
 694    case RADEON_MAPPED_VRAM:
 695       return ws->mapped_vram;
 696    case RADEON_MAPPED_GTT:
 697       return ws->mapped_gtt;
 698    case RADEON_BUFFER_WAIT_TIME_NS:
 699       return ws->buffer_wait_time;
 700    case RADEON_NUM_MAPPED_BUFFERS:
 701       return ws->num_mapped_buffers;
 702    case RADEON_TIMESTAMP:
 703       if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 704          assert(0);
 705          return 0;
 706       }
 707
 708       radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 709                            (uint32_t*)&retval);
 710       return retval;
 711    case RADEON_NUM_GFX_IBS:
 712       return ws->num_gfx_IBs;
 713    case RADEON_NUM_SDMA_IBS:
 714       return ws->num_sdma_IBs;
 715    case RADEON_NUM_BYTES_MOVED:
 716       radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 717                            "num-bytes-moved", (uint32_t*)&retval);
 718       return retval;
 719    case RADEON_NUM_EVICTIONS:
 720    case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 721    case RADEON_VRAM_VIS_USAGE:
 722    case RADEON_GFX_BO_LIST_COUNTER:
 723    case RADEON_GFX_IB_SIZE_COUNTER:
 724       return 0; /* unimplemented */
 725    case RADEON_VRAM_USAGE:
 726       radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 727                            "vram-usage", (uint32_t*)&retval);
 728       return retval;
 729    case RADEON_GTT_USAGE:
 730       radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 731                            "gtt-usage", (uint32_t*)&retval);
 732       return retval;
 733    case RADEON_GPU_TEMPERATURE:
 734       radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 735                            "gpu-temp", (uint32_t*)&retval);
 736       return retval;
 737    case RADEON_CURRENT_SCLK:
 738       radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 739                            "current-gpu-sclk", (uint32_t*)&retval);
 740       return retval;
 741    case RADEON_CURRENT_MCLK:
 742       radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 743                            "current-gpu-mclk", (uint32_t*)&retval);
 744       return retval;
 745    case RADEON_CS_THREAD_TIME:
 746       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 747    }
 748    return 0;
 749 }
 750
 751 static bool radeon_read_registers(struct radeon_winsys *rws,
 752                                   unsigned reg_offset,
 753                                   unsigned num_registers, uint32_t *out)
 754 {
 755    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 756    unsigned i;
 757
 758    for (i = 0; i < num_registers; i++) {
 759       uint32_t reg = reg_offset + i*4;
 760
 761       if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 762          return false;
 763       out[i] = reg;
 764    }
 765    return true;
 766 }
 767
 768 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true)
 769
 770 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 771 {
 772    struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 773    bool destroy;
 774
 775    /* When the reference counter drops to zero, remove the fd from the table.
 776     * This must happen while the mutex is locked, so that
 777     * radeon_drm_winsys_create in another thread doesn't get the winsys
 778     * from the table when the counter drops to 0. */
 779    mtx_lock(&fd_tab_mutex);
 780
 781    destroy = pipe_reference(&rws->reference, NULL);
 782    if (destroy && fd_tab) {
 783       _mesa_hash_table_remove_key(fd_tab, intptr_to_pointer(rws->fd));
 784       if (_mesa_hash_table_num_entries(fd_tab) == 0) {
 785          _mesa_hash_table_destroy(fd_tab, NULL);
 786          fd_tab = NULL;
 787       }
 788    }
 789
 790    mtx_unlock(&fd_tab_mutex);
 791    return destroy;
 792 }
 793
 794 static void radeon_pin_threads_to_L3_cache(struct radeon_winsys *ws,
 795                                            unsigned cache)
 796 {
 797    struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 798
 799    if (util_queue_is_initialized(&rws->cs_queue)) {
 800       util_pin_thread_to_L3(rws->cs_queue.threads[0], cache,
 801             util_cpu_caps.cores_per_L3);
 802    }
 803 }
 804
 805 static bool radeon_ws_is_secure(struct radeon_winsys* ws)
 806 {
 807     return false;
 808 }
 809
 810 static bool radeon_cs_is_secure(struct radeon_cmdbuf* cs)
 811 {
 812     return false;
 813 }
 814
 815 static void radeon_cs_set_secure(struct radeon_cmdbuf* cs, bool enable)
 816 {
 817 }
 818
 819 PUBLIC struct radeon_winsys *
 820 radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
 821                          radeon_screen_create_t screen_create)
 822 {
 823    struct radeon_drm_winsys *ws;
 824
 825    mtx_lock(&fd_tab_mutex);
 826    if (!fd_tab) {
 827       fd_tab = util_hash_table_create_fd_keys();
 828    }
 829
 830    ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 831    if (ws) {
 832       pipe_reference(NULL, &ws->reference);
 833       mtx_unlock(&fd_tab_mutex);
 834       return &ws->base;
 835    }
 836
 837    ws = CALLOC_STRUCT(radeon_drm_winsys);
 838    if (!ws) {
 839       mtx_unlock(&fd_tab_mutex);
 840       return NULL;
 841    }
 842
 843    ws->fd = fcntl(fd, F_DUPFD_CLOEXEC, 3);
 844
 845    if (!do_winsys_init(ws))
 846       goto fail1;
 847
 848    pb_cache_init(&ws->bo_cache, RADEON_MAX_CACHED_HEAPS,
 849                  500000, ws->check_vm ? 1.0f : 2.0f, 0,
 850                  MIN2(ws->info.vram_size, ws->info.gart_size),
 851                  radeon_bo_destroy,
 852                  radeon_bo_can_reclaim);
 853
 854    if (ws->info.r600_has_virtual_memory) {
 855       /* There is no fundamental obstacle to using slab buffer allocation
 856        * without GPUVM, but enabling it requires making sure that the drivers
 857        * honor the address offset.
 858        */
 859       if (!pb_slabs_init(&ws->bo_slabs,
 860                          RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2,
 861                          RADEON_MAX_SLAB_HEAPS,
 862                          ws,
 863                          radeon_bo_can_reclaim_slab,
 864                          radeon_bo_slab_alloc,
 865                          radeon_bo_slab_free))
 866          goto fail_cache;
 867
 868       ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2;
 869    } else {
 870       ws->info.min_alloc_size = ws->info.gart_page_size;
 871    }
 872
 873    if (ws->gen >= DRV_R600) {
 874       ws->surf_man = radeon_surface_manager_new(ws->fd);
 875       if (!ws->surf_man)
 876          goto fail_slab;
 877    }
 878
 879    /* init reference */
 880    pipe_reference_init(&ws->reference, 1);
 881
 882    /* Set functions. */
 883    ws->base.unref = radeon_winsys_unref;
 884    ws->base.destroy = radeon_winsys_destroy;
 885    ws->base.query_info = radeon_query_info;
 886    ws->base.pin_threads_to_L3_cache = radeon_pin_threads_to_L3_cache;
 887    ws->base.cs_request_feature = radeon_cs_request_feature;
 888    ws->base.query_value = radeon_query_value;
 889    ws->base.read_registers = radeon_read_registers;
 890     ws->base.ws_is_secure = radeon_ws_is_secure;
 891     ws->base.cs_is_secure = radeon_cs_is_secure;
 892     ws->base.cs_set_secure = radeon_cs_set_secure;
 893
 894    radeon_drm_bo_init_functions(ws);
 895    radeon_drm_cs_init_functions(ws);
 896    radeon_surface_init_functions(ws);
 897
 898    (void) mtx_init(&ws->hyperz_owner_mutex, mtx_plain);
 899    (void) mtx_init(&ws->cmask_owner_mutex, mtx_plain);
 900
 901    ws->bo_names = util_hash_table_create_ptr_keys();
 902    ws->bo_handles = util_hash_table_create_ptr_keys();
 903    ws->bo_vas = util_hash_table_create_ptr_keys();
 904    (void) mtx_init(&ws->bo_handles_mutex, mtx_plain);
 905    (void) mtx_init(&ws->vm32.mutex, mtx_plain);
 906    (void) mtx_init(&ws->vm64.mutex, mtx_plain);
 907    (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 908    list_inithead(&ws->vm32.holes);
 909    list_inithead(&ws->vm64.holes);
 910
 911    /* The kernel currently returns 8MB. Make sure this doesn't change. */
 912    if (ws->va_start > 8 * 1024 * 1024) {
 913       /* Not enough 32-bit address space. */
 914       radeon_winsys_destroy(&ws->base);
 915       mtx_unlock(&fd_tab_mutex);
 916       return NULL;
 917    }
 918
 919    ws->vm32.start = ws->va_start;
 920    ws->vm32.end = 1ull << 32;
 921
 922    /* The maximum is 8GB of virtual address space limited by the kernel.
 923     * It's obviously not enough for bigger cards, like Hawaiis with 4GB
 924     * and 8GB of physical memory and 4GB of GART.
 925     *
 926     * Older kernels set the limit to 4GB, which is even worse, so they only
 927     * have 32-bit address space.
 928     */
 929    if (ws->info.drm_minor >= 41) {
 930       ws->vm64.start = 1ull << 32;
 931       ws->vm64.end = 1ull << 33;
 932    }
 933
 934    /* TTM aligns the BO size to the CPU page size */
 935    ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
 936    ws->info.pte_fragment_size = 64 * 1024; /* GPUVM page size */
 937
 938    if (ws->num_cpus > 1 && debug_get_option_thread())
 939       util_queue_init(&ws->cs_queue, "rcs", 8, 1, 0);
 940
 941    /* Create the screen at the end. The winsys must be initialized
 942     * completely.
 943     *
 944     * Alternatively, we could create the screen based on "ws->gen"
 945     * and link all drivers into one binary blob. */
 946    ws->base.screen = screen_create(&ws->base, config);
 947    if (!ws->base.screen) {
 948       radeon_winsys_destroy(&ws->base);
 949       mtx_unlock(&fd_tab_mutex);
 950       return NULL;
 951    }
 952
 953    _mesa_hash_table_insert(fd_tab, intptr_to_pointer(ws->fd), ws);
 954
 955    /* We must unlock the mutex once the winsys is fully initialized, so that
 956     * other threads attempting to create the winsys from the same fd will
 957     * get a fully initialized winsys and not just half-way initialized. */
 958    mtx_unlock(&fd_tab_mutex);
 959
 960    return &ws->base;
 961
 962 fail_slab:
 963    if (ws->info.r600_has_virtual_memory)
 964       pb_slabs_deinit(&ws->bo_slabs);
 965 fail_cache:
 966    pb_cache_deinit(&ws->bo_cache);
 967 fail1:
 968    mtx_unlock(&fd_tab_mutex);
 969    if (ws->surf_man)
 970       radeon_surface_manager_free(ws->surf_man);
 971    if (ws->fd >= 0)
 972       close(ws->fd);
 973
 974    FREE(ws);
 975    return NULL;
 976 }