src/intel/compiler/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_shader.h"
  26 #include "brw_eu.h"
  27 #include "dev/gen_debug.h"
  28 #include "compiler/nir/nir.h"
  29 #include "main/errors.h"
  30 #include "util/debug.h"
  31
  32 #define COMMON_OPTIONS                                                        \
  33    .lower_sub = true,                                                         \
  34    .lower_fdiv = true,                                                        \
  35    .lower_scmp = true,                                                        \
  36    .lower_flrp16 = true,                                                      \
  37    .lower_fmod = true,                                                        \
  38    .lower_bitfield_extract = true,                                            \
  39    .lower_bitfield_insert = true,                                             \
  40    .lower_uadd_carry = true,                                                  \
  41    .lower_usub_borrow = true,                                                 \
  42    .lower_fdiv = true,                                                        \
  43    .lower_flrp64 = true,                                                      \
  44    .lower_isign = true,                                                       \
  45    .lower_ldexp = true,                                                       \
  46    .lower_device_index_to_zero = true,                                        \
  47    .vectorize_io = true,                                                      \
  48    .use_interpolated_input_intrinsics = true,                                 \
  49    .vertex_id_zero_based = true,                                              \
  50    .lower_base_vertex = true
  51
  52 #define COMMON_SCALAR_OPTIONS                                                 \
  53    .lower_pack_half_2x16 = true,                                              \
  54    .lower_pack_snorm_2x16 = true,                                             \
  55    .lower_pack_snorm_4x8 = true,                                              \
  56    .lower_pack_unorm_2x16 = true,                                             \
  57    .lower_pack_unorm_4x8 = true,                                              \
  58    .lower_unpack_half_2x16 = true,                                            \
  59    .lower_unpack_snorm_2x16 = true,                                           \
  60    .lower_unpack_snorm_4x8 = true,                                            \
  61    .lower_unpack_unorm_2x16 = true,                                           \
  62    .lower_unpack_unorm_4x8 = true,                                            \
  63    .max_unroll_iterations = 32
  64
  65 static const struct nir_shader_compiler_options scalar_nir_options = {
  66    COMMON_OPTIONS,
  67    COMMON_SCALAR_OPTIONS,
  68 };
  69
  70 static const struct nir_shader_compiler_options vector_nir_options = {
  71    COMMON_OPTIONS,
  72
  73    /* In the vec4 backend, our dpN instruction replicates its result to all the
  74     * components of a vec4.  We would like NIR to give us replicated fdot
  75     * instructions because it can optimize better for us.
  76     */
  77    .fdot_replicates = true,
  78
  79    .lower_pack_snorm_2x16 = true,
  80    .lower_pack_unorm_2x16 = true,
  81    .lower_unpack_snorm_2x16 = true,
  82    .lower_unpack_unorm_2x16 = true,
  83    .lower_extract_byte = true,
  84    .lower_extract_word = true,
  85    .intel_vec4 = true,
  86    .max_unroll_iterations = 32,
  87 };
  88
  89 struct brw_compiler *
  90 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
  91 {
  92    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  93
  94    compiler->devinfo = devinfo;
  95
  96    brw_fs_alloc_reg_sets(compiler);
  97    brw_vec4_alloc_reg_set(compiler);
  98    brw_init_compaction_tables(devinfo);
  99
 100    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 101
 102    compiler->use_tcs_8_patch =
 103       devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH);
 104
 105    if (devinfo->gen >= 10) {
 106       /* We don't support vec4 mode on Cannonlake. */
 107       for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
 108          compiler->scalar_stage[i] = true;
 109    } else {
 110       compiler->scalar_stage[MESA_SHADER_VERTEX] =
 111          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
 112       compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 113          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 114       compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 115          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 116       compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 117          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 118       compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 119       compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 120    }
 121
 122    nir_lower_int64_options int64_options =
 123       nir_lower_imul64 |
 124       nir_lower_isign64 |
 125       nir_lower_divmod64 |
 126       nir_lower_imul_high64;
 127    nir_lower_doubles_options fp64_options =
 128       nir_lower_drcp |
 129       nir_lower_dsqrt |
 130       nir_lower_drsq |
 131       nir_lower_dtrunc |
 132       nir_lower_dfloor |
 133       nir_lower_dceil |
 134       nir_lower_dfract |
 135       nir_lower_dround_even |
 136       nir_lower_dmod;
 137
 138    if (!devinfo->has_64bit_types || (INTEL_DEBUG & DEBUG_SOFT64)) {
 139       int64_options |= nir_lower_mov64 |
 140                        nir_lower_icmp64 |
 141                        nir_lower_iadd64 |
 142                        nir_lower_iabs64 |
 143                        nir_lower_ineg64 |
 144                        nir_lower_logic64 |
 145                        nir_lower_minmax64 |
 146                        nir_lower_shift64 |
 147                        nir_lower_extract64;
 148       fp64_options |= nir_lower_fp64_full_software;
 149    }
 150
 151    /* The Bspec's section tittled "Instruction_multiply[DevBDW+]" claims that
 152     * destination type can be Quadword and source type Doubleword for Gen8 and
 153     * Gen9. So, lower 64 bit multiply instruction on rest of the platforms.
 154     */
 155    if (devinfo->gen < 8 || devinfo->gen > 9)
 156       int64_options |= nir_lower_imul_2x32_64;
 157
 158    /* We want the GLSL compiler to emit code that uses condition codes */
 159    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 160       compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
 161       compiler->glsl_compiler_options[i].MaxIfDepth =
 162          devinfo->gen < 6 ? 16 : UINT_MAX;
 163
 164       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 165       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 166
 167       bool is_scalar = compiler->scalar_stage[i];
 168
 169       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 170       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 171       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 172
 173       struct nir_shader_compiler_options *nir_options =
 174          rzalloc(compiler, struct nir_shader_compiler_options);
 175       if (is_scalar) {
 176          *nir_options = scalar_nir_options;
 177       } else {
 178          *nir_options = vector_nir_options;
 179       }
 180
 181       /* Prior to Gen6, there are no three source operations, and Gen11 loses
 182        * LRP.
 183        */
 184       nir_options->lower_ffma = devinfo->gen < 6;
 185       nir_options->lower_flrp32 = devinfo->gen < 6 || devinfo->gen >= 11;
 186
 187       nir_options->lower_rotate = devinfo->gen < 11;
 188
 189       nir_options->lower_int64_options = int64_options;
 190       nir_options->lower_doubles_options = fp64_options;
 191       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 192
 193       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
 194    }
 195
 196    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 197    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 198    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 199
 200    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 201       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 202
 203    return compiler;
 204 }
 205
 206 static void
 207 insert_u64_bit(uint64_t *val, bool add)
 208 {
 209    *val = (*val << 1) | !!add;
 210 }
 211
 212 uint64_t
 213 brw_get_compiler_config_value(const struct brw_compiler *compiler)
 214 {
 215    uint64_t config = 0;
 216    insert_u64_bit(&config, compiler->precise_trig);
 217    if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) {
 218       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
 219       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
 220       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
 221       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
 222    }
 223    uint64_t debug_bits = INTEL_DEBUG;
 224    uint64_t mask = DEBUG_DISK_CACHE_MASK;
 225    while (mask != 0) {
 226       const uint64_t bit = 1ULL << (ffsll(mask) - 1);
 227       insert_u64_bit(&config, (debug_bits & bit) != 0);
 228       mask &= ~bit;
 229    }
 230    return config;
 231 }
 232
 233 unsigned
 234 brw_prog_data_size(gl_shader_stage stage)
 235 {
 236    STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
 237    STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1);
 238    STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2);
 239    STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3);
 240    STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4);
 241    STATIC_ASSERT(MESA_SHADER_COMPUTE == 5);
 242    static const size_t stage_sizes[] = {
 243       sizeof(struct brw_vs_prog_data),
 244       sizeof(struct brw_tcs_prog_data),
 245       sizeof(struct brw_tes_prog_data),
 246       sizeof(struct brw_gs_prog_data),
 247       sizeof(struct brw_wm_prog_data),
 248       sizeof(struct brw_cs_prog_data),
 249    };
 250    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 251    return stage_sizes[stage];
 252 }
 253
 254 unsigned
 255 brw_prog_key_size(gl_shader_stage stage)
 256 {
 257    static const size_t stage_sizes[] = {
 258       sizeof(struct brw_vs_prog_key),
 259       sizeof(struct brw_tcs_prog_key),
 260       sizeof(struct brw_tes_prog_key),
 261       sizeof(struct brw_gs_prog_key),
 262       sizeof(struct brw_wm_prog_key),
 263       sizeof(struct brw_cs_prog_key),
 264    };
 265    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 266    return stage_sizes[stage];
 267 }