src/intel/compiler/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_shader.h"
  26 #include "brw_eu.h"
  27 #include "common/gen_debug.h"
  28 #include "compiler/nir/nir.h"
  29 #include "main/errors.h"
  30 #include "util/debug.h"
  31
  32 #define COMMON_OPTIONS                                                        \
  33    .lower_sub = true,                                                         \
  34    .lower_fdiv = true,                                                        \
  35    .lower_scmp = true,                                                        \
  36    .lower_fmod32 = true,                                                      \
  37    .lower_fmod64 = false,                                                     \
  38    .lower_bitfield_extract = true,                                            \
  39    .lower_bitfield_insert = true,                                             \
  40    .lower_uadd_carry = true,                                                  \
  41    .lower_usub_borrow = true,                                                 \
  42    .lower_fdiv = true,                                                        \
  43    .lower_flrp64 = true,                                                      \
  44    .lower_ldexp = true,                                                       \
  45    .lower_device_index_to_zero = true,                                        \
  46    .native_integers = true,                                                   \
  47    .use_interpolated_input_intrinsics = true,                                 \
  48    .vertex_id_zero_based = true
  49
  50 #define COMMON_SCALAR_OPTIONS                                                 \
  51    .lower_pack_half_2x16 = true,                                              \
  52    .lower_pack_snorm_2x16 = true,                                             \
  53    .lower_pack_snorm_4x8 = true,                                              \
  54    .lower_pack_unorm_2x16 = true,                                             \
  55    .lower_pack_unorm_4x8 = true,                                              \
  56    .lower_unpack_half_2x16 = true,                                            \
  57    .lower_unpack_snorm_2x16 = true,                                           \
  58    .lower_unpack_snorm_4x8 = true,                                            \
  59    .lower_unpack_unorm_2x16 = true,                                           \
  60    .lower_unpack_unorm_4x8 = true,                                            \
  61    .vs_inputs_dual_locations = true,                                          \
  62    .max_unroll_iterations = 32
  63
  64 static const struct nir_shader_compiler_options scalar_nir_options = {
  65    COMMON_OPTIONS,
  66    COMMON_SCALAR_OPTIONS,
  67 };
  68
  69 static const struct nir_shader_compiler_options scalar_nir_options_gen11 = {
  70    COMMON_OPTIONS,
  71    COMMON_SCALAR_OPTIONS,
  72    .lower_flrp32 = true,
  73 };
  74
  75 static const struct nir_shader_compiler_options vector_nir_options = {
  76    COMMON_OPTIONS,
  77
  78    /* In the vec4 backend, our dpN instruction replicates its result to all the
  79     * components of a vec4.  We would like NIR to give us replicated fdot
  80     * instructions because it can optimize better for us.
  81     */
  82    .fdot_replicates = true,
  83
  84    /* Prior to Gen6, there are no three source operations for SIMD4x2. */
  85    .lower_flrp32 = true,
  86
  87    .lower_pack_snorm_2x16 = true,
  88    .lower_pack_unorm_2x16 = true,
  89    .lower_unpack_snorm_2x16 = true,
  90    .lower_unpack_unorm_2x16 = true,
  91    .lower_extract_byte = true,
  92    .lower_extract_word = true,
  93    .vs_inputs_dual_locations = true,
  94    .max_unroll_iterations = 32,
  95 };
  96
  97 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
  98    COMMON_OPTIONS,
  99
 100    /* In the vec4 backend, our dpN instruction replicates its result to all the
 101     * components of a vec4.  We would like NIR to give us replicated fdot
 102     * instructions because it can optimize better for us.
 103     */
 104    .fdot_replicates = true,
 105
 106    .lower_pack_snorm_2x16 = true,
 107    .lower_pack_unorm_2x16 = true,
 108    .lower_unpack_snorm_2x16 = true,
 109    .lower_unpack_unorm_2x16 = true,
 110    .lower_extract_byte = true,
 111    .lower_extract_word = true,
 112    .vs_inputs_dual_locations = true,
 113    .max_unroll_iterations = 32,
 114 };
 115
 116 struct brw_compiler *
 117 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
 118 {
 119    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 120
 121    compiler->devinfo = devinfo;
 122
 123    brw_fs_alloc_reg_sets(compiler);
 124    brw_vec4_alloc_reg_set(compiler);
 125    brw_init_compaction_tables(devinfo);
 126
 127    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 128
 129    if (devinfo->gen >= 10) {
 130       /* We don't support vec4 mode on Cannonlake. */
 131       for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
 132          compiler->scalar_stage[i] = true;
 133    } else {
 134       compiler->scalar_stage[MESA_SHADER_VERTEX] =
 135          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
 136       compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 137          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 138       compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 139          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 140       compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 141          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 142       compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 143       compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 144    }
 145
 146    /* We want the GLSL compiler to emit code that uses condition codes */
 147    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 148       compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
 149       compiler->glsl_compiler_options[i].MaxIfDepth =
 150          devinfo->gen < 6 ? 16 : UINT_MAX;
 151
 152       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 153       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 154
 155       bool is_scalar = compiler->scalar_stage[i];
 156
 157       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 158       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 159       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 160
 161       if (is_scalar) {
 162          compiler->glsl_compiler_options[i].NirOptions =
 163             devinfo->gen < 11 ? &scalar_nir_options : &scalar_nir_options_gen11;
 164       } else {
 165          compiler->glsl_compiler_options[i].NirOptions =
 166             devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
 167       }
 168
 169       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 170       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
 171    }
 172
 173    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 174    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 175    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 176
 177    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 178       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 179
 180    return compiler;
 181 }
 182
 183 unsigned
 184 brw_prog_data_size(gl_shader_stage stage)
 185 {
 186    STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
 187    STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1);
 188    STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2);
 189    STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3);
 190    STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4);
 191    STATIC_ASSERT(MESA_SHADER_COMPUTE == 5);
 192    static const size_t stage_sizes[] = {
 193       sizeof(struct brw_vs_prog_data),
 194       sizeof(struct brw_tcs_prog_data),
 195       sizeof(struct brw_tes_prog_data),
 196       sizeof(struct brw_gs_prog_data),
 197       sizeof(struct brw_wm_prog_data),
 198       sizeof(struct brw_cs_prog_data),
 199    };
 200    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 201    return stage_sizes[stage];
 202 }
 203
 204 unsigned
 205 brw_prog_key_size(gl_shader_stage stage)
 206 {
 207    static const size_t stage_sizes[] = {
 208       sizeof(struct brw_vs_prog_key),
 209       sizeof(struct brw_tcs_prog_key),
 210       sizeof(struct brw_tes_prog_key),
 211       sizeof(struct brw_gs_prog_key),
 212       sizeof(struct brw_wm_prog_key),
 213       sizeof(struct brw_cs_prog_key),
 214    };
 215    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 216    return stage_sizes[stage];
 217 }