src/intel/compiler/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_shader.h"
  26 #include "brw_eu.h"
  27 #include "common/gen_debug.h"
  28 #include "compiler/nir/nir.h"
  29 #include "main/errors.h"
  30 #include "util/debug.h"
  31
  32 #define COMMON_OPTIONS                                                        \
  33    .lower_sub = true,                                                         \
  34    .lower_fdiv = true,                                                        \
  35    .lower_scmp = true,                                                        \
  36    .lower_fmod32 = true,                                                      \
  37    .lower_fmod64 = false,                                                     \
  38    .lower_bitfield_extract = true,                                            \
  39    .lower_bitfield_insert = true,                                             \
  40    .lower_uadd_carry = true,                                                  \
  41    .lower_usub_borrow = true,                                                 \
  42    .lower_fdiv = true,                                                        \
  43    .lower_flrp64 = true,                                                      \
  44    .lower_ldexp = true,                                                       \
  45    .native_integers = true,                                                   \
  46    .use_interpolated_input_intrinsics = true,                                 \
  47    .vertex_id_zero_based = true
  48
  49 static const struct nir_shader_compiler_options scalar_nir_options = {
  50    COMMON_OPTIONS,
  51    .lower_pack_half_2x16 = true,
  52    .lower_pack_snorm_2x16 = true,
  53    .lower_pack_snorm_4x8 = true,
  54    .lower_pack_unorm_2x16 = true,
  55    .lower_pack_unorm_4x8 = true,
  56    .lower_unpack_half_2x16 = true,
  57    .lower_unpack_snorm_2x16 = true,
  58    .lower_unpack_snorm_4x8 = true,
  59    .lower_unpack_unorm_2x16 = true,
  60    .lower_unpack_unorm_4x8 = true,
  61    .vs_inputs_dual_locations = true,
  62    .max_unroll_iterations = 32,
  63 };
  64
  65 static const struct nir_shader_compiler_options vector_nir_options = {
  66    COMMON_OPTIONS,
  67
  68    /* In the vec4 backend, our dpN instruction replicates its result to all the
  69     * components of a vec4.  We would like NIR to give us replicated fdot
  70     * instructions because it can optimize better for us.
  71     */
  72    .fdot_replicates = true,
  73
  74    /* Prior to Gen6, there are no three source operations for SIMD4x2. */
  75    .lower_flrp32 = true,
  76
  77    .lower_pack_snorm_2x16 = true,
  78    .lower_pack_unorm_2x16 = true,
  79    .lower_unpack_snorm_2x16 = true,
  80    .lower_unpack_unorm_2x16 = true,
  81    .lower_extract_byte = true,
  82    .lower_extract_word = true,
  83    .vs_inputs_dual_locations = true,
  84    .max_unroll_iterations = 32,
  85 };
  86
  87 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
  88    COMMON_OPTIONS,
  89
  90    /* In the vec4 backend, our dpN instruction replicates its result to all the
  91     * components of a vec4.  We would like NIR to give us replicated fdot
  92     * instructions because it can optimize better for us.
  93     */
  94    .fdot_replicates = true,
  95
  96    .lower_pack_snorm_2x16 = true,
  97    .lower_pack_unorm_2x16 = true,
  98    .lower_unpack_snorm_2x16 = true,
  99    .lower_unpack_unorm_2x16 = true,
 100    .lower_extract_byte = true,
 101    .lower_extract_word = true,
 102    .vs_inputs_dual_locations = true,
 103    .max_unroll_iterations = 32,
 104 };
 105
 106 struct brw_compiler *
 107 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
 108 {
 109    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 110
 111    compiler->devinfo = devinfo;
 112
 113    brw_fs_alloc_reg_sets(compiler);
 114    brw_vec4_alloc_reg_set(compiler);
 115    brw_init_compaction_tables(devinfo);
 116
 117    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 118
 119    if (devinfo->gen >= 10) {
 120       /* We don't support vec4 mode on Cannonlake. */
 121       for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
 122          compiler->scalar_stage[i] = true;
 123    } else {
 124       compiler->scalar_stage[MESA_SHADER_VERTEX] =
 125          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
 126       compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 127          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 128       compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 129          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 130       compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 131          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 132       compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 133       compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 134    }
 135
 136    /* We want the GLSL compiler to emit code that uses condition codes */
 137    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 138       compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
 139       compiler->glsl_compiler_options[i].MaxIfDepth =
 140          devinfo->gen < 6 ? 16 : UINT_MAX;
 141
 142       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 143       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 144
 145       bool is_scalar = compiler->scalar_stage[i];
 146
 147       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 148       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 149       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 150
 151       if (is_scalar) {
 152          compiler->glsl_compiler_options[i].NirOptions = &scalar_nir_options;
 153       } else {
 154          compiler->glsl_compiler_options[i].NirOptions =
 155             devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
 156       }
 157
 158       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 159       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
 160    }
 161
 162    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 163    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 164    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 165
 166    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 167       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 168
 169    return compiler;
 170 }
 171
 172 unsigned
 173 brw_prog_data_size(gl_shader_stage stage)
 174 {
 175    STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
 176    STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1);
 177    STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2);
 178    STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3);
 179    STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4);
 180    STATIC_ASSERT(MESA_SHADER_COMPUTE == 5);
 181    static const size_t stage_sizes[] = {
 182       sizeof(struct brw_vs_prog_data),
 183       sizeof(struct brw_tcs_prog_data),
 184       sizeof(struct brw_tes_prog_data),
 185       sizeof(struct brw_gs_prog_data),
 186       sizeof(struct brw_wm_prog_data),
 187       sizeof(struct brw_cs_prog_data),
 188    };
 189    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 190    return stage_sizes[stage];
 191 }
 192
 193 unsigned
 194 brw_prog_key_size(gl_shader_stage stage)
 195 {
 196    static const size_t stage_sizes[] = {
 197       sizeof(struct brw_vs_prog_key),
 198       sizeof(struct brw_tcs_prog_key),
 199       sizeof(struct brw_tes_prog_key),
 200       sizeof(struct brw_gs_prog_key),
 201       sizeof(struct brw_wm_prog_key),
 202       sizeof(struct brw_cs_prog_key),
 203    };
 204    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 205    return stage_sizes[stage];
 206 }