intel/eu: Add a mechanism for emitting relocatable constant MOVs
[mesa.git] / src / intel / compiler / brw_compiler.h
1 /*
2 * Copyright © 2010 - 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
26
27 #include <stdio.h>
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 struct ra_regs;
38 struct nir_shader;
39 struct brw_program;
40
41 struct brw_compiler {
42 const struct gen_device_info *devinfo;
43
44 struct {
45 struct ra_regs *regs;
46
47 /**
48 * Array of the ra classes for the unaligned contiguous register
49 * block sizes used.
50 */
51 int *classes;
52
53 /**
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
56 */
57 uint8_t *ra_reg_to_grf;
58 } vec4_reg_set;
59
60 struct {
61 struct ra_regs *regs;
62
63 /**
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
66 */
67 int classes[16];
68
69 /**
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
76 */
77 int class_to_ra_reg_range[17];
78
79 /**
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
82 */
83 uint8_t *ra_reg_to_grf;
84
85 /**
86 * ra class for the aligned barycentrics we use for PLN, which doesn't
87 * appear in *classes.
88 */
89 int aligned_bary_class;
90 } fs_reg_sets[3];
91
92 void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
94
95 bool scalar_stage[MESA_ALL_SHADER_STAGES];
96 bool use_tcs_8_patch;
97 struct gl_shader_compiler_options glsl_compiler_options[MESA_ALL_SHADER_STAGES];
98
99 /**
100 * Apply workarounds for SIN and COS output range problems.
101 * This can negatively impact performance.
102 */
103 bool precise_trig;
104
105 /**
106 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
107 * Base Address? (If not, it's a normal GPU address.)
108 */
109 bool constant_buffer_0_is_relative;
110
111 /**
112 * Whether or not the driver supports pull constants. If not, the compiler
113 * will attempt to push everything.
114 */
115 bool supports_pull_constants;
116
117 /**
118 * Whether or not the driver supports NIR shader constants. This controls
119 * whether nir_opt_large_constants will be run.
120 */
121 bool supports_shader_constants;
122
123 /**
124 * Whether or not the driver wants uniform params to be compacted by the
125 * back-end compiler.
126 */
127 bool compact_params;
128
129 /**
130 * Whether or not the driver wants variable group size to be lowered by the
131 * back-end compiler.
132 */
133 bool lower_variable_group_size;
134 };
135
136 /**
137 * We use a constant subgroup size of 32. It really only needs to be a
138 * maximum and, since we do SIMD32 for compute shaders in some cases, it
139 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
140 * subgroup size of 32 but will act as if 16 or 24 of those channels are
141 * disabled.
142 */
143 #define BRW_SUBGROUP_SIZE 32
144
145 /**
146 * Program key structures.
147 *
148 * When drawing, we look for the currently bound shaders in the program
149 * cache. This is essentially a hash table lookup, and these are the keys.
150 *
151 * Sometimes OpenGL features specified as state need to be simulated via
152 * shader code, due to a mismatch between the API and the hardware. This
153 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
154 * in the program key so it's considered when searching for a program. If
155 * we haven't seen a particular combination before, we have to recompile a
156 * new specialized version.
157 *
158 * Shader compilation should not look up state in gl_context directly, but
159 * instead use the copy in the program key. This guarantees recompiles will
160 * happen correctly.
161 *
162 * @{
163 */
164
165 enum PACKED gen6_gather_sampler_wa {
166 WA_SIGN = 1, /* whether we need to sign extend */
167 WA_8BIT = 2, /* if we have an 8bit format needing wa */
168 WA_16BIT = 4, /* if we have a 16bit format needing wa */
169 };
170
171 /**
172 * Sampler information needed by VS, WM, and GS program cache keys.
173 */
174 struct brw_sampler_prog_key_data {
175 /**
176 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
177 */
178 uint16_t swizzles[MAX_SAMPLERS];
179
180 uint32_t gl_clamp_mask[3];
181
182 /**
183 * For RG32F, gather4's channel select is broken.
184 */
185 uint32_t gather_channel_quirk_mask;
186
187 /**
188 * Whether this sampler uses the compressed multisample surface layout.
189 */
190 uint32_t compressed_multisample_layout_mask;
191
192 /**
193 * Whether this sampler is using 16x multisampling. If so fetching from
194 * this sampler will be handled with a different instruction, ld2dms_w
195 * instead of ld2dms.
196 */
197 uint32_t msaa_16;
198
199 /**
200 * For Sandybridge, which shader w/a we need for gather quirks.
201 */
202 enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS];
203
204 /**
205 * Texture units that have a YUV image bound.
206 */
207 uint32_t y_u_v_image_mask;
208 uint32_t y_uv_image_mask;
209 uint32_t yx_xuxv_image_mask;
210 uint32_t xy_uxvx_image_mask;
211 uint32_t ayuv_image_mask;
212 uint32_t xyuv_image_mask;
213 uint32_t bt709_mask;
214 uint32_t bt2020_mask;
215
216 /* Scale factor for each texture. */
217 float scale_factors[32];
218 };
219
220 /** An enum representing what kind of input gl_SubgroupSize is. */
221 enum PACKED brw_subgroup_size_type
222 {
223 BRW_SUBGROUP_SIZE_API_CONSTANT, /**< Default Vulkan behavior */
224 BRW_SUBGROUP_SIZE_UNIFORM, /**< OpenGL behavior */
225 BRW_SUBGROUP_SIZE_VARYING, /**< VK_EXT_subgroup_size_control */
226
227 /* These enums are specifically chosen so that the value of the enum is
228 * also the subgroup size. If any new values are added, they must respect
229 * this invariant.
230 */
231 BRW_SUBGROUP_SIZE_REQUIRE_8 = 8, /**< VK_EXT_subgroup_size_control */
232 BRW_SUBGROUP_SIZE_REQUIRE_16 = 16, /**< VK_EXT_subgroup_size_control */
233 BRW_SUBGROUP_SIZE_REQUIRE_32 = 32, /**< VK_EXT_subgroup_size_control */
234 };
235
236 struct brw_base_prog_key {
237 unsigned program_string_id;
238
239 enum brw_subgroup_size_type subgroup_size_type;
240
241 struct brw_sampler_prog_key_data tex;
242 };
243
244 /**
245 * The VF can't natively handle certain types of attributes, such as GL_FIXED
246 * or most 10_10_10_2 types. These flags enable various VS workarounds to
247 * "fix" attributes at the beginning of shaders.
248 */
249 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
250 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
251 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
252 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
253 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
254
255 /**
256 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
257 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
258 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
259 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
260 */
261 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
262 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
263
264 /** The program key for Vertex Shaders. */
265 struct brw_vs_prog_key {
266 struct brw_base_prog_key base;
267
268 /**
269 * Per-attribute workaround flags
270 *
271 * For each attribute, a combination of BRW_ATTRIB_WA_*.
272 *
273 * For OpenGL, where we expose a maximum of 16 user input atttributes
274 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
275 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
276 * expose up to 28 user input vertex attributes that are mapped to slots
277 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
278 * enough to hold this many slots.
279 */
280 uint8_t gl_attrib_wa_flags[MAX2(MAX_GL_VERT_ATTRIB, MAX_VK_VERT_ATTRIB)];
281
282 bool copy_edgeflag:1;
283
284 bool clamp_vertex_color:1;
285
286 /**
287 * How many user clipping planes are being uploaded to the vertex shader as
288 * push constants.
289 *
290 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
291 * clip distances.
292 */
293 unsigned nr_userclip_plane_consts:4;
294
295 /**
296 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
297 * are going to be replaced with point coordinates (as a consequence of a
298 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
299 * our SF thread requires exact matching between VS outputs and FS inputs,
300 * these texture coordinates will need to be unconditionally included in
301 * the VUE, even if they aren't written by the vertex shader.
302 */
303 uint8_t point_coord_replace;
304 };
305
306 /** The program key for Tessellation Control Shaders. */
307 struct brw_tcs_prog_key
308 {
309 struct brw_base_prog_key base;
310
311 GLenum tes_primitive_mode;
312
313 unsigned input_vertices;
314
315 /** A bitfield of per-patch outputs written. */
316 uint32_t patch_outputs_written;
317
318 /** A bitfield of per-vertex outputs written. */
319 uint64_t outputs_written;
320
321 bool quads_workaround;
322 };
323
324 /** The program key for Tessellation Evaluation Shaders. */
325 struct brw_tes_prog_key
326 {
327 struct brw_base_prog_key base;
328
329 /** A bitfield of per-patch inputs read. */
330 uint32_t patch_inputs_read;
331
332 /** A bitfield of per-vertex inputs read. */
333 uint64_t inputs_read;
334
335 /**
336 * How many user clipping planes are being uploaded to the tessellation
337 * evaluation shader as push constants.
338 *
339 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
340 * clip distances.
341 */
342 unsigned nr_userclip_plane_consts:4;
343 };
344
345 /** The program key for Geometry Shaders. */
346 struct brw_gs_prog_key
347 {
348 struct brw_base_prog_key base;
349
350 /**
351 * How many user clipping planes are being uploaded to the geometry shader
352 * as push constants.
353 *
354 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
355 * clip distances.
356 */
357 unsigned nr_userclip_plane_consts:4;
358 };
359
360 enum brw_sf_primitive {
361 BRW_SF_PRIM_POINTS = 0,
362 BRW_SF_PRIM_LINES = 1,
363 BRW_SF_PRIM_TRIANGLES = 2,
364 BRW_SF_PRIM_UNFILLED_TRIS = 3,
365 };
366
367 struct brw_sf_prog_key {
368 uint64_t attrs;
369 bool contains_flat_varying;
370 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
371 uint8_t point_sprite_coord_replace;
372 enum brw_sf_primitive primitive:2;
373 bool do_twoside_color:1;
374 bool frontface_ccw:1;
375 bool do_point_sprite:1;
376 bool do_point_coord:1;
377 bool sprite_origin_lower_left:1;
378 bool userclip_active:1;
379 };
380
381 enum brw_clip_mode {
382 BRW_CLIP_MODE_NORMAL = 0,
383 BRW_CLIP_MODE_CLIP_ALL = 1,
384 BRW_CLIP_MODE_CLIP_NON_REJECTED = 2,
385 BRW_CLIP_MODE_REJECT_ALL = 3,
386 BRW_CLIP_MODE_ACCEPT_ALL = 4,
387 BRW_CLIP_MODE_KERNEL_CLIP = 5,
388 };
389
390 enum brw_clip_fill_mode {
391 BRW_CLIP_FILL_MODE_LINE = 0,
392 BRW_CLIP_FILL_MODE_POINT = 1,
393 BRW_CLIP_FILL_MODE_FILL = 2,
394 BRW_CLIP_FILL_MODE_CULL = 3,
395 };
396
397 /* Note that if unfilled primitives are being emitted, we have to fix
398 * up polygon offset and flatshading at this point:
399 */
400 struct brw_clip_prog_key {
401 uint64_t attrs;
402 bool contains_flat_varying;
403 bool contains_noperspective_varying;
404 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
405 unsigned primitive:4;
406 unsigned nr_userclip:4;
407 bool pv_first:1;
408 bool do_unfilled:1;
409 enum brw_clip_fill_mode fill_cw:2; /* includes cull information */
410 enum brw_clip_fill_mode fill_ccw:2; /* includes cull information */
411 bool offset_cw:1;
412 bool offset_ccw:1;
413 bool copy_bfc_cw:1;
414 bool copy_bfc_ccw:1;
415 enum brw_clip_mode clip_mode:3;
416
417 float offset_factor;
418 float offset_units;
419 float offset_clamp;
420 };
421
422 /* A big lookup table is used to figure out which and how many
423 * additional regs will inserted before the main payload in the WM
424 * program execution. These mainly relate to depth and stencil
425 * processing and the early-depth-test optimization.
426 */
427 enum brw_wm_iz_bits {
428 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT = 0x1,
429 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT = 0x2,
430 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT = 0x4,
431 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT = 0x8,
432 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT = 0x10,
433 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT = 0x20,
434 BRW_WM_IZ_BIT_MAX = 0x40
435 };
436
437 enum brw_wm_aa_enable {
438 BRW_WM_AA_NEVER,
439 BRW_WM_AA_SOMETIMES,
440 BRW_WM_AA_ALWAYS
441 };
442
443 /** The program key for Fragment/Pixel Shaders. */
444 struct brw_wm_prog_key {
445 struct brw_base_prog_key base;
446
447 /* Some collection of BRW_WM_IZ_* */
448 uint8_t iz_lookup;
449 bool stats_wm:1;
450 bool flat_shade:1;
451 unsigned nr_color_regions:5;
452 bool alpha_test_replicate_alpha:1;
453 bool alpha_to_coverage:1;
454 bool clamp_fragment_color:1;
455 bool persample_interp:1;
456 bool multisample_fbo:1;
457 bool frag_coord_adds_sample_pos:1;
458 enum brw_wm_aa_enable line_aa:2;
459 bool high_quality_derivatives:1;
460 bool force_dual_color_blend:1;
461 bool coherent_fb_fetch:1;
462 bool ignore_sample_mask_out:1;
463
464 uint8_t color_outputs_valid;
465 uint64_t input_slots_valid;
466 GLenum alpha_test_func; /* < For Gen4/5 MRT alpha test */
467 float alpha_test_ref;
468 };
469
470 struct brw_cs_prog_key {
471 struct brw_base_prog_key base;
472 };
473
474 /* brw_any_prog_key is any of the keys that map to an API stage */
475 union brw_any_prog_key {
476 struct brw_base_prog_key base;
477 struct brw_vs_prog_key vs;
478 struct brw_tcs_prog_key tcs;
479 struct brw_tes_prog_key tes;
480 struct brw_gs_prog_key gs;
481 struct brw_wm_prog_key wm;
482 struct brw_cs_prog_key cs;
483 };
484
485 /*
486 * Image metadata structure as laid out in the shader parameter
487 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
488 * able to use them. That's okay because the padding and any unused
489 * entries [most of them except when we're doing untyped surface
490 * access] will be removed by the uniform packing pass.
491 */
492 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
493 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
494 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
495 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
496 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
497 #define BRW_IMAGE_PARAM_SIZE 20
498
499 struct brw_image_param {
500 /** Offset applied to the X and Y surface coordinates. */
501 uint32_t offset[2];
502
503 /** Surface X, Y and Z dimensions. */
504 uint32_t size[3];
505
506 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
507 * pixels, vertical slice stride in pixels.
508 */
509 uint32_t stride[4];
510
511 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
512 uint32_t tiling[3];
513
514 /**
515 * Right shift to apply for bit 6 address swizzling. Two different
516 * swizzles can be specified and will be applied one after the other. The
517 * resulting address will be:
518 *
519 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
520 * (addr >> swizzling[1])))
521 *
522 * Use \c 0xff if any of the swizzles is not required.
523 */
524 uint32_t swizzling[2];
525 };
526
527 /** Max number of render targets in a shader */
528 #define BRW_MAX_DRAW_BUFFERS 8
529
530 /**
531 * Max number of binding table entries used for stream output.
532 *
533 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
534 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
535 *
536 * On Gen6, the size of transform feedback data is limited not by the number
537 * of components but by the number of binding table entries we set aside. We
538 * use one binding table entry for a float, one entry for a vector, and one
539 * entry per matrix column. Since the only way we can communicate our
540 * transform feedback capabilities to the client is via
541 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
542 * worst case, in which all the varyings are floats, so we use up one binding
543 * table entry per component. Therefore we need to set aside at least 64
544 * binding table entries for use by transform feedback.
545 *
546 * Note: since we don't currently pack varyings, it is currently impossible
547 * for the client to actually use up all of these binding table entries--if
548 * all of their varyings were floats, they would run out of varying slots and
549 * fail to link. But that's a bug, so it seems prudent to go ahead and
550 * allocate the number of binding table entries we will need once the bug is
551 * fixed.
552 */
553 #define BRW_MAX_SOL_BINDINGS 64
554
555 /**
556 * Binding table index for the first gen6 SOL binding.
557 */
558 #define BRW_GEN6_SOL_BINDING_START 0
559
560 /**
561 * Stride in bytes between shader_time entries.
562 *
563 * We separate entries by a cacheline to reduce traffic between EUs writing to
564 * different entries.
565 */
566 #define BRW_SHADER_TIME_STRIDE 64
567
568 struct brw_ubo_range
569 {
570 uint16_t block;
571 uint8_t start;
572 uint8_t length;
573 };
574
575 /* We reserve the first 2^16 values for builtins */
576 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
577
578 enum brw_param_builtin {
579 BRW_PARAM_BUILTIN_ZERO,
580
581 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X,
582 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y,
583 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z,
584 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W,
585 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X,
586 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y,
587 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z,
588 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W,
589 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X,
590 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y,
591 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z,
592 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W,
593 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X,
594 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y,
595 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z,
596 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W,
597 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X,
598 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y,
599 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z,
600 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W,
601 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X,
602 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y,
603 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z,
604 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W,
605 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X,
606 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y,
607 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z,
608 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W,
609 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X,
610 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y,
611 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z,
612 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W,
613
614 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X,
615 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y,
616 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z,
617 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W,
618 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X,
619 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y,
620
621 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN,
622
623 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X,
624 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y,
625 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z,
626 BRW_PARAM_BUILTIN_SUBGROUP_ID,
627 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X,
628 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Y,
629 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z,
630 };
631
632 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
633 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
634
635 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
636 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
637 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
638
639 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
640 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
641
642 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
643 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
644
645 /** Represents a code relocation
646 *
647 * Relocatable constants are immediates in the code which we want to be able
648 * to replace post-compile with the actual value.
649 */
650 struct brw_shader_reloc {
651 /** The 32-bit ID of the relocatable constant */
652 uint32_t id;
653
654 /** The offset in the shader to the relocatable instruction
655 *
656 * This is the offset to the instruction rather than the immediate value
657 * itself. This allows us to do some sanity checking while we relocate.
658 */
659 uint32_t offset;
660 };
661
662 /** A value to write to a relocation */
663 struct brw_shader_reloc_value {
664 /** The 32-bit ID of the relocatable constant */
665 uint32_t id;
666
667 /** The value with which to replace the relocated immediate */
668 uint32_t value;
669 };
670
671 struct brw_stage_prog_data {
672 struct {
673 /** size of our binding table. */
674 uint32_t size_bytes;
675
676 /** @{
677 * surface indices for the various groups of surfaces
678 */
679 uint32_t pull_constants_start;
680 uint32_t texture_start;
681 uint32_t gather_texture_start;
682 uint32_t ubo_start;
683 uint32_t ssbo_start;
684 uint32_t image_start;
685 uint32_t shader_time_start;
686 uint32_t plane_start[3];
687 /** @} */
688 } binding_table;
689
690 struct brw_ubo_range ubo_ranges[4];
691
692 GLuint nr_params; /**< number of float params/constants */
693 GLuint nr_pull_params;
694
695 /* zero_push_reg is a bitfield which indicates what push registers (if any)
696 * should be zeroed by SW at the start of the shader. The corresponding
697 * push_reg_mask_param specifies the param index (in 32-bit units) where
698 * the actual runtime 64-bit mask will be pushed. The shader will zero
699 * push reg i if
700 *
701 * reg_used & zero_push_reg & ~*push_reg_mask_param & (1ull << i)
702 *
703 * If this field is set, brw_compiler::compact_params must be false.
704 */
705 uint64_t zero_push_reg;
706 unsigned push_reg_mask_param;
707
708 unsigned curb_read_length;
709 unsigned total_scratch;
710 unsigned total_shared;
711
712 unsigned program_size;
713
714 unsigned const_data_size;
715 unsigned const_data_offset;
716
717 unsigned num_relocs;
718 const struct brw_shader_reloc *relocs;
719
720 /** Does this program pull from any UBO or other constant buffers? */
721 bool has_ubo_pull;
722
723 /**
724 * Register where the thread expects to find input data from the URB
725 * (typically uniforms, followed by vertex or fragment attributes).
726 */
727 unsigned dispatch_grf_start_reg;
728
729 bool use_alt_mode; /**< Use ALT floating point mode? Otherwise, IEEE. */
730
731 /* 32-bit identifiers for all push/pull parameters. These can be anything
732 * the driver wishes them to be; the core of the back-end compiler simply
733 * re-arranges them. The one restriction is that the bottom 2^16 values
734 * are reserved for builtins defined in the brw_param_builtin enum defined
735 * above.
736 */
737 uint32_t *param;
738 uint32_t *pull_param;
739
740 /* Whether shader uses atomic operations. */
741 bool uses_atomic_load_store;
742 };
743
744 static inline uint32_t *
745 brw_stage_prog_data_add_params(struct brw_stage_prog_data *prog_data,
746 unsigned nr_new_params)
747 {
748 unsigned old_nr_params = prog_data->nr_params;
749 prog_data->nr_params += nr_new_params;
750 prog_data->param = reralloc(ralloc_parent(prog_data->param),
751 prog_data->param, uint32_t,
752 prog_data->nr_params);
753 return prog_data->param + old_nr_params;
754 }
755
756 enum brw_barycentric_mode {
757 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL = 0,
758 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID = 1,
759 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE = 2,
760 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL = 3,
761 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
762 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE = 5,
763 BRW_BARYCENTRIC_MODE_COUNT = 6
764 };
765 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
766 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
767 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
768 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
769
770 enum brw_pixel_shader_computed_depth_mode {
771 BRW_PSCDEPTH_OFF = 0, /* PS does not compute depth */
772 BRW_PSCDEPTH_ON = 1, /* PS computes depth; no guarantee about value */
773 BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
774 BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
775 };
776
777 /* Data about a particular attempt to compile a program. Note that
778 * there can be many of these, each in a different GL state
779 * corresponding to a different brw_wm_prog_key struct, with different
780 * compiled programs.
781 */
782 struct brw_wm_prog_data {
783 struct brw_stage_prog_data base;
784
785 GLuint num_varying_inputs;
786
787 uint8_t reg_blocks_8;
788 uint8_t reg_blocks_16;
789 uint8_t reg_blocks_32;
790
791 uint8_t dispatch_grf_start_reg_16;
792 uint8_t dispatch_grf_start_reg_32;
793 uint32_t prog_offset_16;
794 uint32_t prog_offset_32;
795
796 struct {
797 /** @{
798 * surface indices the WM-specific surfaces
799 */
800 uint32_t render_target_read_start;
801 /** @} */
802 } binding_table;
803
804 uint8_t computed_depth_mode;
805 bool computed_stencil;
806
807 bool early_fragment_tests;
808 bool post_depth_coverage;
809 bool inner_coverage;
810 bool dispatch_8;
811 bool dispatch_16;
812 bool dispatch_32;
813 bool dual_src_blend;
814 bool persample_dispatch;
815 bool uses_pos_offset;
816 bool uses_omask;
817 bool uses_kill;
818 bool uses_src_depth;
819 bool uses_src_w;
820 bool uses_sample_mask;
821 bool has_render_target_reads;
822 bool has_side_effects;
823 bool pulls_bary;
824
825 bool contains_flat_varying;
826 bool contains_noperspective_varying;
827
828 /**
829 * Mask of which interpolation modes are required by the fragment shader.
830 * Used in hardware setup on gen6+.
831 */
832 uint32_t barycentric_interp_modes;
833
834 /**
835 * Mask of which FS inputs are marked flat by the shader source. This is
836 * needed for setting up 3DSTATE_SF/SBE.
837 */
838 uint32_t flat_inputs;
839
840 /**
841 * The FS inputs
842 */
843 uint64_t inputs;
844
845 /* Mapping of VUE slots to interpolation modes.
846 * Used by the Gen4-5 clip/sf/wm stages.
847 */
848 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
849
850 /**
851 * Map from gl_varying_slot to the position within the FS setup data
852 * payload where the varying's attribute vertex deltas should be delivered.
853 * For varying slots that are not used by the FS, the value is -1.
854 */
855 int urb_setup[VARYING_SLOT_MAX];
856
857 /**
858 * Cache structure into the urb_setup array above that contains the
859 * attribute numbers of active varyings out of urb_setup.
860 * The actual count is stored in urb_setup_attribs_count.
861 */
862 uint8_t urb_setup_attribs[VARYING_SLOT_MAX];
863 uint8_t urb_setup_attribs_count;
864 };
865
866 /** Returns the SIMD width corresponding to a given KSP index
867 *
868 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
869 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
870 * kernel start pointer (KSP) indices that is based on what dispatch widths
871 * are enabled. This function provides, effectively, the reverse mapping.
872 *
873 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
874 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
875 */
876 static inline unsigned
877 brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled,
878 bool simd16_enabled, bool simd32_enabled)
879 {
880 /* This function strictly ignores contiguous dispatch */
881 switch (ksp_idx) {
882 case 0:
883 return simd8_enabled ? 8 :
884 (simd16_enabled && !simd32_enabled) ? 16 :
885 (simd32_enabled && !simd16_enabled) ? 32 : 0;
886 case 1:
887 return (simd32_enabled && (simd16_enabled || simd8_enabled)) ? 32 : 0;
888 case 2:
889 return (simd16_enabled && (simd32_enabled || simd8_enabled)) ? 16 : 0;
890 default:
891 unreachable("Invalid KSP index");
892 }
893 }
894
895 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
896 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
897 (wm_state)._16PixelDispatchEnable, \
898 (wm_state)._32PixelDispatchEnable)
899
900 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
901 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
902
903 static inline uint32_t
904 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data,
905 unsigned simd_width)
906 {
907 switch (simd_width) {
908 case 8: return 0;
909 case 16: return prog_data->prog_offset_16;
910 case 32: return prog_data->prog_offset_32;
911 default: return 0;
912 }
913 }
914
915 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
916 _brw_wm_prog_data_prog_offset(prog_data, \
917 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
918
919 static inline uint8_t
920 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_data,
921 unsigned simd_width)
922 {
923 switch (simd_width) {
924 case 8: return prog_data->base.dispatch_grf_start_reg;
925 case 16: return prog_data->dispatch_grf_start_reg_16;
926 case 32: return prog_data->dispatch_grf_start_reg_32;
927 default: return 0;
928 }
929 }
930
931 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
932 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
933 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
934
935 static inline uint8_t
936 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data,
937 unsigned simd_width)
938 {
939 switch (simd_width) {
940 case 8: return prog_data->reg_blocks_8;
941 case 16: return prog_data->reg_blocks_16;
942 case 32: return prog_data->reg_blocks_32;
943 default: return 0;
944 }
945 }
946
947 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
948 _brw_wm_prog_data_reg_blocks(prog_data, \
949 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
950
951 struct brw_push_const_block {
952 unsigned dwords; /* Dword count, not reg aligned */
953 unsigned regs;
954 unsigned size; /* Bytes, register aligned */
955 };
956
957 struct brw_cs_prog_data {
958 struct brw_stage_prog_data base;
959
960 unsigned local_size[3];
961 unsigned slm_size;
962
963 /* Program offsets for the 8/16/32 SIMD variants. Multiple variants are
964 * kept when using variable group size, and the right one can only be
965 * decided at dispatch time.
966 */
967 unsigned prog_offset[3];
968
969 /* Bitmask indicating which program offsets are valid. */
970 unsigned prog_mask;
971
972 /* Bitmask indicating which programs have spilled. */
973 unsigned prog_spilled;
974
975 bool uses_barrier;
976 bool uses_num_work_groups;
977
978 struct {
979 struct brw_push_const_block cross_thread;
980 struct brw_push_const_block per_thread;
981 } push;
982
983 struct {
984 /** @{
985 * surface indices the CS-specific surfaces
986 */
987 uint32_t work_groups_start;
988 /** @} */
989 } binding_table;
990 };
991
992 static inline uint32_t
993 brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data *prog_data,
994 unsigned dispatch_width)
995 {
996 assert(dispatch_width == 8 ||
997 dispatch_width == 16 ||
998 dispatch_width == 32);
999 const unsigned index = dispatch_width / 16;
1000 assert(prog_data->prog_mask & (1 << index));
1001 return prog_data->prog_offset[index];
1002 }
1003
1004 /**
1005 * Enum representing the i965-specific vertex results that don't correspond
1006 * exactly to any element of gl_varying_slot. The values of this enum are
1007 * assigned such that they don't conflict with gl_varying_slot.
1008 */
1009 typedef enum
1010 {
1011 BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
1012 BRW_VARYING_SLOT_PAD,
1013 /**
1014 * Technically this is not a varying but just a placeholder that
1015 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
1016 * builtin variable to be compiled correctly. see compile_sf_prog() for
1017 * more info.
1018 */
1019 BRW_VARYING_SLOT_PNTC,
1020 BRW_VARYING_SLOT_COUNT
1021 } brw_varying_slot;
1022
1023 /**
1024 * We always program SF to start reading at an offset of 1 (2 varying slots)
1025 * from the start of the vertex URB entry. This causes it to skip:
1026 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1027 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
1028 */
1029 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
1030
1031 /**
1032 * Bitmask indicating which fragment shader inputs represent varyings (and
1033 * hence have to be delivered to the fragment shader by the SF/SBE stage).
1034 */
1035 #define BRW_FS_VARYING_INPUT_MASK \
1036 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
1037 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
1038
1039 /**
1040 * Data structure recording the relationship between the gl_varying_slot enum
1041 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
1042 * single octaword within the VUE (128 bits).
1043 *
1044 * Note that each BRW register contains 256 bits (2 octawords), so when
1045 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
1046 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
1047 * in a vertex shader), each register corresponds to a single VUE slot, since
1048 * it contains data for two separate vertices.
1049 */
1050 struct brw_vue_map {
1051 /**
1052 * Bitfield representing all varying slots that are (a) stored in this VUE
1053 * map, and (b) actually written by the shader. Does not include any of
1054 * the additional varying slots defined in brw_varying_slot.
1055 */
1056 uint64_t slots_valid;
1057
1058 /**
1059 * Is this VUE map for a separate shader pipeline?
1060 *
1061 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
1062 * without the linker having a chance to dead code eliminate unused varyings.
1063 *
1064 * This means that we have to use a fixed slot layout, based on the output's
1065 * location field, rather than assigning slots in a compact contiguous block.
1066 */
1067 bool separate;
1068
1069 /**
1070 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
1071 * not stored in a slot (because they are not written, or because
1072 * additional processing is applied before storing them in the VUE), the
1073 * value is -1.
1074 */
1075 signed char varying_to_slot[VARYING_SLOT_TESS_MAX];
1076
1077 /**
1078 * Map from VUE slot to gl_varying_slot value. For slots that do not
1079 * directly correspond to a gl_varying_slot, the value comes from
1080 * brw_varying_slot.
1081 *
1082 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
1083 */
1084 signed char slot_to_varying[VARYING_SLOT_TESS_MAX];
1085
1086 /**
1087 * Total number of VUE slots in use
1088 */
1089 int num_slots;
1090
1091 /**
1092 * Number of per-patch VUE slots. Only valid for tessellation control
1093 * shader outputs and tessellation evaluation shader inputs.
1094 */
1095 int num_per_patch_slots;
1096
1097 /**
1098 * Number of per-vertex VUE slots. Only valid for tessellation control
1099 * shader outputs and tessellation evaluation shader inputs.
1100 */
1101 int num_per_vertex_slots;
1102 };
1103
1104 void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map);
1105
1106 /**
1107 * Convert a VUE slot number into a byte offset within the VUE.
1108 */
1109 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
1110 {
1111 return 16*slot;
1112 }
1113
1114 /**
1115 * Convert a vertex output (brw_varying_slot) into a byte offset within the
1116 * VUE.
1117 */
1118 static inline
1119 GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying)
1120 {
1121 return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
1122 }
1123
1124 void brw_compute_vue_map(const struct gen_device_info *devinfo,
1125 struct brw_vue_map *vue_map,
1126 uint64_t slots_valid,
1127 bool separate_shader,
1128 uint32_t pos_slots);
1129
1130 void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
1131 uint64_t slots_valid,
1132 uint32_t is_patch);
1133
1134 /* brw_interpolation_map.c */
1135 void brw_setup_vue_interpolation(struct brw_vue_map *vue_map,
1136 struct nir_shader *nir,
1137 struct brw_wm_prog_data *prog_data);
1138
1139 enum shader_dispatch_mode {
1140 DISPATCH_MODE_4X1_SINGLE = 0,
1141 DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
1142 DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
1143 DISPATCH_MODE_SIMD8 = 3,
1144
1145 DISPATCH_MODE_TCS_SINGLE_PATCH = 0,
1146 DISPATCH_MODE_TCS_8_PATCH = 2,
1147 };
1148
1149 /**
1150 * @defgroup Tessellator parameter enumerations.
1151 *
1152 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1153 * as part of the tessellation evaluation shader.
1154 *
1155 * @{
1156 */
1157 enum brw_tess_partitioning {
1158 BRW_TESS_PARTITIONING_INTEGER = 0,
1159 BRW_TESS_PARTITIONING_ODD_FRACTIONAL = 1,
1160 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2,
1161 };
1162
1163 enum brw_tess_output_topology {
1164 BRW_TESS_OUTPUT_TOPOLOGY_POINT = 0,
1165 BRW_TESS_OUTPUT_TOPOLOGY_LINE = 1,
1166 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW = 2,
1167 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3,
1168 };
1169
1170 enum brw_tess_domain {
1171 BRW_TESS_DOMAIN_QUAD = 0,
1172 BRW_TESS_DOMAIN_TRI = 1,
1173 BRW_TESS_DOMAIN_ISOLINE = 2,
1174 };
1175 /** @} */
1176
1177 struct brw_vue_prog_data {
1178 struct brw_stage_prog_data base;
1179 struct brw_vue_map vue_map;
1180
1181 /** Should the hardware deliver input VUE handles for URB pull loads? */
1182 bool include_vue_handles;
1183
1184 GLuint urb_read_length;
1185 GLuint total_grf;
1186
1187 uint32_t clip_distance_mask;
1188 uint32_t cull_distance_mask;
1189
1190 /* Used for calculating urb partitions. In the VS, this is the size of the
1191 * URB entry used for both input and output to the thread. In the GS, this
1192 * is the size of the URB entry used for output.
1193 */
1194 GLuint urb_entry_size;
1195
1196 enum shader_dispatch_mode dispatch_mode;
1197 };
1198
1199 struct brw_vs_prog_data {
1200 struct brw_vue_prog_data base;
1201
1202 GLbitfield64 inputs_read;
1203 GLbitfield64 double_inputs_read;
1204
1205 unsigned nr_attribute_slots;
1206
1207 bool uses_vertexid;
1208 bool uses_instanceid;
1209 bool uses_is_indexed_draw;
1210 bool uses_firstvertex;
1211 bool uses_baseinstance;
1212 bool uses_drawid;
1213 };
1214
1215 struct brw_tcs_prog_data
1216 {
1217 struct brw_vue_prog_data base;
1218
1219 /** Should the non-SINGLE_PATCH payload provide primitive ID? */
1220 bool include_primitive_id;
1221
1222 /** Number vertices in output patch */
1223 int instances;
1224
1225 /** Track patch count threshold */
1226 int patch_count_threshold;
1227 };
1228
1229
1230 struct brw_tes_prog_data
1231 {
1232 struct brw_vue_prog_data base;
1233
1234 enum brw_tess_partitioning partitioning;
1235 enum brw_tess_output_topology output_topology;
1236 enum brw_tess_domain domain;
1237 };
1238
1239 struct brw_gs_prog_data
1240 {
1241 struct brw_vue_prog_data base;
1242
1243 unsigned vertices_in;
1244
1245 /**
1246 * Size of an output vertex, measured in HWORDS (32 bytes).
1247 */
1248 unsigned output_vertex_size_hwords;
1249
1250 unsigned output_topology;
1251
1252 /**
1253 * Size of the control data (cut bits or StreamID bits), in hwords (32
1254 * bytes). 0 if there is no control data.
1255 */
1256 unsigned control_data_header_size_hwords;
1257
1258 /**
1259 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1260 * if the control data is StreamID bits, or
1261 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1262 * Ignored if control_data_header_size is 0.
1263 */
1264 unsigned control_data_format;
1265
1266 bool include_primitive_id;
1267
1268 /**
1269 * The number of vertices emitted, if constant - otherwise -1.
1270 */
1271 int static_vertex_count;
1272
1273 int invocations;
1274
1275 /**
1276 * Gen6: Provoking vertex convention for odd-numbered triangles
1277 * in tristrips.
1278 */
1279 GLuint pv_first:1;
1280
1281 /**
1282 * Gen6: Number of varyings that are output to transform feedback.
1283 */
1284 GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
1285
1286 /**
1287 * Gen6: Map from the index of a transform feedback binding table entry to the
1288 * gl_varying_slot that should be streamed out through that binding table
1289 * entry.
1290 */
1291 unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */];
1292
1293 /**
1294 * Gen6: Map from the index of a transform feedback binding table entry to the
1295 * swizzles that should be used when streaming out data through that
1296 * binding table entry.
1297 */
1298 unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
1299 };
1300
1301 struct brw_sf_prog_data {
1302 uint32_t urb_read_length;
1303 uint32_t total_grf;
1304
1305 /* Each vertex may have upto 12 attributes, 4 components each,
1306 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1307 * rows.
1308 *
1309 * Actually we use 4 for each, so call it 12 rows.
1310 */
1311 unsigned urb_entry_size;
1312 };
1313
1314 struct brw_clip_prog_data {
1315 uint32_t curb_read_length; /* user planes? */
1316 uint32_t clip_mode;
1317 uint32_t urb_read_length;
1318 uint32_t total_grf;
1319 };
1320
1321 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1322 union brw_any_prog_data {
1323 struct brw_stage_prog_data base;
1324 struct brw_vue_prog_data vue;
1325 struct brw_vs_prog_data vs;
1326 struct brw_tcs_prog_data tcs;
1327 struct brw_tes_prog_data tes;
1328 struct brw_gs_prog_data gs;
1329 struct brw_wm_prog_data wm;
1330 struct brw_cs_prog_data cs;
1331 };
1332
1333 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1334 static inline struct brw_##stage##_prog_data * \
1335 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1336 { \
1337 return (struct brw_##stage##_prog_data *) prog_data; \
1338 } \
1339 static inline const struct brw_##stage##_prog_data * \
1340 brw_##stage##_prog_data_const(const struct brw_stage_prog_data *prog_data) \
1341 { \
1342 return (const struct brw_##stage##_prog_data *) prog_data; \
1343 }
1344 DEFINE_PROG_DATA_DOWNCAST(vue)
1345 DEFINE_PROG_DATA_DOWNCAST(vs)
1346 DEFINE_PROG_DATA_DOWNCAST(tcs)
1347 DEFINE_PROG_DATA_DOWNCAST(tes)
1348 DEFINE_PROG_DATA_DOWNCAST(gs)
1349 DEFINE_PROG_DATA_DOWNCAST(wm)
1350 DEFINE_PROG_DATA_DOWNCAST(cs)
1351 DEFINE_PROG_DATA_DOWNCAST(ff_gs)
1352 DEFINE_PROG_DATA_DOWNCAST(clip)
1353 DEFINE_PROG_DATA_DOWNCAST(sf)
1354 #undef DEFINE_PROG_DATA_DOWNCAST
1355
1356 struct brw_compile_stats {
1357 uint32_t dispatch_width; /**< 0 for vec4 */
1358 uint32_t instructions;
1359 uint32_t sends;
1360 uint32_t loops;
1361 uint32_t cycles;
1362 uint32_t spills;
1363 uint32_t fills;
1364 };
1365
1366 /** @} */
1367
1368 struct brw_compiler *
1369 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo);
1370
1371 /**
1372 * Returns a compiler configuration for use with disk shader cache
1373 *
1374 * This value only needs to change for settings that can cause different
1375 * program generation between two runs on the same hardware.
1376 *
1377 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1378 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1379 */
1380 uint64_t
1381 brw_get_compiler_config_value(const struct brw_compiler *compiler);
1382
1383 unsigned
1384 brw_prog_data_size(gl_shader_stage stage);
1385
1386 unsigned
1387 brw_prog_key_size(gl_shader_stage stage);
1388
1389 void
1390 brw_prog_key_set_id(union brw_any_prog_key *key, gl_shader_stage, unsigned id);
1391
1392 /**
1393 * Compile a vertex shader.
1394 *
1395 * Returns the final assembly and the program's size.
1396 */
1397 const unsigned *
1398 brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
1399 void *mem_ctx,
1400 const struct brw_vs_prog_key *key,
1401 struct brw_vs_prog_data *prog_data,
1402 struct nir_shader *shader,
1403 int shader_time_index,
1404 struct brw_compile_stats *stats,
1405 char **error_str);
1406
1407 /**
1408 * Compile a tessellation control shader.
1409 *
1410 * Returns the final assembly and the program's size.
1411 */
1412 const unsigned *
1413 brw_compile_tcs(const struct brw_compiler *compiler,
1414 void *log_data,
1415 void *mem_ctx,
1416 const struct brw_tcs_prog_key *key,
1417 struct brw_tcs_prog_data *prog_data,
1418 struct nir_shader *nir,
1419 int shader_time_index,
1420 struct brw_compile_stats *stats,
1421 char **error_str);
1422
1423 /**
1424 * Compile a tessellation evaluation shader.
1425 *
1426 * Returns the final assembly and the program's size.
1427 */
1428 const unsigned *
1429 brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
1430 void *mem_ctx,
1431 const struct brw_tes_prog_key *key,
1432 const struct brw_vue_map *input_vue_map,
1433 struct brw_tes_prog_data *prog_data,
1434 struct nir_shader *shader,
1435 int shader_time_index,
1436 struct brw_compile_stats *stats,
1437 char **error_str);
1438
1439 /**
1440 * Compile a vertex shader.
1441 *
1442 * Returns the final assembly and the program's size.
1443 */
1444 const unsigned *
1445 brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
1446 void *mem_ctx,
1447 const struct brw_gs_prog_key *key,
1448 struct brw_gs_prog_data *prog_data,
1449 struct nir_shader *shader,
1450 struct gl_program *prog,
1451 int shader_time_index,
1452 struct brw_compile_stats *stats,
1453 char **error_str);
1454
1455 /**
1456 * Compile a strips and fans shader.
1457 *
1458 * This is a fixed-function shader determined entirely by the shader key and
1459 * a VUE map.
1460 *
1461 * Returns the final assembly and the program's size.
1462 */
1463 const unsigned *
1464 brw_compile_sf(const struct brw_compiler *compiler,
1465 void *mem_ctx,
1466 const struct brw_sf_prog_key *key,
1467 struct brw_sf_prog_data *prog_data,
1468 struct brw_vue_map *vue_map,
1469 unsigned *final_assembly_size);
1470
1471 /**
1472 * Compile a clipper shader.
1473 *
1474 * This is a fixed-function shader determined entirely by the shader key and
1475 * a VUE map.
1476 *
1477 * Returns the final assembly and the program's size.
1478 */
1479 const unsigned *
1480 brw_compile_clip(const struct brw_compiler *compiler,
1481 void *mem_ctx,
1482 const struct brw_clip_prog_key *key,
1483 struct brw_clip_prog_data *prog_data,
1484 struct brw_vue_map *vue_map,
1485 unsigned *final_assembly_size);
1486
1487 /**
1488 * Compile a fragment shader.
1489 *
1490 * Returns the final assembly and the program's size.
1491 */
1492 const unsigned *
1493 brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
1494 void *mem_ctx,
1495 const struct brw_wm_prog_key *key,
1496 struct brw_wm_prog_data *prog_data,
1497 struct nir_shader *shader,
1498 int shader_time_index8,
1499 int shader_time_index16,
1500 int shader_time_index32,
1501 bool allow_spilling,
1502 bool use_rep_send, struct brw_vue_map *vue_map,
1503 struct brw_compile_stats *stats, /**< Array of three stats */
1504 char **error_str);
1505
1506 /**
1507 * Compile a compute shader.
1508 *
1509 * Returns the final assembly and the program's size.
1510 */
1511 const unsigned *
1512 brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
1513 void *mem_ctx,
1514 const struct brw_cs_prog_key *key,
1515 struct brw_cs_prog_data *prog_data,
1516 const struct nir_shader *shader,
1517 int shader_time_index,
1518 struct brw_compile_stats *stats,
1519 char **error_str);
1520
1521 void brw_debug_key_recompile(const struct brw_compiler *c, void *log,
1522 gl_shader_stage stage,
1523 const struct brw_base_prog_key *old_key,
1524 const struct brw_base_prog_key *key);
1525
1526 static inline uint32_t
1527 encode_slm_size(unsigned gen, uint32_t bytes)
1528 {
1529 uint32_t slm_size = 0;
1530
1531 /* Shared Local Memory is specified as powers of two, and encoded in
1532 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1533 *
1534 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1535 * -------------------------------------------------------------------
1536 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1537 * -------------------------------------------------------------------
1538 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1539 */
1540 assert(bytes <= 64 * 1024);
1541
1542 if (bytes > 0) {
1543 /* Shared Local Memory Size is specified as powers of two. */
1544 slm_size = util_next_power_of_two(bytes);
1545
1546 if (gen >= 9) {
1547 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1548 slm_size = ffs(MAX2(slm_size, 1024)) - 10;
1549 } else {
1550 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1551 slm_size = MAX2(slm_size, 4096) / 4096;
1552 }
1553 }
1554
1555 return slm_size;
1556 }
1557
1558 unsigned
1559 brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data,
1560 unsigned threads);
1561
1562 unsigned
1563 brw_cs_simd_size_for_group_size(const struct gen_device_info *devinfo,
1564 const struct brw_cs_prog_data *cs_prog_data,
1565 unsigned group_size);
1566
1567 void
1568 brw_write_shader_relocs(const struct gen_device_info *devinfo,
1569 void *program,
1570 const struct brw_stage_prog_data *prog_data,
1571 struct brw_shader_reloc_value *values,
1572 unsigned num_values);
1573
1574 /**
1575 * Calculate the RightExecutionMask field used in GPGPU_WALKER.
1576 */
1577 static inline unsigned
1578 brw_cs_right_mask(unsigned group_size, unsigned simd_size)
1579 {
1580 const uint32_t remainder = group_size & (simd_size - 1);
1581 if (remainder > 0)
1582 return ~0u >> (32 - remainder);
1583 else
1584 return ~0u >> (32 - simd_size);
1585 }
1586
1587 /**
1588 * Return true if the given shader stage is dispatched contiguously by the
1589 * relevant fixed function starting from channel 0 of the SIMD thread, which
1590 * implies that the dispatch mask of a thread can be assumed to have the form
1591 * '2^n - 1' for some n.
1592 */
1593 static inline bool
1594 brw_stage_has_packed_dispatch(ASSERTED const struct gen_device_info *devinfo,
1595 gl_shader_stage stage,
1596 const struct brw_stage_prog_data *prog_data)
1597 {
1598 /* The code below makes assumptions about the hardware's thread dispatch
1599 * behavior that could be proven wrong in future generations -- Make sure
1600 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1601 * the NIR front-end before changing this assertion.
1602 */
1603 assert(devinfo->gen <= 12);
1604
1605 switch (stage) {
1606 case MESA_SHADER_FRAGMENT: {
1607 /* The PSD discards subspans coming in with no lit samples, which in the
1608 * per-pixel shading case implies that each subspan will either be fully
1609 * lit (due to the VMask being used to allow derivative computations),
1610 * or not dispatched at all. In per-sample dispatch mode individual
1611 * samples from the same subspan have a fixed relative location within
1612 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1613 * general and we should return false.
1614 */
1615 const struct brw_wm_prog_data *wm_prog_data =
1616 (const struct brw_wm_prog_data *)prog_data;
1617 return !wm_prog_data->persample_dispatch;
1618 }
1619 case MESA_SHADER_COMPUTE:
1620 /* Compute shaders will be spawned with either a fully enabled dispatch
1621 * mask or with whatever bottom/right execution mask was given to the
1622 * GPGPU walker command to be used along the workgroup edges -- In both
1623 * cases the dispatch mask is required to be tightly packed for our
1624 * invocation index calculations to work.
1625 */
1626 return true;
1627 default:
1628 /* Most remaining fixed functions are limited to use a packed dispatch
1629 * mask due to the hardware representation of the dispatch mask as a
1630 * single counter representing the number of enabled channels.
1631 */
1632 return true;
1633 }
1634 }
1635
1636 /**
1637 * Computes the first varying slot in the URB produced by the previous stage
1638 * that is used in the next stage. We do this by testing the varying slots in
1639 * the previous stage's vue map against the inputs read in the next stage.
1640 *
1641 * Note that:
1642 *
1643 * - Each URB offset contains two varying slots and we can only skip a
1644 * full offset if both slots are unused, so the value we return here is always
1645 * rounded down to the closest multiple of two.
1646 *
1647 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1648 * part of the vue header, so if these are read we can't skip anything.
1649 */
1650 static inline int
1651 brw_compute_first_urb_slot_required(uint64_t inputs_read,
1652 const struct brw_vue_map *prev_stage_vue_map)
1653 {
1654 if ((inputs_read & (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT)) == 0) {
1655 for (int i = 0; i < prev_stage_vue_map->num_slots; i++) {
1656 int varying = prev_stage_vue_map->slot_to_varying[i];
1657 if (varying > 0 && (inputs_read & BITFIELD64_BIT(varying)) != 0)
1658 return ROUND_DOWN_TO(i, 2);
1659 }
1660 }
1661
1662 return 0;
1663 }
1664
1665 #ifdef __cplusplus
1666 } /* extern "C" */
1667 #endif
1668
1669 #endif /* BRW_COMPILER_H */