intel/eu: Include brw_compiler.h in brw_eu.h
[mesa.git] / src / intel / compiler / brw_compiler.h
1 /*
2 * Copyright © 2010 - 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
26
27 #include <stdio.h>
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 struct ra_regs;
38 struct nir_shader;
39 struct brw_program;
40
41 struct brw_compiler {
42 const struct gen_device_info *devinfo;
43
44 struct {
45 struct ra_regs *regs;
46
47 /**
48 * Array of the ra classes for the unaligned contiguous register
49 * block sizes used.
50 */
51 int *classes;
52
53 /**
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
56 */
57 uint8_t *ra_reg_to_grf;
58 } vec4_reg_set;
59
60 struct {
61 struct ra_regs *regs;
62
63 /**
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
66 */
67 int classes[16];
68
69 /**
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
76 */
77 int class_to_ra_reg_range[17];
78
79 /**
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
82 */
83 uint8_t *ra_reg_to_grf;
84
85 /**
86 * ra class for the aligned barycentrics we use for PLN, which doesn't
87 * appear in *classes.
88 */
89 int aligned_bary_class;
90 } fs_reg_sets[3];
91
92 void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
94
95 bool scalar_stage[MESA_ALL_SHADER_STAGES];
96 bool use_tcs_8_patch;
97 struct gl_shader_compiler_options glsl_compiler_options[MESA_ALL_SHADER_STAGES];
98
99 /**
100 * Apply workarounds for SIN and COS output range problems.
101 * This can negatively impact performance.
102 */
103 bool precise_trig;
104
105 /**
106 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
107 * Base Address? (If not, it's a normal GPU address.)
108 */
109 bool constant_buffer_0_is_relative;
110
111 /**
112 * Whether or not the driver supports pull constants. If not, the compiler
113 * will attempt to push everything.
114 */
115 bool supports_pull_constants;
116
117 /**
118 * Whether or not the driver supports NIR shader constants. This controls
119 * whether nir_opt_large_constants will be run.
120 */
121 bool supports_shader_constants;
122
123 /**
124 * Whether or not the driver wants uniform params to be compacted by the
125 * back-end compiler.
126 */
127 bool compact_params;
128
129 /**
130 * Whether or not the driver wants variable group size to be lowered by the
131 * back-end compiler.
132 */
133 bool lower_variable_group_size;
134 };
135
136 /**
137 * We use a constant subgroup size of 32. It really only needs to be a
138 * maximum and, since we do SIMD32 for compute shaders in some cases, it
139 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
140 * subgroup size of 32 but will act as if 16 or 24 of those channels are
141 * disabled.
142 */
143 #define BRW_SUBGROUP_SIZE 32
144
145 /**
146 * Program key structures.
147 *
148 * When drawing, we look for the currently bound shaders in the program
149 * cache. This is essentially a hash table lookup, and these are the keys.
150 *
151 * Sometimes OpenGL features specified as state need to be simulated via
152 * shader code, due to a mismatch between the API and the hardware. This
153 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
154 * in the program key so it's considered when searching for a program. If
155 * we haven't seen a particular combination before, we have to recompile a
156 * new specialized version.
157 *
158 * Shader compilation should not look up state in gl_context directly, but
159 * instead use the copy in the program key. This guarantees recompiles will
160 * happen correctly.
161 *
162 * @{
163 */
164
165 enum PACKED gen6_gather_sampler_wa {
166 WA_SIGN = 1, /* whether we need to sign extend */
167 WA_8BIT = 2, /* if we have an 8bit format needing wa */
168 WA_16BIT = 4, /* if we have a 16bit format needing wa */
169 };
170
171 /**
172 * Sampler information needed by VS, WM, and GS program cache keys.
173 */
174 struct brw_sampler_prog_key_data {
175 /**
176 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
177 */
178 uint16_t swizzles[MAX_SAMPLERS];
179
180 uint32_t gl_clamp_mask[3];
181
182 /**
183 * For RG32F, gather4's channel select is broken.
184 */
185 uint32_t gather_channel_quirk_mask;
186
187 /**
188 * Whether this sampler uses the compressed multisample surface layout.
189 */
190 uint32_t compressed_multisample_layout_mask;
191
192 /**
193 * Whether this sampler is using 16x multisampling. If so fetching from
194 * this sampler will be handled with a different instruction, ld2dms_w
195 * instead of ld2dms.
196 */
197 uint32_t msaa_16;
198
199 /**
200 * For Sandybridge, which shader w/a we need for gather quirks.
201 */
202 enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS];
203
204 /**
205 * Texture units that have a YUV image bound.
206 */
207 uint32_t y_u_v_image_mask;
208 uint32_t y_uv_image_mask;
209 uint32_t yx_xuxv_image_mask;
210 uint32_t xy_uxvx_image_mask;
211 uint32_t ayuv_image_mask;
212 uint32_t xyuv_image_mask;
213 uint32_t bt709_mask;
214 uint32_t bt2020_mask;
215
216 /* Scale factor for each texture. */
217 float scale_factors[32];
218 };
219
220 /** An enum representing what kind of input gl_SubgroupSize is. */
221 enum PACKED brw_subgroup_size_type
222 {
223 BRW_SUBGROUP_SIZE_API_CONSTANT, /**< Default Vulkan behavior */
224 BRW_SUBGROUP_SIZE_UNIFORM, /**< OpenGL behavior */
225 BRW_SUBGROUP_SIZE_VARYING, /**< VK_EXT_subgroup_size_control */
226
227 /* These enums are specifically chosen so that the value of the enum is
228 * also the subgroup size. If any new values are added, they must respect
229 * this invariant.
230 */
231 BRW_SUBGROUP_SIZE_REQUIRE_8 = 8, /**< VK_EXT_subgroup_size_control */
232 BRW_SUBGROUP_SIZE_REQUIRE_16 = 16, /**< VK_EXT_subgroup_size_control */
233 BRW_SUBGROUP_SIZE_REQUIRE_32 = 32, /**< VK_EXT_subgroup_size_control */
234 };
235
236 struct brw_base_prog_key {
237 unsigned program_string_id;
238
239 enum brw_subgroup_size_type subgroup_size_type;
240
241 struct brw_sampler_prog_key_data tex;
242 };
243
244 /**
245 * The VF can't natively handle certain types of attributes, such as GL_FIXED
246 * or most 10_10_10_2 types. These flags enable various VS workarounds to
247 * "fix" attributes at the beginning of shaders.
248 */
249 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
250 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
251 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
252 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
253 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
254
255 /**
256 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
257 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
258 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
259 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
260 */
261 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
262 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
263
264 /** The program key for Vertex Shaders. */
265 struct brw_vs_prog_key {
266 struct brw_base_prog_key base;
267
268 /**
269 * Per-attribute workaround flags
270 *
271 * For each attribute, a combination of BRW_ATTRIB_WA_*.
272 *
273 * For OpenGL, where we expose a maximum of 16 user input atttributes
274 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
275 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
276 * expose up to 28 user input vertex attributes that are mapped to slots
277 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
278 * enough to hold this many slots.
279 */
280 uint8_t gl_attrib_wa_flags[MAX2(MAX_GL_VERT_ATTRIB, MAX_VK_VERT_ATTRIB)];
281
282 bool copy_edgeflag:1;
283
284 bool clamp_vertex_color:1;
285
286 /**
287 * How many user clipping planes are being uploaded to the vertex shader as
288 * push constants.
289 *
290 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
291 * clip distances.
292 */
293 unsigned nr_userclip_plane_consts:4;
294
295 /**
296 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
297 * are going to be replaced with point coordinates (as a consequence of a
298 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
299 * our SF thread requires exact matching between VS outputs and FS inputs,
300 * these texture coordinates will need to be unconditionally included in
301 * the VUE, even if they aren't written by the vertex shader.
302 */
303 uint8_t point_coord_replace;
304 };
305
306 /** The program key for Tessellation Control Shaders. */
307 struct brw_tcs_prog_key
308 {
309 struct brw_base_prog_key base;
310
311 GLenum tes_primitive_mode;
312
313 unsigned input_vertices;
314
315 /** A bitfield of per-patch outputs written. */
316 uint32_t patch_outputs_written;
317
318 /** A bitfield of per-vertex outputs written. */
319 uint64_t outputs_written;
320
321 bool quads_workaround;
322 };
323
324 /** The program key for Tessellation Evaluation Shaders. */
325 struct brw_tes_prog_key
326 {
327 struct brw_base_prog_key base;
328
329 /** A bitfield of per-patch inputs read. */
330 uint32_t patch_inputs_read;
331
332 /** A bitfield of per-vertex inputs read. */
333 uint64_t inputs_read;
334
335 /**
336 * How many user clipping planes are being uploaded to the tessellation
337 * evaluation shader as push constants.
338 *
339 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
340 * clip distances.
341 */
342 unsigned nr_userclip_plane_consts:4;
343 };
344
345 /** The program key for Geometry Shaders. */
346 struct brw_gs_prog_key
347 {
348 struct brw_base_prog_key base;
349
350 /**
351 * How many user clipping planes are being uploaded to the geometry shader
352 * as push constants.
353 *
354 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
355 * clip distances.
356 */
357 unsigned nr_userclip_plane_consts:4;
358 };
359
360 enum brw_sf_primitive {
361 BRW_SF_PRIM_POINTS = 0,
362 BRW_SF_PRIM_LINES = 1,
363 BRW_SF_PRIM_TRIANGLES = 2,
364 BRW_SF_PRIM_UNFILLED_TRIS = 3,
365 };
366
367 struct brw_sf_prog_key {
368 uint64_t attrs;
369 bool contains_flat_varying;
370 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
371 uint8_t point_sprite_coord_replace;
372 enum brw_sf_primitive primitive:2;
373 bool do_twoside_color:1;
374 bool frontface_ccw:1;
375 bool do_point_sprite:1;
376 bool do_point_coord:1;
377 bool sprite_origin_lower_left:1;
378 bool userclip_active:1;
379 };
380
381 enum brw_clip_mode {
382 BRW_CLIP_MODE_NORMAL = 0,
383 BRW_CLIP_MODE_CLIP_ALL = 1,
384 BRW_CLIP_MODE_CLIP_NON_REJECTED = 2,
385 BRW_CLIP_MODE_REJECT_ALL = 3,
386 BRW_CLIP_MODE_ACCEPT_ALL = 4,
387 BRW_CLIP_MODE_KERNEL_CLIP = 5,
388 };
389
390 enum brw_clip_fill_mode {
391 BRW_CLIP_FILL_MODE_LINE = 0,
392 BRW_CLIP_FILL_MODE_POINT = 1,
393 BRW_CLIP_FILL_MODE_FILL = 2,
394 BRW_CLIP_FILL_MODE_CULL = 3,
395 };
396
397 /* Note that if unfilled primitives are being emitted, we have to fix
398 * up polygon offset and flatshading at this point:
399 */
400 struct brw_clip_prog_key {
401 uint64_t attrs;
402 bool contains_flat_varying;
403 bool contains_noperspective_varying;
404 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
405 unsigned primitive:4;
406 unsigned nr_userclip:4;
407 bool pv_first:1;
408 bool do_unfilled:1;
409 enum brw_clip_fill_mode fill_cw:2; /* includes cull information */
410 enum brw_clip_fill_mode fill_ccw:2; /* includes cull information */
411 bool offset_cw:1;
412 bool offset_ccw:1;
413 bool copy_bfc_cw:1;
414 bool copy_bfc_ccw:1;
415 enum brw_clip_mode clip_mode:3;
416
417 float offset_factor;
418 float offset_units;
419 float offset_clamp;
420 };
421
422 /* A big lookup table is used to figure out which and how many
423 * additional regs will inserted before the main payload in the WM
424 * program execution. These mainly relate to depth and stencil
425 * processing and the early-depth-test optimization.
426 */
427 enum brw_wm_iz_bits {
428 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT = 0x1,
429 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT = 0x2,
430 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT = 0x4,
431 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT = 0x8,
432 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT = 0x10,
433 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT = 0x20,
434 BRW_WM_IZ_BIT_MAX = 0x40
435 };
436
437 enum brw_wm_aa_enable {
438 BRW_WM_AA_NEVER,
439 BRW_WM_AA_SOMETIMES,
440 BRW_WM_AA_ALWAYS
441 };
442
443 /** The program key for Fragment/Pixel Shaders. */
444 struct brw_wm_prog_key {
445 struct brw_base_prog_key base;
446
447 /* Some collection of BRW_WM_IZ_* */
448 uint8_t iz_lookup;
449 bool stats_wm:1;
450 bool flat_shade:1;
451 unsigned nr_color_regions:5;
452 bool alpha_test_replicate_alpha:1;
453 bool alpha_to_coverage:1;
454 bool clamp_fragment_color:1;
455 bool persample_interp:1;
456 bool multisample_fbo:1;
457 bool frag_coord_adds_sample_pos:1;
458 enum brw_wm_aa_enable line_aa:2;
459 bool high_quality_derivatives:1;
460 bool force_dual_color_blend:1;
461 bool coherent_fb_fetch:1;
462 bool ignore_sample_mask_out:1;
463
464 uint8_t color_outputs_valid;
465 uint64_t input_slots_valid;
466 GLenum alpha_test_func; /* < For Gen4/5 MRT alpha test */
467 float alpha_test_ref;
468 };
469
470 struct brw_cs_prog_key {
471 struct brw_base_prog_key base;
472 };
473
474 /* brw_any_prog_key is any of the keys that map to an API stage */
475 union brw_any_prog_key {
476 struct brw_base_prog_key base;
477 struct brw_vs_prog_key vs;
478 struct brw_tcs_prog_key tcs;
479 struct brw_tes_prog_key tes;
480 struct brw_gs_prog_key gs;
481 struct brw_wm_prog_key wm;
482 struct brw_cs_prog_key cs;
483 };
484
485 /*
486 * Image metadata structure as laid out in the shader parameter
487 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
488 * able to use them. That's okay because the padding and any unused
489 * entries [most of them except when we're doing untyped surface
490 * access] will be removed by the uniform packing pass.
491 */
492 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
493 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
494 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
495 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
496 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
497 #define BRW_IMAGE_PARAM_SIZE 20
498
499 struct brw_image_param {
500 /** Offset applied to the X and Y surface coordinates. */
501 uint32_t offset[2];
502
503 /** Surface X, Y and Z dimensions. */
504 uint32_t size[3];
505
506 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
507 * pixels, vertical slice stride in pixels.
508 */
509 uint32_t stride[4];
510
511 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
512 uint32_t tiling[3];
513
514 /**
515 * Right shift to apply for bit 6 address swizzling. Two different
516 * swizzles can be specified and will be applied one after the other. The
517 * resulting address will be:
518 *
519 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
520 * (addr >> swizzling[1])))
521 *
522 * Use \c 0xff if any of the swizzles is not required.
523 */
524 uint32_t swizzling[2];
525 };
526
527 /** Max number of render targets in a shader */
528 #define BRW_MAX_DRAW_BUFFERS 8
529
530 /**
531 * Max number of binding table entries used for stream output.
532 *
533 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
534 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
535 *
536 * On Gen6, the size of transform feedback data is limited not by the number
537 * of components but by the number of binding table entries we set aside. We
538 * use one binding table entry for a float, one entry for a vector, and one
539 * entry per matrix column. Since the only way we can communicate our
540 * transform feedback capabilities to the client is via
541 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
542 * worst case, in which all the varyings are floats, so we use up one binding
543 * table entry per component. Therefore we need to set aside at least 64
544 * binding table entries for use by transform feedback.
545 *
546 * Note: since we don't currently pack varyings, it is currently impossible
547 * for the client to actually use up all of these binding table entries--if
548 * all of their varyings were floats, they would run out of varying slots and
549 * fail to link. But that's a bug, so it seems prudent to go ahead and
550 * allocate the number of binding table entries we will need once the bug is
551 * fixed.
552 */
553 #define BRW_MAX_SOL_BINDINGS 64
554
555 /**
556 * Binding table index for the first gen6 SOL binding.
557 */
558 #define BRW_GEN6_SOL_BINDING_START 0
559
560 /**
561 * Stride in bytes between shader_time entries.
562 *
563 * We separate entries by a cacheline to reduce traffic between EUs writing to
564 * different entries.
565 */
566 #define BRW_SHADER_TIME_STRIDE 64
567
568 struct brw_ubo_range
569 {
570 uint16_t block;
571 uint8_t start;
572 uint8_t length;
573 };
574
575 /* We reserve the first 2^16 values for builtins */
576 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
577
578 enum brw_param_builtin {
579 BRW_PARAM_BUILTIN_ZERO,
580
581 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X,
582 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y,
583 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z,
584 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W,
585 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X,
586 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y,
587 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z,
588 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W,
589 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X,
590 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y,
591 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z,
592 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W,
593 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X,
594 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y,
595 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z,
596 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W,
597 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X,
598 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y,
599 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z,
600 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W,
601 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X,
602 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y,
603 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z,
604 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W,
605 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X,
606 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y,
607 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z,
608 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W,
609 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X,
610 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y,
611 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z,
612 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W,
613
614 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X,
615 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y,
616 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z,
617 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W,
618 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X,
619 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y,
620
621 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN,
622
623 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X,
624 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y,
625 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z,
626 BRW_PARAM_BUILTIN_SUBGROUP_ID,
627 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X,
628 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Y,
629 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z,
630 };
631
632 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
633 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
634
635 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
636 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
637 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
638
639 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
640 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
641
642 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
643 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
644
645 struct brw_stage_prog_data {
646 struct {
647 /** size of our binding table. */
648 uint32_t size_bytes;
649
650 /** @{
651 * surface indices for the various groups of surfaces
652 */
653 uint32_t pull_constants_start;
654 uint32_t texture_start;
655 uint32_t gather_texture_start;
656 uint32_t ubo_start;
657 uint32_t ssbo_start;
658 uint32_t image_start;
659 uint32_t shader_time_start;
660 uint32_t plane_start[3];
661 /** @} */
662 } binding_table;
663
664 struct brw_ubo_range ubo_ranges[4];
665
666 GLuint nr_params; /**< number of float params/constants */
667 GLuint nr_pull_params;
668
669 /* zero_push_reg is a bitfield which indicates what push registers (if any)
670 * should be zeroed by SW at the start of the shader. The corresponding
671 * push_reg_mask_param specifies the param index (in 32-bit units) where
672 * the actual runtime 64-bit mask will be pushed. The shader will zero
673 * push reg i if
674 *
675 * reg_used & zero_push_reg & ~*push_reg_mask_param & (1ull << i)
676 *
677 * If this field is set, brw_compiler::compact_params must be false.
678 */
679 uint64_t zero_push_reg;
680 unsigned push_reg_mask_param;
681
682 unsigned curb_read_length;
683 unsigned total_scratch;
684 unsigned total_shared;
685
686 unsigned program_size;
687
688 unsigned const_data_size;
689 unsigned const_data_offset;
690
691 /** Does this program pull from any UBO or other constant buffers? */
692 bool has_ubo_pull;
693
694 /**
695 * Register where the thread expects to find input data from the URB
696 * (typically uniforms, followed by vertex or fragment attributes).
697 */
698 unsigned dispatch_grf_start_reg;
699
700 bool use_alt_mode; /**< Use ALT floating point mode? Otherwise, IEEE. */
701
702 /* 32-bit identifiers for all push/pull parameters. These can be anything
703 * the driver wishes them to be; the core of the back-end compiler simply
704 * re-arranges them. The one restriction is that the bottom 2^16 values
705 * are reserved for builtins defined in the brw_param_builtin enum defined
706 * above.
707 */
708 uint32_t *param;
709 uint32_t *pull_param;
710
711 /* Whether shader uses atomic operations. */
712 bool uses_atomic_load_store;
713 };
714
715 static inline uint32_t *
716 brw_stage_prog_data_add_params(struct brw_stage_prog_data *prog_data,
717 unsigned nr_new_params)
718 {
719 unsigned old_nr_params = prog_data->nr_params;
720 prog_data->nr_params += nr_new_params;
721 prog_data->param = reralloc(ralloc_parent(prog_data->param),
722 prog_data->param, uint32_t,
723 prog_data->nr_params);
724 return prog_data->param + old_nr_params;
725 }
726
727 enum brw_barycentric_mode {
728 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL = 0,
729 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID = 1,
730 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE = 2,
731 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL = 3,
732 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
733 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE = 5,
734 BRW_BARYCENTRIC_MODE_COUNT = 6
735 };
736 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
737 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
738 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
739 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
740
741 enum brw_pixel_shader_computed_depth_mode {
742 BRW_PSCDEPTH_OFF = 0, /* PS does not compute depth */
743 BRW_PSCDEPTH_ON = 1, /* PS computes depth; no guarantee about value */
744 BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
745 BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
746 };
747
748 /* Data about a particular attempt to compile a program. Note that
749 * there can be many of these, each in a different GL state
750 * corresponding to a different brw_wm_prog_key struct, with different
751 * compiled programs.
752 */
753 struct brw_wm_prog_data {
754 struct brw_stage_prog_data base;
755
756 GLuint num_varying_inputs;
757
758 uint8_t reg_blocks_8;
759 uint8_t reg_blocks_16;
760 uint8_t reg_blocks_32;
761
762 uint8_t dispatch_grf_start_reg_16;
763 uint8_t dispatch_grf_start_reg_32;
764 uint32_t prog_offset_16;
765 uint32_t prog_offset_32;
766
767 struct {
768 /** @{
769 * surface indices the WM-specific surfaces
770 */
771 uint32_t render_target_read_start;
772 /** @} */
773 } binding_table;
774
775 uint8_t computed_depth_mode;
776 bool computed_stencil;
777
778 bool early_fragment_tests;
779 bool post_depth_coverage;
780 bool inner_coverage;
781 bool dispatch_8;
782 bool dispatch_16;
783 bool dispatch_32;
784 bool dual_src_blend;
785 bool persample_dispatch;
786 bool uses_pos_offset;
787 bool uses_omask;
788 bool uses_kill;
789 bool uses_src_depth;
790 bool uses_src_w;
791 bool uses_sample_mask;
792 bool has_render_target_reads;
793 bool has_side_effects;
794 bool pulls_bary;
795
796 bool contains_flat_varying;
797 bool contains_noperspective_varying;
798
799 /**
800 * Mask of which interpolation modes are required by the fragment shader.
801 * Used in hardware setup on gen6+.
802 */
803 uint32_t barycentric_interp_modes;
804
805 /**
806 * Mask of which FS inputs are marked flat by the shader source. This is
807 * needed for setting up 3DSTATE_SF/SBE.
808 */
809 uint32_t flat_inputs;
810
811 /**
812 * The FS inputs
813 */
814 uint64_t inputs;
815
816 /* Mapping of VUE slots to interpolation modes.
817 * Used by the Gen4-5 clip/sf/wm stages.
818 */
819 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
820
821 /**
822 * Map from gl_varying_slot to the position within the FS setup data
823 * payload where the varying's attribute vertex deltas should be delivered.
824 * For varying slots that are not used by the FS, the value is -1.
825 */
826 int urb_setup[VARYING_SLOT_MAX];
827
828 /**
829 * Cache structure into the urb_setup array above that contains the
830 * attribute numbers of active varyings out of urb_setup.
831 * The actual count is stored in urb_setup_attribs_count.
832 */
833 uint8_t urb_setup_attribs[VARYING_SLOT_MAX];
834 uint8_t urb_setup_attribs_count;
835 };
836
837 /** Returns the SIMD width corresponding to a given KSP index
838 *
839 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
840 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
841 * kernel start pointer (KSP) indices that is based on what dispatch widths
842 * are enabled. This function provides, effectively, the reverse mapping.
843 *
844 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
845 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
846 */
847 static inline unsigned
848 brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled,
849 bool simd16_enabled, bool simd32_enabled)
850 {
851 /* This function strictly ignores contiguous dispatch */
852 switch (ksp_idx) {
853 case 0:
854 return simd8_enabled ? 8 :
855 (simd16_enabled && !simd32_enabled) ? 16 :
856 (simd32_enabled && !simd16_enabled) ? 32 : 0;
857 case 1:
858 return (simd32_enabled && (simd16_enabled || simd8_enabled)) ? 32 : 0;
859 case 2:
860 return (simd16_enabled && (simd32_enabled || simd8_enabled)) ? 16 : 0;
861 default:
862 unreachable("Invalid KSP index");
863 }
864 }
865
866 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
867 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
868 (wm_state)._16PixelDispatchEnable, \
869 (wm_state)._32PixelDispatchEnable)
870
871 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
872 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
873
874 static inline uint32_t
875 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data,
876 unsigned simd_width)
877 {
878 switch (simd_width) {
879 case 8: return 0;
880 case 16: return prog_data->prog_offset_16;
881 case 32: return prog_data->prog_offset_32;
882 default: return 0;
883 }
884 }
885
886 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
887 _brw_wm_prog_data_prog_offset(prog_data, \
888 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
889
890 static inline uint8_t
891 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_data,
892 unsigned simd_width)
893 {
894 switch (simd_width) {
895 case 8: return prog_data->base.dispatch_grf_start_reg;
896 case 16: return prog_data->dispatch_grf_start_reg_16;
897 case 32: return prog_data->dispatch_grf_start_reg_32;
898 default: return 0;
899 }
900 }
901
902 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
903 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
904 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
905
906 static inline uint8_t
907 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data,
908 unsigned simd_width)
909 {
910 switch (simd_width) {
911 case 8: return prog_data->reg_blocks_8;
912 case 16: return prog_data->reg_blocks_16;
913 case 32: return prog_data->reg_blocks_32;
914 default: return 0;
915 }
916 }
917
918 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
919 _brw_wm_prog_data_reg_blocks(prog_data, \
920 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
921
922 struct brw_push_const_block {
923 unsigned dwords; /* Dword count, not reg aligned */
924 unsigned regs;
925 unsigned size; /* Bytes, register aligned */
926 };
927
928 struct brw_cs_prog_data {
929 struct brw_stage_prog_data base;
930
931 unsigned local_size[3];
932 unsigned slm_size;
933
934 /* Program offsets for the 8/16/32 SIMD variants. Multiple variants are
935 * kept when using variable group size, and the right one can only be
936 * decided at dispatch time.
937 */
938 unsigned prog_offset[3];
939
940 /* Bitmask indicating which program offsets are valid. */
941 unsigned prog_mask;
942
943 /* Bitmask indicating which programs have spilled. */
944 unsigned prog_spilled;
945
946 bool uses_barrier;
947 bool uses_num_work_groups;
948
949 struct {
950 struct brw_push_const_block cross_thread;
951 struct brw_push_const_block per_thread;
952 } push;
953
954 struct {
955 /** @{
956 * surface indices the CS-specific surfaces
957 */
958 uint32_t work_groups_start;
959 /** @} */
960 } binding_table;
961 };
962
963 static inline uint32_t
964 brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data *prog_data,
965 unsigned dispatch_width)
966 {
967 assert(dispatch_width == 8 ||
968 dispatch_width == 16 ||
969 dispatch_width == 32);
970 const unsigned index = dispatch_width / 16;
971 assert(prog_data->prog_mask & (1 << index));
972 return prog_data->prog_offset[index];
973 }
974
975 /**
976 * Enum representing the i965-specific vertex results that don't correspond
977 * exactly to any element of gl_varying_slot. The values of this enum are
978 * assigned such that they don't conflict with gl_varying_slot.
979 */
980 typedef enum
981 {
982 BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
983 BRW_VARYING_SLOT_PAD,
984 /**
985 * Technically this is not a varying but just a placeholder that
986 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
987 * builtin variable to be compiled correctly. see compile_sf_prog() for
988 * more info.
989 */
990 BRW_VARYING_SLOT_PNTC,
991 BRW_VARYING_SLOT_COUNT
992 } brw_varying_slot;
993
994 /**
995 * We always program SF to start reading at an offset of 1 (2 varying slots)
996 * from the start of the vertex URB entry. This causes it to skip:
997 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
998 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
999 */
1000 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
1001
1002 /**
1003 * Bitmask indicating which fragment shader inputs represent varyings (and
1004 * hence have to be delivered to the fragment shader by the SF/SBE stage).
1005 */
1006 #define BRW_FS_VARYING_INPUT_MASK \
1007 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
1008 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
1009
1010 /**
1011 * Data structure recording the relationship between the gl_varying_slot enum
1012 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
1013 * single octaword within the VUE (128 bits).
1014 *
1015 * Note that each BRW register contains 256 bits (2 octawords), so when
1016 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
1017 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
1018 * in a vertex shader), each register corresponds to a single VUE slot, since
1019 * it contains data for two separate vertices.
1020 */
1021 struct brw_vue_map {
1022 /**
1023 * Bitfield representing all varying slots that are (a) stored in this VUE
1024 * map, and (b) actually written by the shader. Does not include any of
1025 * the additional varying slots defined in brw_varying_slot.
1026 */
1027 uint64_t slots_valid;
1028
1029 /**
1030 * Is this VUE map for a separate shader pipeline?
1031 *
1032 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
1033 * without the linker having a chance to dead code eliminate unused varyings.
1034 *
1035 * This means that we have to use a fixed slot layout, based on the output's
1036 * location field, rather than assigning slots in a compact contiguous block.
1037 */
1038 bool separate;
1039
1040 /**
1041 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
1042 * not stored in a slot (because they are not written, or because
1043 * additional processing is applied before storing them in the VUE), the
1044 * value is -1.
1045 */
1046 signed char varying_to_slot[VARYING_SLOT_TESS_MAX];
1047
1048 /**
1049 * Map from VUE slot to gl_varying_slot value. For slots that do not
1050 * directly correspond to a gl_varying_slot, the value comes from
1051 * brw_varying_slot.
1052 *
1053 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
1054 */
1055 signed char slot_to_varying[VARYING_SLOT_TESS_MAX];
1056
1057 /**
1058 * Total number of VUE slots in use
1059 */
1060 int num_slots;
1061
1062 /**
1063 * Number of per-patch VUE slots. Only valid for tessellation control
1064 * shader outputs and tessellation evaluation shader inputs.
1065 */
1066 int num_per_patch_slots;
1067
1068 /**
1069 * Number of per-vertex VUE slots. Only valid for tessellation control
1070 * shader outputs and tessellation evaluation shader inputs.
1071 */
1072 int num_per_vertex_slots;
1073 };
1074
1075 void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map);
1076
1077 /**
1078 * Convert a VUE slot number into a byte offset within the VUE.
1079 */
1080 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
1081 {
1082 return 16*slot;
1083 }
1084
1085 /**
1086 * Convert a vertex output (brw_varying_slot) into a byte offset within the
1087 * VUE.
1088 */
1089 static inline
1090 GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying)
1091 {
1092 return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
1093 }
1094
1095 void brw_compute_vue_map(const struct gen_device_info *devinfo,
1096 struct brw_vue_map *vue_map,
1097 uint64_t slots_valid,
1098 bool separate_shader,
1099 uint32_t pos_slots);
1100
1101 void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
1102 uint64_t slots_valid,
1103 uint32_t is_patch);
1104
1105 /* brw_interpolation_map.c */
1106 void brw_setup_vue_interpolation(struct brw_vue_map *vue_map,
1107 struct nir_shader *nir,
1108 struct brw_wm_prog_data *prog_data);
1109
1110 enum shader_dispatch_mode {
1111 DISPATCH_MODE_4X1_SINGLE = 0,
1112 DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
1113 DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
1114 DISPATCH_MODE_SIMD8 = 3,
1115
1116 DISPATCH_MODE_TCS_SINGLE_PATCH = 0,
1117 DISPATCH_MODE_TCS_8_PATCH = 2,
1118 };
1119
1120 /**
1121 * @defgroup Tessellator parameter enumerations.
1122 *
1123 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1124 * as part of the tessellation evaluation shader.
1125 *
1126 * @{
1127 */
1128 enum brw_tess_partitioning {
1129 BRW_TESS_PARTITIONING_INTEGER = 0,
1130 BRW_TESS_PARTITIONING_ODD_FRACTIONAL = 1,
1131 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2,
1132 };
1133
1134 enum brw_tess_output_topology {
1135 BRW_TESS_OUTPUT_TOPOLOGY_POINT = 0,
1136 BRW_TESS_OUTPUT_TOPOLOGY_LINE = 1,
1137 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW = 2,
1138 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3,
1139 };
1140
1141 enum brw_tess_domain {
1142 BRW_TESS_DOMAIN_QUAD = 0,
1143 BRW_TESS_DOMAIN_TRI = 1,
1144 BRW_TESS_DOMAIN_ISOLINE = 2,
1145 };
1146 /** @} */
1147
1148 struct brw_vue_prog_data {
1149 struct brw_stage_prog_data base;
1150 struct brw_vue_map vue_map;
1151
1152 /** Should the hardware deliver input VUE handles for URB pull loads? */
1153 bool include_vue_handles;
1154
1155 GLuint urb_read_length;
1156 GLuint total_grf;
1157
1158 uint32_t clip_distance_mask;
1159 uint32_t cull_distance_mask;
1160
1161 /* Used for calculating urb partitions. In the VS, this is the size of the
1162 * URB entry used for both input and output to the thread. In the GS, this
1163 * is the size of the URB entry used for output.
1164 */
1165 GLuint urb_entry_size;
1166
1167 enum shader_dispatch_mode dispatch_mode;
1168 };
1169
1170 struct brw_vs_prog_data {
1171 struct brw_vue_prog_data base;
1172
1173 GLbitfield64 inputs_read;
1174 GLbitfield64 double_inputs_read;
1175
1176 unsigned nr_attribute_slots;
1177
1178 bool uses_vertexid;
1179 bool uses_instanceid;
1180 bool uses_is_indexed_draw;
1181 bool uses_firstvertex;
1182 bool uses_baseinstance;
1183 bool uses_drawid;
1184 };
1185
1186 struct brw_tcs_prog_data
1187 {
1188 struct brw_vue_prog_data base;
1189
1190 /** Should the non-SINGLE_PATCH payload provide primitive ID? */
1191 bool include_primitive_id;
1192
1193 /** Number vertices in output patch */
1194 int instances;
1195
1196 /** Track patch count threshold */
1197 int patch_count_threshold;
1198 };
1199
1200
1201 struct brw_tes_prog_data
1202 {
1203 struct brw_vue_prog_data base;
1204
1205 enum brw_tess_partitioning partitioning;
1206 enum brw_tess_output_topology output_topology;
1207 enum brw_tess_domain domain;
1208 };
1209
1210 struct brw_gs_prog_data
1211 {
1212 struct brw_vue_prog_data base;
1213
1214 unsigned vertices_in;
1215
1216 /**
1217 * Size of an output vertex, measured in HWORDS (32 bytes).
1218 */
1219 unsigned output_vertex_size_hwords;
1220
1221 unsigned output_topology;
1222
1223 /**
1224 * Size of the control data (cut bits or StreamID bits), in hwords (32
1225 * bytes). 0 if there is no control data.
1226 */
1227 unsigned control_data_header_size_hwords;
1228
1229 /**
1230 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1231 * if the control data is StreamID bits, or
1232 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1233 * Ignored if control_data_header_size is 0.
1234 */
1235 unsigned control_data_format;
1236
1237 bool include_primitive_id;
1238
1239 /**
1240 * The number of vertices emitted, if constant - otherwise -1.
1241 */
1242 int static_vertex_count;
1243
1244 int invocations;
1245
1246 /**
1247 * Gen6: Provoking vertex convention for odd-numbered triangles
1248 * in tristrips.
1249 */
1250 GLuint pv_first:1;
1251
1252 /**
1253 * Gen6: Number of varyings that are output to transform feedback.
1254 */
1255 GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
1256
1257 /**
1258 * Gen6: Map from the index of a transform feedback binding table entry to the
1259 * gl_varying_slot that should be streamed out through that binding table
1260 * entry.
1261 */
1262 unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */];
1263
1264 /**
1265 * Gen6: Map from the index of a transform feedback binding table entry to the
1266 * swizzles that should be used when streaming out data through that
1267 * binding table entry.
1268 */
1269 unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
1270 };
1271
1272 struct brw_sf_prog_data {
1273 uint32_t urb_read_length;
1274 uint32_t total_grf;
1275
1276 /* Each vertex may have upto 12 attributes, 4 components each,
1277 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1278 * rows.
1279 *
1280 * Actually we use 4 for each, so call it 12 rows.
1281 */
1282 unsigned urb_entry_size;
1283 };
1284
1285 struct brw_clip_prog_data {
1286 uint32_t curb_read_length; /* user planes? */
1287 uint32_t clip_mode;
1288 uint32_t urb_read_length;
1289 uint32_t total_grf;
1290 };
1291
1292 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1293 union brw_any_prog_data {
1294 struct brw_stage_prog_data base;
1295 struct brw_vue_prog_data vue;
1296 struct brw_vs_prog_data vs;
1297 struct brw_tcs_prog_data tcs;
1298 struct brw_tes_prog_data tes;
1299 struct brw_gs_prog_data gs;
1300 struct brw_wm_prog_data wm;
1301 struct brw_cs_prog_data cs;
1302 };
1303
1304 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1305 static inline struct brw_##stage##_prog_data * \
1306 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1307 { \
1308 return (struct brw_##stage##_prog_data *) prog_data; \
1309 } \
1310 static inline const struct brw_##stage##_prog_data * \
1311 brw_##stage##_prog_data_const(const struct brw_stage_prog_data *prog_data) \
1312 { \
1313 return (const struct brw_##stage##_prog_data *) prog_data; \
1314 }
1315 DEFINE_PROG_DATA_DOWNCAST(vue)
1316 DEFINE_PROG_DATA_DOWNCAST(vs)
1317 DEFINE_PROG_DATA_DOWNCAST(tcs)
1318 DEFINE_PROG_DATA_DOWNCAST(tes)
1319 DEFINE_PROG_DATA_DOWNCAST(gs)
1320 DEFINE_PROG_DATA_DOWNCAST(wm)
1321 DEFINE_PROG_DATA_DOWNCAST(cs)
1322 DEFINE_PROG_DATA_DOWNCAST(ff_gs)
1323 DEFINE_PROG_DATA_DOWNCAST(clip)
1324 DEFINE_PROG_DATA_DOWNCAST(sf)
1325 #undef DEFINE_PROG_DATA_DOWNCAST
1326
1327 struct brw_compile_stats {
1328 uint32_t dispatch_width; /**< 0 for vec4 */
1329 uint32_t instructions;
1330 uint32_t sends;
1331 uint32_t loops;
1332 uint32_t cycles;
1333 uint32_t spills;
1334 uint32_t fills;
1335 };
1336
1337 /** @} */
1338
1339 struct brw_compiler *
1340 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo);
1341
1342 /**
1343 * Returns a compiler configuration for use with disk shader cache
1344 *
1345 * This value only needs to change for settings that can cause different
1346 * program generation between two runs on the same hardware.
1347 *
1348 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1349 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1350 */
1351 uint64_t
1352 brw_get_compiler_config_value(const struct brw_compiler *compiler);
1353
1354 unsigned
1355 brw_prog_data_size(gl_shader_stage stage);
1356
1357 unsigned
1358 brw_prog_key_size(gl_shader_stage stage);
1359
1360 void
1361 brw_prog_key_set_id(union brw_any_prog_key *key, gl_shader_stage, unsigned id);
1362
1363 /**
1364 * Compile a vertex shader.
1365 *
1366 * Returns the final assembly and the program's size.
1367 */
1368 const unsigned *
1369 brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
1370 void *mem_ctx,
1371 const struct brw_vs_prog_key *key,
1372 struct brw_vs_prog_data *prog_data,
1373 struct nir_shader *shader,
1374 int shader_time_index,
1375 struct brw_compile_stats *stats,
1376 char **error_str);
1377
1378 /**
1379 * Compile a tessellation control shader.
1380 *
1381 * Returns the final assembly and the program's size.
1382 */
1383 const unsigned *
1384 brw_compile_tcs(const struct brw_compiler *compiler,
1385 void *log_data,
1386 void *mem_ctx,
1387 const struct brw_tcs_prog_key *key,
1388 struct brw_tcs_prog_data *prog_data,
1389 struct nir_shader *nir,
1390 int shader_time_index,
1391 struct brw_compile_stats *stats,
1392 char **error_str);
1393
1394 /**
1395 * Compile a tessellation evaluation shader.
1396 *
1397 * Returns the final assembly and the program's size.
1398 */
1399 const unsigned *
1400 brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
1401 void *mem_ctx,
1402 const struct brw_tes_prog_key *key,
1403 const struct brw_vue_map *input_vue_map,
1404 struct brw_tes_prog_data *prog_data,
1405 struct nir_shader *shader,
1406 int shader_time_index,
1407 struct brw_compile_stats *stats,
1408 char **error_str);
1409
1410 /**
1411 * Compile a vertex shader.
1412 *
1413 * Returns the final assembly and the program's size.
1414 */
1415 const unsigned *
1416 brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
1417 void *mem_ctx,
1418 const struct brw_gs_prog_key *key,
1419 struct brw_gs_prog_data *prog_data,
1420 struct nir_shader *shader,
1421 struct gl_program *prog,
1422 int shader_time_index,
1423 struct brw_compile_stats *stats,
1424 char **error_str);
1425
1426 /**
1427 * Compile a strips and fans shader.
1428 *
1429 * This is a fixed-function shader determined entirely by the shader key and
1430 * a VUE map.
1431 *
1432 * Returns the final assembly and the program's size.
1433 */
1434 const unsigned *
1435 brw_compile_sf(const struct brw_compiler *compiler,
1436 void *mem_ctx,
1437 const struct brw_sf_prog_key *key,
1438 struct brw_sf_prog_data *prog_data,
1439 struct brw_vue_map *vue_map,
1440 unsigned *final_assembly_size);
1441
1442 /**
1443 * Compile a clipper shader.
1444 *
1445 * This is a fixed-function shader determined entirely by the shader key and
1446 * a VUE map.
1447 *
1448 * Returns the final assembly and the program's size.
1449 */
1450 const unsigned *
1451 brw_compile_clip(const struct brw_compiler *compiler,
1452 void *mem_ctx,
1453 const struct brw_clip_prog_key *key,
1454 struct brw_clip_prog_data *prog_data,
1455 struct brw_vue_map *vue_map,
1456 unsigned *final_assembly_size);
1457
1458 /**
1459 * Compile a fragment shader.
1460 *
1461 * Returns the final assembly and the program's size.
1462 */
1463 const unsigned *
1464 brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
1465 void *mem_ctx,
1466 const struct brw_wm_prog_key *key,
1467 struct brw_wm_prog_data *prog_data,
1468 struct nir_shader *shader,
1469 int shader_time_index8,
1470 int shader_time_index16,
1471 int shader_time_index32,
1472 bool allow_spilling,
1473 bool use_rep_send, struct brw_vue_map *vue_map,
1474 struct brw_compile_stats *stats, /**< Array of three stats */
1475 char **error_str);
1476
1477 /**
1478 * Compile a compute shader.
1479 *
1480 * Returns the final assembly and the program's size.
1481 */
1482 const unsigned *
1483 brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
1484 void *mem_ctx,
1485 const struct brw_cs_prog_key *key,
1486 struct brw_cs_prog_data *prog_data,
1487 const struct nir_shader *shader,
1488 int shader_time_index,
1489 struct brw_compile_stats *stats,
1490 char **error_str);
1491
1492 void brw_debug_key_recompile(const struct brw_compiler *c, void *log,
1493 gl_shader_stage stage,
1494 const struct brw_base_prog_key *old_key,
1495 const struct brw_base_prog_key *key);
1496
1497 static inline uint32_t
1498 encode_slm_size(unsigned gen, uint32_t bytes)
1499 {
1500 uint32_t slm_size = 0;
1501
1502 /* Shared Local Memory is specified as powers of two, and encoded in
1503 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1504 *
1505 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1506 * -------------------------------------------------------------------
1507 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1508 * -------------------------------------------------------------------
1509 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1510 */
1511 assert(bytes <= 64 * 1024);
1512
1513 if (bytes > 0) {
1514 /* Shared Local Memory Size is specified as powers of two. */
1515 slm_size = util_next_power_of_two(bytes);
1516
1517 if (gen >= 9) {
1518 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1519 slm_size = ffs(MAX2(slm_size, 1024)) - 10;
1520 } else {
1521 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1522 slm_size = MAX2(slm_size, 4096) / 4096;
1523 }
1524 }
1525
1526 return slm_size;
1527 }
1528
1529 unsigned
1530 brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data,
1531 unsigned threads);
1532
1533 unsigned
1534 brw_cs_simd_size_for_group_size(const struct gen_device_info *devinfo,
1535 const struct brw_cs_prog_data *cs_prog_data,
1536 unsigned group_size);
1537
1538 /**
1539 * Calculate the RightExecutionMask field used in GPGPU_WALKER.
1540 */
1541 static inline unsigned
1542 brw_cs_right_mask(unsigned group_size, unsigned simd_size)
1543 {
1544 const uint32_t remainder = group_size & (simd_size - 1);
1545 if (remainder > 0)
1546 return ~0u >> (32 - remainder);
1547 else
1548 return ~0u >> (32 - simd_size);
1549 }
1550
1551 /**
1552 * Return true if the given shader stage is dispatched contiguously by the
1553 * relevant fixed function starting from channel 0 of the SIMD thread, which
1554 * implies that the dispatch mask of a thread can be assumed to have the form
1555 * '2^n - 1' for some n.
1556 */
1557 static inline bool
1558 brw_stage_has_packed_dispatch(ASSERTED const struct gen_device_info *devinfo,
1559 gl_shader_stage stage,
1560 const struct brw_stage_prog_data *prog_data)
1561 {
1562 /* The code below makes assumptions about the hardware's thread dispatch
1563 * behavior that could be proven wrong in future generations -- Make sure
1564 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1565 * the NIR front-end before changing this assertion.
1566 */
1567 assert(devinfo->gen <= 12);
1568
1569 switch (stage) {
1570 case MESA_SHADER_FRAGMENT: {
1571 /* The PSD discards subspans coming in with no lit samples, which in the
1572 * per-pixel shading case implies that each subspan will either be fully
1573 * lit (due to the VMask being used to allow derivative computations),
1574 * or not dispatched at all. In per-sample dispatch mode individual
1575 * samples from the same subspan have a fixed relative location within
1576 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1577 * general and we should return false.
1578 */
1579 const struct brw_wm_prog_data *wm_prog_data =
1580 (const struct brw_wm_prog_data *)prog_data;
1581 return !wm_prog_data->persample_dispatch;
1582 }
1583 case MESA_SHADER_COMPUTE:
1584 /* Compute shaders will be spawned with either a fully enabled dispatch
1585 * mask or with whatever bottom/right execution mask was given to the
1586 * GPGPU walker command to be used along the workgroup edges -- In both
1587 * cases the dispatch mask is required to be tightly packed for our
1588 * invocation index calculations to work.
1589 */
1590 return true;
1591 default:
1592 /* Most remaining fixed functions are limited to use a packed dispatch
1593 * mask due to the hardware representation of the dispatch mask as a
1594 * single counter representing the number of enabled channels.
1595 */
1596 return true;
1597 }
1598 }
1599
1600 /**
1601 * Computes the first varying slot in the URB produced by the previous stage
1602 * that is used in the next stage. We do this by testing the varying slots in
1603 * the previous stage's vue map against the inputs read in the next stage.
1604 *
1605 * Note that:
1606 *
1607 * - Each URB offset contains two varying slots and we can only skip a
1608 * full offset if both slots are unused, so the value we return here is always
1609 * rounded down to the closest multiple of two.
1610 *
1611 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1612 * part of the vue header, so if these are read we can't skip anything.
1613 */
1614 static inline int
1615 brw_compute_first_urb_slot_required(uint64_t inputs_read,
1616 const struct brw_vue_map *prev_stage_vue_map)
1617 {
1618 if ((inputs_read & (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT)) == 0) {
1619 for (int i = 0; i < prev_stage_vue_map->num_slots; i++) {
1620 int varying = prev_stage_vue_map->slot_to_varying[i];
1621 if (varying > 0 && (inputs_read & BITFIELD64_BIT(varying)) != 0)
1622 return ROUND_DOWN_TO(i, 2);
1623 }
1624 }
1625
1626 return 0;
1627 }
1628
1629 #ifdef __cplusplus
1630 } /* extern "C" */
1631 #endif
1632
1633 #endif /* BRW_COMPILER_H */