2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
106 * Base Address? (If not, it's a normal GPU address.)
108 bool constant_buffer_0_is_relative
;
111 * Whether or not the driver supports pull constants. If not, the compiler
112 * will attempt to push everything.
114 bool supports_pull_constants
;
118 * We use a constant subgroup size of 32. It really only needs to be a
119 * maximum and, since we do SIMD32 for compute shaders in some cases, it
120 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
121 * subgroup size of 32 but will act as if 16 or 24 of those channels are
124 #define BRW_SUBGROUP_SIZE 32
127 * Program key structures.
129 * When drawing, we look for the currently bound shaders in the program
130 * cache. This is essentially a hash table lookup, and these are the keys.
132 * Sometimes OpenGL features specified as state need to be simulated via
133 * shader code, due to a mismatch between the API and the hardware. This
134 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
135 * in the program key so it's considered when searching for a program. If
136 * we haven't seen a particular combination before, we have to recompile a
137 * new specialized version.
139 * Shader compilation should not look up state in gl_context directly, but
140 * instead use the copy in the program key. This guarantees recompiles will
146 enum PACKED gen6_gather_sampler_wa
{
147 WA_SIGN
= 1, /* whether we need to sign extend */
148 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
149 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
153 * Sampler information needed by VS, WM, and GS program cache keys.
155 struct brw_sampler_prog_key_data
{
157 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
159 uint16_t swizzles
[MAX_SAMPLERS
];
161 uint32_t gl_clamp_mask
[3];
164 * For RG32F, gather4's channel select is broken.
166 uint32_t gather_channel_quirk_mask
;
169 * Whether this sampler uses the compressed multisample surface layout.
171 uint32_t compressed_multisample_layout_mask
;
174 * Whether this sampler is using 16x multisampling. If so fetching from
175 * this sampler will be handled with a different instruction, ld2dms_w
181 * For Sandybridge, which shader w/a we need for gather quirks.
183 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
186 * Texture units that have a YUV image bound.
188 uint32_t y_u_v_image_mask
;
189 uint32_t y_uv_image_mask
;
190 uint32_t yx_xuxv_image_mask
;
191 uint32_t xy_uxvx_image_mask
;
195 * The VF can't natively handle certain types of attributes, such as GL_FIXED
196 * or most 10_10_10_2 types. These flags enable various VS workarounds to
197 * "fix" attributes at the beginning of shaders.
199 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
200 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
201 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
202 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
203 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
206 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
207 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
208 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
209 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
211 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
212 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
214 /** The program key for Vertex Shaders. */
215 struct brw_vs_prog_key
{
216 unsigned program_string_id
;
219 * Per-attribute workaround flags
221 * For each attribute, a combination of BRW_ATTRIB_WA_*.
223 * For OpenGL, where we expose a maximum of 16 user input atttributes
224 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
225 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
226 * expose up to 28 user input vertex attributes that are mapped to slots
227 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
228 * enough to hold this many slots.
230 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
232 bool copy_edgeflag
:1;
234 bool clamp_vertex_color
:1;
237 * How many user clipping planes are being uploaded to the vertex shader as
240 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
243 unsigned nr_userclip_plane_consts
:4;
246 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
247 * are going to be replaced with point coordinates (as a consequence of a
248 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
249 * our SF thread requires exact matching between VS outputs and FS inputs,
250 * these texture coordinates will need to be unconditionally included in
251 * the VUE, even if they aren't written by the vertex shader.
253 uint8_t point_coord_replace
;
255 struct brw_sampler_prog_key_data tex
;
258 /** The program key for Tessellation Control Shaders. */
259 struct brw_tcs_prog_key
261 unsigned program_string_id
;
263 GLenum tes_primitive_mode
;
265 unsigned input_vertices
;
267 /** A bitfield of per-patch outputs written. */
268 uint32_t patch_outputs_written
;
270 /** A bitfield of per-vertex outputs written. */
271 uint64_t outputs_written
;
273 bool quads_workaround
;
275 struct brw_sampler_prog_key_data tex
;
278 /** The program key for Tessellation Evaluation Shaders. */
279 struct brw_tes_prog_key
281 unsigned program_string_id
;
283 /** A bitfield of per-patch inputs read. */
284 uint32_t patch_inputs_read
;
286 /** A bitfield of per-vertex inputs read. */
287 uint64_t inputs_read
;
289 struct brw_sampler_prog_key_data tex
;
292 /** The program key for Geometry Shaders. */
293 struct brw_gs_prog_key
295 unsigned program_string_id
;
297 struct brw_sampler_prog_key_data tex
;
300 enum brw_sf_primitive
{
301 BRW_SF_PRIM_POINTS
= 0,
302 BRW_SF_PRIM_LINES
= 1,
303 BRW_SF_PRIM_TRIANGLES
= 2,
304 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
307 struct brw_sf_prog_key
{
309 bool contains_flat_varying
;
310 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
311 uint8_t point_sprite_coord_replace
;
312 enum brw_sf_primitive primitive
:2;
313 bool do_twoside_color
:1;
314 bool frontface_ccw
:1;
315 bool do_point_sprite
:1;
316 bool do_point_coord
:1;
317 bool sprite_origin_lower_left
:1;
318 bool userclip_active
:1;
322 BRW_CLIP_MODE_NORMAL
= 0,
323 BRW_CLIP_MODE_CLIP_ALL
= 1,
324 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
325 BRW_CLIP_MODE_REJECT_ALL
= 3,
326 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
327 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
330 enum brw_clip_fill_mode
{
331 BRW_CLIP_FILL_MODE_LINE
= 0,
332 BRW_CLIP_FILL_MODE_POINT
= 1,
333 BRW_CLIP_FILL_MODE_FILL
= 2,
334 BRW_CLIP_FILL_MODE_CULL
= 3,
337 /* Note that if unfilled primitives are being emitted, we have to fix
338 * up polygon offset and flatshading at this point:
340 struct brw_clip_prog_key
{
342 bool contains_flat_varying
;
343 bool contains_noperspective_varying
;
344 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
345 unsigned primitive
:4;
346 unsigned nr_userclip
:4;
349 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
350 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
355 enum brw_clip_mode clip_mode
:3;
362 /* A big lookup table is used to figure out which and how many
363 * additional regs will inserted before the main payload in the WM
364 * program execution. These mainly relate to depth and stencil
365 * processing and the early-depth-test optimization.
367 enum brw_wm_iz_bits
{
368 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
369 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
370 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
371 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
372 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
373 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
374 BRW_WM_IZ_BIT_MAX
= 0x40
377 enum brw_wm_aa_enable
{
383 /** The program key for Fragment/Pixel Shaders. */
384 struct brw_wm_prog_key
{
385 /* Some collection of BRW_WM_IZ_* */
389 unsigned nr_color_regions
:5;
390 bool replicate_alpha
:1;
391 bool clamp_fragment_color
:1;
392 bool persample_interp
:1;
393 bool multisample_fbo
:1;
394 bool frag_coord_adds_sample_pos
:1;
395 enum brw_wm_aa_enable line_aa
:2;
396 bool high_quality_derivatives
:1;
397 bool force_dual_color_blend
:1;
398 bool coherent_fb_fetch
:1;
400 uint64_t input_slots_valid
;
401 unsigned program_string_id
;
402 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
403 float alpha_test_ref
;
405 struct brw_sampler_prog_key_data tex
;
408 struct brw_cs_prog_key
{
409 uint32_t program_string_id
;
410 struct brw_sampler_prog_key_data tex
;
413 /* brw_any_prog_key is any of the keys that map to an API stage */
414 union brw_any_prog_key
{
415 struct brw_vs_prog_key vs
;
416 struct brw_tcs_prog_key tcs
;
417 struct brw_tes_prog_key tes
;
418 struct brw_gs_prog_key gs
;
419 struct brw_wm_prog_key wm
;
420 struct brw_cs_prog_key cs
;
424 * Image metadata structure as laid out in the shader parameter
425 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
426 * able to use them. That's okay because the padding and any unused
427 * entries [most of them except when we're doing untyped surface
428 * access] will be removed by the uniform packing pass.
430 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
431 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
432 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
433 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
434 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
435 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
436 #define BRW_IMAGE_PARAM_SIZE 24
438 struct brw_image_param
{
439 /** Surface binding table index. */
440 uint32_t surface_idx
;
442 /** Offset applied to the X and Y surface coordinates. */
445 /** Surface X, Y and Z dimensions. */
448 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
449 * pixels, vertical slice stride in pixels.
453 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
457 * Right shift to apply for bit 6 address swizzling. Two different
458 * swizzles can be specified and will be applied one after the other. The
459 * resulting address will be:
461 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
462 * (addr >> swizzling[1])))
464 * Use \c 0xff if any of the swizzles is not required.
466 uint32_t swizzling
[2];
469 /** Max number of render targets in a shader */
470 #define BRW_MAX_DRAW_BUFFERS 8
473 * Max number of binding table entries used for stream output.
475 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
476 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
478 * On Gen6, the size of transform feedback data is limited not by the number
479 * of components but by the number of binding table entries we set aside. We
480 * use one binding table entry for a float, one entry for a vector, and one
481 * entry per matrix column. Since the only way we can communicate our
482 * transform feedback capabilities to the client is via
483 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
484 * worst case, in which all the varyings are floats, so we use up one binding
485 * table entry per component. Therefore we need to set aside at least 64
486 * binding table entries for use by transform feedback.
488 * Note: since we don't currently pack varyings, it is currently impossible
489 * for the client to actually use up all of these binding table entries--if
490 * all of their varyings were floats, they would run out of varying slots and
491 * fail to link. But that's a bug, so it seems prudent to go ahead and
492 * allocate the number of binding table entries we will need once the bug is
495 #define BRW_MAX_SOL_BINDINGS 64
498 * Binding table index for the first gen6 SOL binding.
500 #define BRW_GEN6_SOL_BINDING_START 0
503 * Stride in bytes between shader_time entries.
505 * We separate entries by a cacheline to reduce traffic between EUs writing to
508 #define BRW_SHADER_TIME_STRIDE 64
517 /* We reserve the first 2^16 values for builtins */
518 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
520 enum brw_param_builtin
{
521 BRW_PARAM_BUILTIN_ZERO
,
523 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
524 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
525 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
526 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
527 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
528 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
529 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
530 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
531 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
532 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
533 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
534 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
535 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
536 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
537 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
538 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
539 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
540 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
541 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
542 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
543 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
544 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
545 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
546 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
547 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
548 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
549 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
550 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
551 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
552 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
553 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
554 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
556 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
557 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
558 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
559 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
560 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
561 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
563 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
564 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
565 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
566 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
569 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
570 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
572 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
573 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
574 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
576 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
577 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
579 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
580 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
582 struct brw_stage_prog_data
{
584 /** size of our binding table. */
588 * surface indices for the various groups of surfaces
590 uint32_t pull_constants_start
;
591 uint32_t texture_start
;
592 uint32_t gather_texture_start
;
595 uint32_t image_start
;
596 uint32_t shader_time_start
;
597 uint32_t plane_start
[3];
601 struct brw_ubo_range ubo_ranges
[4];
603 GLuint nr_params
; /**< number of float params/constants */
604 GLuint nr_pull_params
;
606 unsigned curb_read_length
;
607 unsigned total_scratch
;
608 unsigned total_shared
;
610 unsigned program_size
;
613 * Register where the thread expects to find input data from the URB
614 * (typically uniforms, followed by vertex or fragment attributes).
616 unsigned dispatch_grf_start_reg
;
618 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
620 /* 32-bit identifiers for all push/pull parameters. These can be anything
621 * the driver wishes them to be; the core of the back-end compiler simply
622 * re-arranges them. The one restriction is that the bottom 2^16 values
623 * are reserved for builtins defined in the brw_param_builtin enum defined
627 uint32_t *pull_param
;
630 static inline uint32_t *
631 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
632 unsigned nr_new_params
)
634 unsigned old_nr_params
= prog_data
->nr_params
;
635 prog_data
->nr_params
+= nr_new_params
;
636 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
637 prog_data
->param
, uint32_t,
638 prog_data
->nr_params
);
639 return prog_data
->param
+ old_nr_params
;
643 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
646 /* A binding table index is 8 bits and the top 3 values are reserved for
647 * special things (stateless and SLM).
649 assert(surf_index
<= 252);
651 prog_data
->binding_table
.size_bytes
=
652 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
655 enum brw_barycentric_mode
{
656 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
657 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
658 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
659 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
660 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
661 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
662 BRW_BARYCENTRIC_MODE_COUNT
= 6
664 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
665 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
666 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
667 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
669 enum brw_pixel_shader_computed_depth_mode
{
670 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
671 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
672 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
673 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
676 /* Data about a particular attempt to compile a program. Note that
677 * there can be many of these, each in a different GL state
678 * corresponding to a different brw_wm_prog_key struct, with different
681 struct brw_wm_prog_data
{
682 struct brw_stage_prog_data base
;
684 GLuint num_varying_inputs
;
686 uint8_t reg_blocks_0
;
687 uint8_t reg_blocks_2
;
689 uint8_t dispatch_grf_start_reg_2
;
690 uint32_t prog_offset_2
;
694 * surface indices the WM-specific surfaces
696 uint32_t render_target_read_start
;
700 uint8_t computed_depth_mode
;
701 bool computed_stencil
;
703 bool early_fragment_tests
;
704 bool post_depth_coverage
;
709 bool persample_dispatch
;
710 bool uses_pos_offset
;
715 bool uses_sample_mask
;
716 bool has_render_target_reads
;
717 bool has_side_effects
;
720 bool contains_flat_varying
;
721 bool contains_noperspective_varying
;
724 * Mask of which interpolation modes are required by the fragment shader.
725 * Used in hardware setup on gen6+.
727 uint32_t barycentric_interp_modes
;
730 * Mask of which FS inputs are marked flat by the shader source. This is
731 * needed for setting up 3DSTATE_SF/SBE.
733 uint32_t flat_inputs
;
735 /* Mapping of VUE slots to interpolation modes.
736 * Used by the Gen4-5 clip/sf/wm stages.
738 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
741 * Map from gl_varying_slot to the position within the FS setup data
742 * payload where the varying's attribute vertex deltas should be delivered.
743 * For varying slots that are not used by the FS, the value is -1.
745 int urb_setup
[VARYING_SLOT_MAX
];
748 struct brw_push_const_block
{
749 unsigned dwords
; /* Dword count, not reg aligned */
751 unsigned size
; /* Bytes, register aligned */
754 struct brw_cs_prog_data
{
755 struct brw_stage_prog_data base
;
757 unsigned local_size
[3];
761 bool uses_num_work_groups
;
764 struct brw_push_const_block cross_thread
;
765 struct brw_push_const_block per_thread
;
766 struct brw_push_const_block total
;
771 * surface indices the CS-specific surfaces
773 uint32_t work_groups_start
;
779 * Enum representing the i965-specific vertex results that don't correspond
780 * exactly to any element of gl_varying_slot. The values of this enum are
781 * assigned such that they don't conflict with gl_varying_slot.
785 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
786 BRW_VARYING_SLOT_PAD
,
788 * Technically this is not a varying but just a placeholder that
789 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
790 * builtin variable to be compiled correctly. see compile_sf_prog() for
793 BRW_VARYING_SLOT_PNTC
,
794 BRW_VARYING_SLOT_COUNT
798 * We always program SF to start reading at an offset of 1 (2 varying slots)
799 * from the start of the vertex URB entry. This causes it to skip:
800 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
801 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
803 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
806 * Bitmask indicating which fragment shader inputs represent varyings (and
807 * hence have to be delivered to the fragment shader by the SF/SBE stage).
809 #define BRW_FS_VARYING_INPUT_MASK \
810 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
811 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
814 * Data structure recording the relationship between the gl_varying_slot enum
815 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
816 * single octaword within the VUE (128 bits).
818 * Note that each BRW register contains 256 bits (2 octawords), so when
819 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
820 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
821 * in a vertex shader), each register corresponds to a single VUE slot, since
822 * it contains data for two separate vertices.
826 * Bitfield representing all varying slots that are (a) stored in this VUE
827 * map, and (b) actually written by the shader. Does not include any of
828 * the additional varying slots defined in brw_varying_slot.
830 uint64_t slots_valid
;
833 * Is this VUE map for a separate shader pipeline?
835 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
836 * without the linker having a chance to dead code eliminate unused varyings.
838 * This means that we have to use a fixed slot layout, based on the output's
839 * location field, rather than assigning slots in a compact contiguous block.
844 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
845 * not stored in a slot (because they are not written, or because
846 * additional processing is applied before storing them in the VUE), the
849 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
852 * Map from VUE slot to gl_varying_slot value. For slots that do not
853 * directly correspond to a gl_varying_slot, the value comes from
856 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
858 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
861 * Total number of VUE slots in use
866 * Number of per-patch VUE slots. Only valid for tessellation control
867 * shader outputs and tessellation evaluation shader inputs.
869 int num_per_patch_slots
;
872 * Number of per-vertex VUE slots. Only valid for tessellation control
873 * shader outputs and tessellation evaluation shader inputs.
875 int num_per_vertex_slots
;
878 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
881 * Convert a VUE slot number into a byte offset within the VUE.
883 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
889 * Convert a vertex output (brw_varying_slot) into a byte offset within the
893 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
895 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
898 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
899 struct brw_vue_map
*vue_map
,
900 uint64_t slots_valid
,
901 bool separate_shader
);
903 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
904 uint64_t slots_valid
,
907 /* brw_interpolation_map.c */
908 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
909 struct nir_shader
*nir
,
910 struct brw_wm_prog_data
*prog_data
,
911 const struct gen_device_info
*devinfo
);
913 enum shader_dispatch_mode
{
914 DISPATCH_MODE_4X1_SINGLE
= 0,
915 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
916 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
917 DISPATCH_MODE_SIMD8
= 3,
921 * @defgroup Tessellator parameter enumerations.
923 * These correspond to the hardware values in 3DSTATE_TE, and are provided
924 * as part of the tessellation evaluation shader.
928 enum brw_tess_partitioning
{
929 BRW_TESS_PARTITIONING_INTEGER
= 0,
930 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
931 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
934 enum brw_tess_output_topology
{
935 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
936 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
937 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
938 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
941 enum brw_tess_domain
{
942 BRW_TESS_DOMAIN_QUAD
= 0,
943 BRW_TESS_DOMAIN_TRI
= 1,
944 BRW_TESS_DOMAIN_ISOLINE
= 2,
948 struct brw_vue_prog_data
{
949 struct brw_stage_prog_data base
;
950 struct brw_vue_map vue_map
;
952 /** Should the hardware deliver input VUE handles for URB pull loads? */
953 bool include_vue_handles
;
955 GLuint urb_read_length
;
958 uint32_t clip_distance_mask
;
959 uint32_t cull_distance_mask
;
961 /* Used for calculating urb partitions. In the VS, this is the size of the
962 * URB entry used for both input and output to the thread. In the GS, this
963 * is the size of the URB entry used for output.
965 GLuint urb_entry_size
;
967 enum shader_dispatch_mode dispatch_mode
;
970 struct brw_vs_prog_data
{
971 struct brw_vue_prog_data base
;
973 GLbitfield64 inputs_read
;
974 GLbitfield64 double_inputs_read
;
976 unsigned nr_attribute_slots
;
979 bool uses_instanceid
;
980 bool uses_basevertex
;
981 bool uses_baseinstance
;
985 struct brw_tcs_prog_data
987 struct brw_vue_prog_data base
;
989 /** Number vertices in output patch */
994 struct brw_tes_prog_data
996 struct brw_vue_prog_data base
;
998 enum brw_tess_partitioning partitioning
;
999 enum brw_tess_output_topology output_topology
;
1000 enum brw_tess_domain domain
;
1003 struct brw_gs_prog_data
1005 struct brw_vue_prog_data base
;
1007 unsigned vertices_in
;
1010 * Size of an output vertex, measured in HWORDS (32 bytes).
1012 unsigned output_vertex_size_hwords
;
1014 unsigned output_topology
;
1017 * Size of the control data (cut bits or StreamID bits), in hwords (32
1018 * bytes). 0 if there is no control data.
1020 unsigned control_data_header_size_hwords
;
1023 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1024 * if the control data is StreamID bits, or
1025 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1026 * Ignored if control_data_header_size is 0.
1028 unsigned control_data_format
;
1030 bool include_primitive_id
;
1033 * The number of vertices emitted, if constant - otherwise -1.
1035 int static_vertex_count
;
1040 * Gen6: Provoking vertex convention for odd-numbered triangles
1046 * Gen6: Number of varyings that are output to transform feedback.
1048 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1051 * Gen6: Map from the index of a transform feedback binding table entry to the
1052 * gl_varying_slot that should be streamed out through that binding table
1055 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1058 * Gen6: Map from the index of a transform feedback binding table entry to the
1059 * swizzles that should be used when streaming out data through that
1060 * binding table entry.
1062 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1065 struct brw_sf_prog_data
{
1066 uint32_t urb_read_length
;
1069 /* Each vertex may have upto 12 attributes, 4 components each,
1070 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1073 * Actually we use 4 for each, so call it 12 rows.
1075 unsigned urb_entry_size
;
1078 struct brw_clip_prog_data
{
1079 uint32_t curb_read_length
; /* user planes? */
1081 uint32_t urb_read_length
;
1085 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1086 union brw_any_prog_data
{
1087 struct brw_stage_prog_data base
;
1088 struct brw_vue_prog_data vue
;
1089 struct brw_vs_prog_data vs
;
1090 struct brw_tcs_prog_data tcs
;
1091 struct brw_tes_prog_data tes
;
1092 struct brw_gs_prog_data gs
;
1093 struct brw_wm_prog_data wm
;
1094 struct brw_cs_prog_data cs
;
1097 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1098 static inline struct brw_##stage##_prog_data * \
1099 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1101 return (struct brw_##stage##_prog_data *) prog_data; \
1103 DEFINE_PROG_DATA_DOWNCAST(vue
)
1104 DEFINE_PROG_DATA_DOWNCAST(vs
)
1105 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1106 DEFINE_PROG_DATA_DOWNCAST(tes
)
1107 DEFINE_PROG_DATA_DOWNCAST(gs
)
1108 DEFINE_PROG_DATA_DOWNCAST(wm
)
1109 DEFINE_PROG_DATA_DOWNCAST(cs
)
1110 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1111 DEFINE_PROG_DATA_DOWNCAST(clip
)
1112 DEFINE_PROG_DATA_DOWNCAST(sf
)
1113 #undef DEFINE_PROG_DATA_DOWNCAST
1117 struct brw_compiler
*
1118 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1121 brw_prog_data_size(gl_shader_stage stage
);
1124 brw_prog_key_size(gl_shader_stage stage
);
1127 * Compile a vertex shader.
1129 * Returns the final assembly and the program's size.
1132 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1134 const struct brw_vs_prog_key
*key
,
1135 struct brw_vs_prog_data
*prog_data
,
1136 const struct nir_shader
*shader
,
1137 int shader_time_index
,
1141 * Compile a tessellation control shader.
1143 * Returns the final assembly and the program's size.
1146 brw_compile_tcs(const struct brw_compiler
*compiler
,
1149 const struct brw_tcs_prog_key
*key
,
1150 struct brw_tcs_prog_data
*prog_data
,
1151 const struct nir_shader
*nir
,
1152 int shader_time_index
,
1156 * Compile a tessellation evaluation shader.
1158 * Returns the final assembly and the program's size.
1161 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1163 const struct brw_tes_prog_key
*key
,
1164 const struct brw_vue_map
*input_vue_map
,
1165 struct brw_tes_prog_data
*prog_data
,
1166 const struct nir_shader
*shader
,
1167 struct gl_program
*prog
,
1168 int shader_time_index
,
1172 * Compile a vertex shader.
1174 * Returns the final assembly and the program's size.
1177 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1179 const struct brw_gs_prog_key
*key
,
1180 struct brw_gs_prog_data
*prog_data
,
1181 const struct nir_shader
*shader
,
1182 struct gl_program
*prog
,
1183 int shader_time_index
,
1187 * Compile a strips and fans shader.
1189 * This is a fixed-function shader determined entirely by the shader key and
1192 * Returns the final assembly and the program's size.
1195 brw_compile_sf(const struct brw_compiler
*compiler
,
1197 const struct brw_sf_prog_key
*key
,
1198 struct brw_sf_prog_data
*prog_data
,
1199 struct brw_vue_map
*vue_map
,
1200 unsigned *final_assembly_size
);
1203 * Compile a clipper shader.
1205 * This is a fixed-function shader determined entirely by the shader key and
1208 * Returns the final assembly and the program's size.
1211 brw_compile_clip(const struct brw_compiler
*compiler
,
1213 const struct brw_clip_prog_key
*key
,
1214 struct brw_clip_prog_data
*prog_data
,
1215 struct brw_vue_map
*vue_map
,
1216 unsigned *final_assembly_size
);
1219 * Compile a fragment shader.
1221 * Returns the final assembly and the program's size.
1224 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1226 const struct brw_wm_prog_key
*key
,
1227 struct brw_wm_prog_data
*prog_data
,
1228 const struct nir_shader
*shader
,
1229 struct gl_program
*prog
,
1230 int shader_time_index8
,
1231 int shader_time_index16
,
1232 bool allow_spilling
,
1233 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1237 * Compile a compute shader.
1239 * Returns the final assembly and the program's size.
1242 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1244 const struct brw_cs_prog_key
*key
,
1245 struct brw_cs_prog_data
*prog_data
,
1246 const struct nir_shader
*shader
,
1247 int shader_time_index
,
1250 static inline uint32_t
1251 encode_slm_size(unsigned gen
, uint32_t bytes
)
1253 uint32_t slm_size
= 0;
1255 /* Shared Local Memory is specified as powers of two, and encoded in
1256 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1258 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1259 * -------------------------------------------------------------------
1260 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1261 * -------------------------------------------------------------------
1262 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1264 assert(bytes
<= 64 * 1024);
1267 /* Shared Local Memory Size is specified as powers of two. */
1268 slm_size
= util_next_power_of_two(bytes
);
1271 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1272 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1274 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1275 slm_size
= MAX2(slm_size
, 4096) / 4096;
1283 * Return true if the given shader stage is dispatched contiguously by the
1284 * relevant fixed function starting from channel 0 of the SIMD thread, which
1285 * implies that the dispatch mask of a thread can be assumed to have the form
1286 * '2^n - 1' for some n.
1289 brw_stage_has_packed_dispatch(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
1290 gl_shader_stage stage
,
1291 const struct brw_stage_prog_data
*prog_data
)
1293 /* The code below makes assumptions about the hardware's thread dispatch
1294 * behavior that could be proven wrong in future generations -- Make sure
1295 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1296 * the NIR front-end before changing this assertion.
1298 assert(devinfo
->gen
<= 11);
1301 case MESA_SHADER_FRAGMENT
: {
1302 /* The PSD discards subspans coming in with no lit samples, which in the
1303 * per-pixel shading case implies that each subspan will either be fully
1304 * lit (due to the VMask being used to allow derivative computations),
1305 * or not dispatched at all. In per-sample dispatch mode individual
1306 * samples from the same subspan have a fixed relative location within
1307 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1308 * general and we should return false.
1310 const struct brw_wm_prog_data
*wm_prog_data
=
1311 (const struct brw_wm_prog_data
*)prog_data
;
1312 return !wm_prog_data
->persample_dispatch
;
1314 case MESA_SHADER_COMPUTE
:
1315 /* Compute shaders will be spawned with either a fully enabled dispatch
1316 * mask or with whatever bottom/right execution mask was given to the
1317 * GPGPU walker command to be used along the workgroup edges -- In both
1318 * cases the dispatch mask is required to be tightly packed for our
1319 * invocation index calculations to work.
1323 /* Most remaining fixed functions are limited to use a packed dispatch
1324 * mask due to the hardware representation of the dispatch mask as a
1325 * single counter representing the number of enabled channels.
1332 * Computes the first varying slot in the URB produced by the previous stage
1333 * that is used in the next stage. We do this by testing the varying slots in
1334 * the previous stage's vue map against the inputs read in the next stage.
1338 * - Each URB offset contains two varying slots and we can only skip a
1339 * full offset if both slots are unused, so the value we return here is always
1340 * rounded down to the closest multiple of two.
1342 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1343 * part of the vue header, so if these are read we can't skip anything.
1346 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1347 const struct brw_vue_map
*prev_stage_vue_map
)
1349 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1350 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1351 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1352 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1353 return ROUND_DOWN_TO(i
, 2);
1364 #endif /* BRW_COMPILER_H */