2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned barycentrics we use for PLN, which doesn't
89 int aligned_bary_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
97 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
100 * Apply workarounds for SIN and COS output range problems.
101 * This can negatively impact performance.
106 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
107 * Base Address? (If not, it's a normal GPU address.)
109 bool constant_buffer_0_is_relative
;
112 * Whether or not the driver supports pull constants. If not, the compiler
113 * will attempt to push everything.
115 bool supports_pull_constants
;
118 * Whether or not the driver supports NIR shader constants. This controls
119 * whether nir_opt_large_constants will be run.
121 bool supports_shader_constants
;
124 * Whether or not the driver wants uniform params to be compacted by the
130 * Whether or not the driver wants variable group size to be lowered by the
133 bool lower_variable_group_size
;
137 * We use a constant subgroup size of 32. It really only needs to be a
138 * maximum and, since we do SIMD32 for compute shaders in some cases, it
139 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
140 * subgroup size of 32 but will act as if 16 or 24 of those channels are
143 #define BRW_SUBGROUP_SIZE 32
146 * Program key structures.
148 * When drawing, we look for the currently bound shaders in the program
149 * cache. This is essentially a hash table lookup, and these are the keys.
151 * Sometimes OpenGL features specified as state need to be simulated via
152 * shader code, due to a mismatch between the API and the hardware. This
153 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
154 * in the program key so it's considered when searching for a program. If
155 * we haven't seen a particular combination before, we have to recompile a
156 * new specialized version.
158 * Shader compilation should not look up state in gl_context directly, but
159 * instead use the copy in the program key. This guarantees recompiles will
165 enum PACKED gen6_gather_sampler_wa
{
166 WA_SIGN
= 1, /* whether we need to sign extend */
167 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
168 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
172 * Sampler information needed by VS, WM, and GS program cache keys.
174 struct brw_sampler_prog_key_data
{
176 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
178 uint16_t swizzles
[MAX_SAMPLERS
];
180 uint32_t gl_clamp_mask
[3];
183 * For RG32F, gather4's channel select is broken.
185 uint32_t gather_channel_quirk_mask
;
188 * Whether this sampler uses the compressed multisample surface layout.
190 uint32_t compressed_multisample_layout_mask
;
193 * Whether this sampler is using 16x multisampling. If so fetching from
194 * this sampler will be handled with a different instruction, ld2dms_w
200 * For Sandybridge, which shader w/a we need for gather quirks.
202 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
205 * Texture units that have a YUV image bound.
207 uint32_t y_u_v_image_mask
;
208 uint32_t y_uv_image_mask
;
209 uint32_t yx_xuxv_image_mask
;
210 uint32_t xy_uxvx_image_mask
;
211 uint32_t ayuv_image_mask
;
212 uint32_t xyuv_image_mask
;
214 /* Scale factor for each texture. */
215 float scale_factors
[32];
218 /** An enum representing what kind of input gl_SubgroupSize is. */
219 enum PACKED brw_subgroup_size_type
221 BRW_SUBGROUP_SIZE_API_CONSTANT
, /**< Default Vulkan behavior */
222 BRW_SUBGROUP_SIZE_UNIFORM
, /**< OpenGL behavior */
223 BRW_SUBGROUP_SIZE_VARYING
, /**< VK_EXT_subgroup_size_control */
225 /* These enums are specifically chosen so that the value of the enum is
226 * also the subgroup size. If any new values are added, they must respect
229 BRW_SUBGROUP_SIZE_REQUIRE_8
= 8, /**< VK_EXT_subgroup_size_control */
230 BRW_SUBGROUP_SIZE_REQUIRE_16
= 16, /**< VK_EXT_subgroup_size_control */
231 BRW_SUBGROUP_SIZE_REQUIRE_32
= 32, /**< VK_EXT_subgroup_size_control */
234 struct brw_base_prog_key
{
235 unsigned program_string_id
;
237 enum brw_subgroup_size_type subgroup_size_type
;
239 struct brw_sampler_prog_key_data tex
;
243 * The VF can't natively handle certain types of attributes, such as GL_FIXED
244 * or most 10_10_10_2 types. These flags enable various VS workarounds to
245 * "fix" attributes at the beginning of shaders.
247 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
248 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
249 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
250 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
251 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
254 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
255 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
256 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
257 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
259 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
260 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
262 /** The program key for Vertex Shaders. */
263 struct brw_vs_prog_key
{
264 struct brw_base_prog_key base
;
267 * Per-attribute workaround flags
269 * For each attribute, a combination of BRW_ATTRIB_WA_*.
271 * For OpenGL, where we expose a maximum of 16 user input atttributes
272 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
273 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
274 * expose up to 28 user input vertex attributes that are mapped to slots
275 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
276 * enough to hold this many slots.
278 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
280 bool copy_edgeflag
:1;
282 bool clamp_vertex_color
:1;
285 * How many user clipping planes are being uploaded to the vertex shader as
288 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
291 unsigned nr_userclip_plane_consts
:4;
294 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
295 * are going to be replaced with point coordinates (as a consequence of a
296 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
297 * our SF thread requires exact matching between VS outputs and FS inputs,
298 * these texture coordinates will need to be unconditionally included in
299 * the VUE, even if they aren't written by the vertex shader.
301 uint8_t point_coord_replace
;
304 /** The program key for Tessellation Control Shaders. */
305 struct brw_tcs_prog_key
307 struct brw_base_prog_key base
;
309 GLenum tes_primitive_mode
;
311 unsigned input_vertices
;
313 /** A bitfield of per-patch outputs written. */
314 uint32_t patch_outputs_written
;
316 /** A bitfield of per-vertex outputs written. */
317 uint64_t outputs_written
;
319 bool quads_workaround
;
322 /** The program key for Tessellation Evaluation Shaders. */
323 struct brw_tes_prog_key
325 struct brw_base_prog_key base
;
327 /** A bitfield of per-patch inputs read. */
328 uint32_t patch_inputs_read
;
330 /** A bitfield of per-vertex inputs read. */
331 uint64_t inputs_read
;
334 * How many user clipping planes are being uploaded to the tessellation
335 * evaluation shader as push constants.
337 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
340 unsigned nr_userclip_plane_consts
:4;
343 /** The program key for Geometry Shaders. */
344 struct brw_gs_prog_key
346 struct brw_base_prog_key base
;
349 * How many user clipping planes are being uploaded to the geometry shader
352 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
355 unsigned nr_userclip_plane_consts
:4;
358 enum brw_sf_primitive
{
359 BRW_SF_PRIM_POINTS
= 0,
360 BRW_SF_PRIM_LINES
= 1,
361 BRW_SF_PRIM_TRIANGLES
= 2,
362 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
365 struct brw_sf_prog_key
{
367 bool contains_flat_varying
;
368 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
369 uint8_t point_sprite_coord_replace
;
370 enum brw_sf_primitive primitive
:2;
371 bool do_twoside_color
:1;
372 bool frontface_ccw
:1;
373 bool do_point_sprite
:1;
374 bool do_point_coord
:1;
375 bool sprite_origin_lower_left
:1;
376 bool userclip_active
:1;
380 BRW_CLIP_MODE_NORMAL
= 0,
381 BRW_CLIP_MODE_CLIP_ALL
= 1,
382 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
383 BRW_CLIP_MODE_REJECT_ALL
= 3,
384 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
385 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
388 enum brw_clip_fill_mode
{
389 BRW_CLIP_FILL_MODE_LINE
= 0,
390 BRW_CLIP_FILL_MODE_POINT
= 1,
391 BRW_CLIP_FILL_MODE_FILL
= 2,
392 BRW_CLIP_FILL_MODE_CULL
= 3,
395 /* Note that if unfilled primitives are being emitted, we have to fix
396 * up polygon offset and flatshading at this point:
398 struct brw_clip_prog_key
{
400 bool contains_flat_varying
;
401 bool contains_noperspective_varying
;
402 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
403 unsigned primitive
:4;
404 unsigned nr_userclip
:4;
407 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
408 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
413 enum brw_clip_mode clip_mode
:3;
420 /* A big lookup table is used to figure out which and how many
421 * additional regs will inserted before the main payload in the WM
422 * program execution. These mainly relate to depth and stencil
423 * processing and the early-depth-test optimization.
425 enum brw_wm_iz_bits
{
426 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
427 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
428 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
429 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
430 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
431 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
432 BRW_WM_IZ_BIT_MAX
= 0x40
435 enum brw_wm_aa_enable
{
441 /** The program key for Fragment/Pixel Shaders. */
442 struct brw_wm_prog_key
{
443 struct brw_base_prog_key base
;
445 /* Some collection of BRW_WM_IZ_* */
449 unsigned nr_color_regions
:5;
450 bool alpha_test_replicate_alpha
:1;
451 bool alpha_to_coverage
:1;
452 bool clamp_fragment_color
:1;
453 bool persample_interp
:1;
454 bool multisample_fbo
:1;
455 bool frag_coord_adds_sample_pos
:1;
456 enum brw_wm_aa_enable line_aa
:2;
457 bool high_quality_derivatives
:1;
458 bool force_dual_color_blend
:1;
459 bool coherent_fb_fetch
:1;
460 bool ignore_sample_mask_out
:1;
462 uint8_t color_outputs_valid
;
463 uint64_t input_slots_valid
;
464 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
465 float alpha_test_ref
;
468 struct brw_cs_prog_key
{
469 struct brw_base_prog_key base
;
472 /* brw_any_prog_key is any of the keys that map to an API stage */
473 union brw_any_prog_key
{
474 struct brw_base_prog_key base
;
475 struct brw_vs_prog_key vs
;
476 struct brw_tcs_prog_key tcs
;
477 struct brw_tes_prog_key tes
;
478 struct brw_gs_prog_key gs
;
479 struct brw_wm_prog_key wm
;
480 struct brw_cs_prog_key cs
;
484 * Image metadata structure as laid out in the shader parameter
485 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
486 * able to use them. That's okay because the padding and any unused
487 * entries [most of them except when we're doing untyped surface
488 * access] will be removed by the uniform packing pass.
490 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
491 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
492 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
493 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
494 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
495 #define BRW_IMAGE_PARAM_SIZE 20
497 struct brw_image_param
{
498 /** Offset applied to the X and Y surface coordinates. */
501 /** Surface X, Y and Z dimensions. */
504 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
505 * pixels, vertical slice stride in pixels.
509 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
513 * Right shift to apply for bit 6 address swizzling. Two different
514 * swizzles can be specified and will be applied one after the other. The
515 * resulting address will be:
517 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
518 * (addr >> swizzling[1])))
520 * Use \c 0xff if any of the swizzles is not required.
522 uint32_t swizzling
[2];
525 /** Max number of render targets in a shader */
526 #define BRW_MAX_DRAW_BUFFERS 8
529 * Max number of binding table entries used for stream output.
531 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
532 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
534 * On Gen6, the size of transform feedback data is limited not by the number
535 * of components but by the number of binding table entries we set aside. We
536 * use one binding table entry for a float, one entry for a vector, and one
537 * entry per matrix column. Since the only way we can communicate our
538 * transform feedback capabilities to the client is via
539 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
540 * worst case, in which all the varyings are floats, so we use up one binding
541 * table entry per component. Therefore we need to set aside at least 64
542 * binding table entries for use by transform feedback.
544 * Note: since we don't currently pack varyings, it is currently impossible
545 * for the client to actually use up all of these binding table entries--if
546 * all of their varyings were floats, they would run out of varying slots and
547 * fail to link. But that's a bug, so it seems prudent to go ahead and
548 * allocate the number of binding table entries we will need once the bug is
551 #define BRW_MAX_SOL_BINDINGS 64
554 * Binding table index for the first gen6 SOL binding.
556 #define BRW_GEN6_SOL_BINDING_START 0
559 * Stride in bytes between shader_time entries.
561 * We separate entries by a cacheline to reduce traffic between EUs writing to
564 #define BRW_SHADER_TIME_STRIDE 64
573 /* We reserve the first 2^16 values for builtins */
574 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
576 enum brw_param_builtin
{
577 BRW_PARAM_BUILTIN_ZERO
,
579 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
580 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
581 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
582 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
583 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
584 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
585 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
586 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
587 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
588 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
589 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
590 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
591 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
592 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
593 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
594 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
595 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
596 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
597 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
598 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
599 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
600 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
601 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
602 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
603 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
604 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
605 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
606 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
607 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
608 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
609 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
610 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
612 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
613 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
614 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
615 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
616 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
617 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
619 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
,
621 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
622 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
623 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
624 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
625 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
,
626 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Y
,
627 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z
,
630 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
631 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
633 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
634 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
635 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
637 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
638 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
640 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
641 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
643 struct brw_stage_prog_data
{
645 /** size of our binding table. */
649 * surface indices for the various groups of surfaces
651 uint32_t pull_constants_start
;
652 uint32_t texture_start
;
653 uint32_t gather_texture_start
;
656 uint32_t image_start
;
657 uint32_t shader_time_start
;
658 uint32_t plane_start
[3];
662 struct brw_ubo_range ubo_ranges
[4];
664 GLuint nr_params
; /**< number of float params/constants */
665 GLuint nr_pull_params
;
667 /* zero_push_reg is a bitfield which indicates what push registers (if any)
668 * should be zeroed by SW at the start of the shader. The corresponding
669 * push_reg_mask_param specifies the param index (in 32-bit units) where
670 * the actual runtime 64-bit mask will be pushed. The shader will zero
673 * reg_used & zero_push_reg & ~*push_reg_mask_param & (1ull << i)
675 * If this field is set, brw_compiler::compact_params must be false.
677 uint64_t zero_push_reg
;
678 unsigned push_reg_mask_param
;
680 unsigned curb_read_length
;
681 unsigned total_scratch
;
682 unsigned total_shared
;
684 unsigned program_size
;
686 /** Does this program pull from any UBO or other constant buffers? */
690 * Register where the thread expects to find input data from the URB
691 * (typically uniforms, followed by vertex or fragment attributes).
693 unsigned dispatch_grf_start_reg
;
695 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
697 /* 32-bit identifiers for all push/pull parameters. These can be anything
698 * the driver wishes them to be; the core of the back-end compiler simply
699 * re-arranges them. The one restriction is that the bottom 2^16 values
700 * are reserved for builtins defined in the brw_param_builtin enum defined
704 uint32_t *pull_param
;
706 /* Whether shader uses atomic operations. */
707 bool uses_atomic_load_store
;
710 static inline uint32_t *
711 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
712 unsigned nr_new_params
)
714 unsigned old_nr_params
= prog_data
->nr_params
;
715 prog_data
->nr_params
+= nr_new_params
;
716 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
717 prog_data
->param
, uint32_t,
718 prog_data
->nr_params
);
719 return prog_data
->param
+ old_nr_params
;
722 enum brw_barycentric_mode
{
723 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
724 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
725 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
726 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
727 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
728 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
729 BRW_BARYCENTRIC_MODE_COUNT
= 6
731 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
732 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
733 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
734 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
736 enum brw_pixel_shader_computed_depth_mode
{
737 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
738 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
739 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
740 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
743 /* Data about a particular attempt to compile a program. Note that
744 * there can be many of these, each in a different GL state
745 * corresponding to a different brw_wm_prog_key struct, with different
748 struct brw_wm_prog_data
{
749 struct brw_stage_prog_data base
;
751 GLuint num_varying_inputs
;
753 uint8_t reg_blocks_8
;
754 uint8_t reg_blocks_16
;
755 uint8_t reg_blocks_32
;
757 uint8_t dispatch_grf_start_reg_16
;
758 uint8_t dispatch_grf_start_reg_32
;
759 uint32_t prog_offset_16
;
760 uint32_t prog_offset_32
;
764 * surface indices the WM-specific surfaces
766 uint32_t render_target_read_start
;
770 uint8_t computed_depth_mode
;
771 bool computed_stencil
;
773 bool early_fragment_tests
;
774 bool post_depth_coverage
;
780 bool persample_dispatch
;
781 bool uses_pos_offset
;
786 bool uses_sample_mask
;
787 bool has_render_target_reads
;
788 bool has_side_effects
;
791 bool contains_flat_varying
;
792 bool contains_noperspective_varying
;
795 * Mask of which interpolation modes are required by the fragment shader.
796 * Used in hardware setup on gen6+.
798 uint32_t barycentric_interp_modes
;
801 * Mask of which FS inputs are marked flat by the shader source. This is
802 * needed for setting up 3DSTATE_SF/SBE.
804 uint32_t flat_inputs
;
811 /* Mapping of VUE slots to interpolation modes.
812 * Used by the Gen4-5 clip/sf/wm stages.
814 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
817 * Map from gl_varying_slot to the position within the FS setup data
818 * payload where the varying's attribute vertex deltas should be delivered.
819 * For varying slots that are not used by the FS, the value is -1.
821 int urb_setup
[VARYING_SLOT_MAX
];
824 * Cache structure into the urb_setup array above that contains the
825 * attribute numbers of active varyings out of urb_setup.
826 * The actual count is stored in urb_setup_attribs_count.
828 uint8_t urb_setup_attribs
[VARYING_SLOT_MAX
];
829 uint8_t urb_setup_attribs_count
;
832 /** Returns the SIMD width corresponding to a given KSP index
834 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
835 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
836 * kernel start pointer (KSP) indices that is based on what dispatch widths
837 * are enabled. This function provides, effectively, the reverse mapping.
839 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
840 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
842 static inline unsigned
843 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
844 bool simd16_enabled
, bool simd32_enabled
)
846 /* This function strictly ignores contiguous dispatch */
849 return simd8_enabled
? 8 :
850 (simd16_enabled
&& !simd32_enabled
) ? 16 :
851 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
853 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
855 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
857 unreachable("Invalid KSP index");
861 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
862 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
863 (wm_state)._16PixelDispatchEnable, \
864 (wm_state)._32PixelDispatchEnable)
866 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
867 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
869 static inline uint32_t
870 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
873 switch (simd_width
) {
875 case 16: return prog_data
->prog_offset_16
;
876 case 32: return prog_data
->prog_offset_32
;
881 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
882 _brw_wm_prog_data_prog_offset(prog_data, \
883 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
885 static inline uint8_t
886 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
889 switch (simd_width
) {
890 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
891 case 16: return prog_data
->dispatch_grf_start_reg_16
;
892 case 32: return prog_data
->dispatch_grf_start_reg_32
;
897 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
898 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
899 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
901 static inline uint8_t
902 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
905 switch (simd_width
) {
906 case 8: return prog_data
->reg_blocks_8
;
907 case 16: return prog_data
->reg_blocks_16
;
908 case 32: return prog_data
->reg_blocks_32
;
913 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
914 _brw_wm_prog_data_reg_blocks(prog_data, \
915 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
917 struct brw_push_const_block
{
918 unsigned dwords
; /* Dword count, not reg aligned */
920 unsigned size
; /* Bytes, register aligned */
923 struct brw_cs_prog_data
{
924 struct brw_stage_prog_data base
;
926 unsigned local_size
[3];
929 /* Program offsets for the 8/16/32 SIMD variants. Multiple variants are
930 * kept when using variable group size, and the right one can only be
931 * decided at dispatch time.
933 unsigned prog_offset
[3];
935 /* Bitmask indicating which program offsets are valid. */
938 /* Bitmask indicating which programs have spilled. */
939 unsigned prog_spilled
;
942 bool uses_num_work_groups
;
945 struct brw_push_const_block cross_thread
;
946 struct brw_push_const_block per_thread
;
951 * surface indices the CS-specific surfaces
953 uint32_t work_groups_start
;
958 static inline uint32_t
959 brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data
*prog_data
,
960 unsigned dispatch_width
)
962 assert(dispatch_width
== 8 ||
963 dispatch_width
== 16 ||
964 dispatch_width
== 32);
965 const unsigned index
= dispatch_width
/ 16;
966 assert(prog_data
->prog_mask
& (1 << index
));
967 return prog_data
->prog_offset
[index
];
971 * Enum representing the i965-specific vertex results that don't correspond
972 * exactly to any element of gl_varying_slot. The values of this enum are
973 * assigned such that they don't conflict with gl_varying_slot.
977 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
978 BRW_VARYING_SLOT_PAD
,
980 * Technically this is not a varying but just a placeholder that
981 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
982 * builtin variable to be compiled correctly. see compile_sf_prog() for
985 BRW_VARYING_SLOT_PNTC
,
986 BRW_VARYING_SLOT_COUNT
990 * We always program SF to start reading at an offset of 1 (2 varying slots)
991 * from the start of the vertex URB entry. This causes it to skip:
992 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
993 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
995 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
998 * Bitmask indicating which fragment shader inputs represent varyings (and
999 * hence have to be delivered to the fragment shader by the SF/SBE stage).
1001 #define BRW_FS_VARYING_INPUT_MASK \
1002 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
1003 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
1006 * Data structure recording the relationship between the gl_varying_slot enum
1007 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
1008 * single octaword within the VUE (128 bits).
1010 * Note that each BRW register contains 256 bits (2 octawords), so when
1011 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
1012 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
1013 * in a vertex shader), each register corresponds to a single VUE slot, since
1014 * it contains data for two separate vertices.
1016 struct brw_vue_map
{
1018 * Bitfield representing all varying slots that are (a) stored in this VUE
1019 * map, and (b) actually written by the shader. Does not include any of
1020 * the additional varying slots defined in brw_varying_slot.
1022 uint64_t slots_valid
;
1025 * Is this VUE map for a separate shader pipeline?
1027 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
1028 * without the linker having a chance to dead code eliminate unused varyings.
1030 * This means that we have to use a fixed slot layout, based on the output's
1031 * location field, rather than assigning slots in a compact contiguous block.
1036 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
1037 * not stored in a slot (because they are not written, or because
1038 * additional processing is applied before storing them in the VUE), the
1041 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
1044 * Map from VUE slot to gl_varying_slot value. For slots that do not
1045 * directly correspond to a gl_varying_slot, the value comes from
1048 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
1050 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
1053 * Total number of VUE slots in use
1058 * Number of per-patch VUE slots. Only valid for tessellation control
1059 * shader outputs and tessellation evaluation shader inputs.
1061 int num_per_patch_slots
;
1064 * Number of per-vertex VUE slots. Only valid for tessellation control
1065 * shader outputs and tessellation evaluation shader inputs.
1067 int num_per_vertex_slots
;
1070 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
1073 * Convert a VUE slot number into a byte offset within the VUE.
1075 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
1081 * Convert a vertex output (brw_varying_slot) into a byte offset within the
1085 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
1087 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
1090 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
1091 struct brw_vue_map
*vue_map
,
1092 uint64_t slots_valid
,
1093 bool separate_shader
,
1094 uint32_t pos_slots
);
1096 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
1097 uint64_t slots_valid
,
1100 /* brw_interpolation_map.c */
1101 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
1102 struct nir_shader
*nir
,
1103 struct brw_wm_prog_data
*prog_data
);
1105 enum shader_dispatch_mode
{
1106 DISPATCH_MODE_4X1_SINGLE
= 0,
1107 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
1108 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
1109 DISPATCH_MODE_SIMD8
= 3,
1111 DISPATCH_MODE_TCS_SINGLE_PATCH
= 0,
1112 DISPATCH_MODE_TCS_8_PATCH
= 2,
1116 * @defgroup Tessellator parameter enumerations.
1118 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1119 * as part of the tessellation evaluation shader.
1123 enum brw_tess_partitioning
{
1124 BRW_TESS_PARTITIONING_INTEGER
= 0,
1125 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1126 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1129 enum brw_tess_output_topology
{
1130 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1131 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1132 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1133 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1136 enum brw_tess_domain
{
1137 BRW_TESS_DOMAIN_QUAD
= 0,
1138 BRW_TESS_DOMAIN_TRI
= 1,
1139 BRW_TESS_DOMAIN_ISOLINE
= 2,
1143 struct brw_vue_prog_data
{
1144 struct brw_stage_prog_data base
;
1145 struct brw_vue_map vue_map
;
1147 /** Should the hardware deliver input VUE handles for URB pull loads? */
1148 bool include_vue_handles
;
1150 GLuint urb_read_length
;
1153 uint32_t clip_distance_mask
;
1154 uint32_t cull_distance_mask
;
1156 /* Used for calculating urb partitions. In the VS, this is the size of the
1157 * URB entry used for both input and output to the thread. In the GS, this
1158 * is the size of the URB entry used for output.
1160 GLuint urb_entry_size
;
1162 enum shader_dispatch_mode dispatch_mode
;
1165 struct brw_vs_prog_data
{
1166 struct brw_vue_prog_data base
;
1168 GLbitfield64 inputs_read
;
1169 GLbitfield64 double_inputs_read
;
1171 unsigned nr_attribute_slots
;
1174 bool uses_instanceid
;
1175 bool uses_is_indexed_draw
;
1176 bool uses_firstvertex
;
1177 bool uses_baseinstance
;
1181 struct brw_tcs_prog_data
1183 struct brw_vue_prog_data base
;
1185 /** Should the non-SINGLE_PATCH payload provide primitive ID? */
1186 bool include_primitive_id
;
1188 /** Number vertices in output patch */
1191 /** Track patch count threshold */
1192 int patch_count_threshold
;
1196 struct brw_tes_prog_data
1198 struct brw_vue_prog_data base
;
1200 enum brw_tess_partitioning partitioning
;
1201 enum brw_tess_output_topology output_topology
;
1202 enum brw_tess_domain domain
;
1205 struct brw_gs_prog_data
1207 struct brw_vue_prog_data base
;
1209 unsigned vertices_in
;
1212 * Size of an output vertex, measured in HWORDS (32 bytes).
1214 unsigned output_vertex_size_hwords
;
1216 unsigned output_topology
;
1219 * Size of the control data (cut bits or StreamID bits), in hwords (32
1220 * bytes). 0 if there is no control data.
1222 unsigned control_data_header_size_hwords
;
1225 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1226 * if the control data is StreamID bits, or
1227 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1228 * Ignored if control_data_header_size is 0.
1230 unsigned control_data_format
;
1232 bool include_primitive_id
;
1235 * The number of vertices emitted, if constant - otherwise -1.
1237 int static_vertex_count
;
1242 * Gen6: Provoking vertex convention for odd-numbered triangles
1248 * Gen6: Number of varyings that are output to transform feedback.
1250 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1253 * Gen6: Map from the index of a transform feedback binding table entry to the
1254 * gl_varying_slot that should be streamed out through that binding table
1257 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1260 * Gen6: Map from the index of a transform feedback binding table entry to the
1261 * swizzles that should be used when streaming out data through that
1262 * binding table entry.
1264 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1267 struct brw_sf_prog_data
{
1268 uint32_t urb_read_length
;
1271 /* Each vertex may have upto 12 attributes, 4 components each,
1272 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1275 * Actually we use 4 for each, so call it 12 rows.
1277 unsigned urb_entry_size
;
1280 struct brw_clip_prog_data
{
1281 uint32_t curb_read_length
; /* user planes? */
1283 uint32_t urb_read_length
;
1287 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1288 union brw_any_prog_data
{
1289 struct brw_stage_prog_data base
;
1290 struct brw_vue_prog_data vue
;
1291 struct brw_vs_prog_data vs
;
1292 struct brw_tcs_prog_data tcs
;
1293 struct brw_tes_prog_data tes
;
1294 struct brw_gs_prog_data gs
;
1295 struct brw_wm_prog_data wm
;
1296 struct brw_cs_prog_data cs
;
1299 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1300 static inline struct brw_##stage##_prog_data * \
1301 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1303 return (struct brw_##stage##_prog_data *) prog_data; \
1305 static inline const struct brw_##stage##_prog_data * \
1306 brw_##stage##_prog_data_const(const struct brw_stage_prog_data *prog_data) \
1308 return (const struct brw_##stage##_prog_data *) prog_data; \
1310 DEFINE_PROG_DATA_DOWNCAST(vue
)
1311 DEFINE_PROG_DATA_DOWNCAST(vs
)
1312 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1313 DEFINE_PROG_DATA_DOWNCAST(tes
)
1314 DEFINE_PROG_DATA_DOWNCAST(gs
)
1315 DEFINE_PROG_DATA_DOWNCAST(wm
)
1316 DEFINE_PROG_DATA_DOWNCAST(cs
)
1317 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1318 DEFINE_PROG_DATA_DOWNCAST(clip
)
1319 DEFINE_PROG_DATA_DOWNCAST(sf
)
1320 #undef DEFINE_PROG_DATA_DOWNCAST
1322 struct brw_compile_stats
{
1323 uint32_t dispatch_width
; /**< 0 for vec4 */
1324 uint32_t instructions
;
1334 struct brw_compiler
*
1335 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1338 * Returns a compiler configuration for use with disk shader cache
1340 * This value only needs to change for settings that can cause different
1341 * program generation between two runs on the same hardware.
1343 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1344 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1347 brw_get_compiler_config_value(const struct brw_compiler
*compiler
);
1350 brw_prog_data_size(gl_shader_stage stage
);
1353 brw_prog_key_size(gl_shader_stage stage
);
1356 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage
, unsigned id
);
1359 * Compile a vertex shader.
1361 * Returns the final assembly and the program's size.
1364 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1366 const struct brw_vs_prog_key
*key
,
1367 struct brw_vs_prog_data
*prog_data
,
1368 struct nir_shader
*shader
,
1369 int shader_time_index
,
1370 struct brw_compile_stats
*stats
,
1374 * Compile a tessellation control shader.
1376 * Returns the final assembly and the program's size.
1379 brw_compile_tcs(const struct brw_compiler
*compiler
,
1382 const struct brw_tcs_prog_key
*key
,
1383 struct brw_tcs_prog_data
*prog_data
,
1384 struct nir_shader
*nir
,
1385 int shader_time_index
,
1386 struct brw_compile_stats
*stats
,
1390 * Compile a tessellation evaluation shader.
1392 * Returns the final assembly and the program's size.
1395 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1397 const struct brw_tes_prog_key
*key
,
1398 const struct brw_vue_map
*input_vue_map
,
1399 struct brw_tes_prog_data
*prog_data
,
1400 struct nir_shader
*shader
,
1401 int shader_time_index
,
1402 struct brw_compile_stats
*stats
,
1406 * Compile a vertex shader.
1408 * Returns the final assembly and the program's size.
1411 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1413 const struct brw_gs_prog_key
*key
,
1414 struct brw_gs_prog_data
*prog_data
,
1415 struct nir_shader
*shader
,
1416 struct gl_program
*prog
,
1417 int shader_time_index
,
1418 struct brw_compile_stats
*stats
,
1422 * Compile a strips and fans shader.
1424 * This is a fixed-function shader determined entirely by the shader key and
1427 * Returns the final assembly and the program's size.
1430 brw_compile_sf(const struct brw_compiler
*compiler
,
1432 const struct brw_sf_prog_key
*key
,
1433 struct brw_sf_prog_data
*prog_data
,
1434 struct brw_vue_map
*vue_map
,
1435 unsigned *final_assembly_size
);
1438 * Compile a clipper shader.
1440 * This is a fixed-function shader determined entirely by the shader key and
1443 * Returns the final assembly and the program's size.
1446 brw_compile_clip(const struct brw_compiler
*compiler
,
1448 const struct brw_clip_prog_key
*key
,
1449 struct brw_clip_prog_data
*prog_data
,
1450 struct brw_vue_map
*vue_map
,
1451 unsigned *final_assembly_size
);
1454 * Compile a fragment shader.
1456 * Returns the final assembly and the program's size.
1459 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1461 const struct brw_wm_prog_key
*key
,
1462 struct brw_wm_prog_data
*prog_data
,
1463 struct nir_shader
*shader
,
1464 int shader_time_index8
,
1465 int shader_time_index16
,
1466 int shader_time_index32
,
1467 bool allow_spilling
,
1468 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1469 struct brw_compile_stats
*stats
, /**< Array of three stats */
1473 * Compile a compute shader.
1475 * Returns the final assembly and the program's size.
1478 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1480 const struct brw_cs_prog_key
*key
,
1481 struct brw_cs_prog_data
*prog_data
,
1482 const struct nir_shader
*shader
,
1483 int shader_time_index
,
1484 struct brw_compile_stats
*stats
,
1487 void brw_debug_key_recompile(const struct brw_compiler
*c
, void *log
,
1488 gl_shader_stage stage
,
1489 const struct brw_base_prog_key
*old_key
,
1490 const struct brw_base_prog_key
*key
);
1492 static inline uint32_t
1493 encode_slm_size(unsigned gen
, uint32_t bytes
)
1495 uint32_t slm_size
= 0;
1497 /* Shared Local Memory is specified as powers of two, and encoded in
1498 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1500 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1501 * -------------------------------------------------------------------
1502 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1503 * -------------------------------------------------------------------
1504 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1506 assert(bytes
<= 64 * 1024);
1509 /* Shared Local Memory Size is specified as powers of two. */
1510 slm_size
= util_next_power_of_two(bytes
);
1513 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1514 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1516 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1517 slm_size
= MAX2(slm_size
, 4096) / 4096;
1525 brw_cs_push_const_total_size(const struct brw_cs_prog_data
*cs_prog_data
,
1529 brw_cs_simd_size_for_group_size(const struct gen_device_info
*devinfo
,
1530 const struct brw_cs_prog_data
*cs_prog_data
,
1531 unsigned group_size
);
1534 * Calculate the RightExecutionMask field used in GPGPU_WALKER.
1536 static inline unsigned
1537 brw_cs_right_mask(unsigned group_size
, unsigned simd_size
)
1539 const uint32_t remainder
= group_size
& (simd_size
- 1);
1541 return ~0u >> (32 - remainder
);
1543 return ~0u >> (32 - simd_size
);
1547 * Return true if the given shader stage is dispatched contiguously by the
1548 * relevant fixed function starting from channel 0 of the SIMD thread, which
1549 * implies that the dispatch mask of a thread can be assumed to have the form
1550 * '2^n - 1' for some n.
1553 brw_stage_has_packed_dispatch(ASSERTED
const struct gen_device_info
*devinfo
,
1554 gl_shader_stage stage
,
1555 const struct brw_stage_prog_data
*prog_data
)
1557 /* The code below makes assumptions about the hardware's thread dispatch
1558 * behavior that could be proven wrong in future generations -- Make sure
1559 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1560 * the NIR front-end before changing this assertion.
1562 assert(devinfo
->gen
<= 12);
1565 case MESA_SHADER_FRAGMENT
: {
1566 /* The PSD discards subspans coming in with no lit samples, which in the
1567 * per-pixel shading case implies that each subspan will either be fully
1568 * lit (due to the VMask being used to allow derivative computations),
1569 * or not dispatched at all. In per-sample dispatch mode individual
1570 * samples from the same subspan have a fixed relative location within
1571 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1572 * general and we should return false.
1574 const struct brw_wm_prog_data
*wm_prog_data
=
1575 (const struct brw_wm_prog_data
*)prog_data
;
1576 return !wm_prog_data
->persample_dispatch
;
1578 case MESA_SHADER_COMPUTE
:
1579 /* Compute shaders will be spawned with either a fully enabled dispatch
1580 * mask or with whatever bottom/right execution mask was given to the
1581 * GPGPU walker command to be used along the workgroup edges -- In both
1582 * cases the dispatch mask is required to be tightly packed for our
1583 * invocation index calculations to work.
1587 /* Most remaining fixed functions are limited to use a packed dispatch
1588 * mask due to the hardware representation of the dispatch mask as a
1589 * single counter representing the number of enabled channels.
1596 * Computes the first varying slot in the URB produced by the previous stage
1597 * that is used in the next stage. We do this by testing the varying slots in
1598 * the previous stage's vue map against the inputs read in the next stage.
1602 * - Each URB offset contains two varying slots and we can only skip a
1603 * full offset if both slots are unused, so the value we return here is always
1604 * rounded down to the closest multiple of two.
1606 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1607 * part of the vue header, so if these are read we can't skip anything.
1610 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1611 const struct brw_vue_map
*prev_stage_vue_map
)
1613 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1614 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1615 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1616 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1617 return ROUND_DOWN_TO(i
, 2);
1628 #endif /* BRW_COMPILER_H */