2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "util/ralloc.h"
41 const struct gen_device_info
*devinfo
;
47 * Array of the ra classes for the unaligned contiguous register
53 * Mapping for register-allocated objects in *regs to the first
54 * GRF for that object.
56 uint8_t *ra_reg_to_grf
;
63 * Array of the ra classes for the unaligned contiguous register
64 * block sizes used, indexed by register size.
69 * Mapping from classes to ra_reg ranges. Each of the per-size
70 * classes corresponds to a range of ra_reg nodes. This array stores
71 * those ranges in the form of first ra_reg in each class and the
72 * total number of ra_reg elements in the last array element. This
73 * way the range of the i'th class is given by:
74 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
76 int class_to_ra_reg_range
[17];
79 * Mapping for register-allocated objects in *regs to the first
80 * GRF for that object.
82 uint8_t *ra_reg_to_grf
;
85 * ra class for the aligned pairs we use for PLN, which doesn't
88 int aligned_pairs_class
;
91 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
92 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
94 bool scalar_stage
[MESA_SHADER_STAGES
];
95 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
98 * Apply workarounds for SIN and COS output range problems.
99 * This can negatively impact performance.
104 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
105 * Base Address? (If not, it's a normal GPU address.)
107 bool constant_buffer_0_is_relative
;
110 * Whether or not the driver supports pull constants. If not, the compiler
111 * will attempt to push everything.
113 bool supports_pull_constants
;
117 * We use a constant subgroup size of 32. It really only needs to be a
118 * maximum and, since we do SIMD32 for compute shaders in some cases, it
119 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
120 * subgroup size of 32 but will act as if 16 or 24 of those channels are
123 #define BRW_SUBGROUP_SIZE 32
126 * Program key structures.
128 * When drawing, we look for the currently bound shaders in the program
129 * cache. This is essentially a hash table lookup, and these are the keys.
131 * Sometimes OpenGL features specified as state need to be simulated via
132 * shader code, due to a mismatch between the API and the hardware. This
133 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
134 * in the program key so it's considered when searching for a program. If
135 * we haven't seen a particular combination before, we have to recompile a
136 * new specialized version.
138 * Shader compilation should not look up state in gl_context directly, but
139 * instead use the copy in the program key. This guarantees recompiles will
145 enum PACKED gen6_gather_sampler_wa
{
146 WA_SIGN
= 1, /* whether we need to sign extend */
147 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
148 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
152 * Sampler information needed by VS, WM, and GS program cache keys.
154 struct brw_sampler_prog_key_data
{
156 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
158 uint16_t swizzles
[MAX_SAMPLERS
];
160 uint32_t gl_clamp_mask
[3];
163 * For RG32F, gather4's channel select is broken.
165 uint32_t gather_channel_quirk_mask
;
168 * Whether this sampler uses the compressed multisample surface layout.
170 uint32_t compressed_multisample_layout_mask
;
173 * Whether this sampler is using 16x multisampling. If so fetching from
174 * this sampler will be handled with a different instruction, ld2dms_w
180 * For Sandybridge, which shader w/a we need for gather quirks.
182 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
185 * Texture units that have a YUV image bound.
187 uint32_t y_u_v_image_mask
;
188 uint32_t y_uv_image_mask
;
189 uint32_t yx_xuxv_image_mask
;
190 uint32_t xy_uxvx_image_mask
;
194 * The VF can't natively handle certain types of attributes, such as GL_FIXED
195 * or most 10_10_10_2 types. These flags enable various VS workarounds to
196 * "fix" attributes at the beginning of shaders.
198 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
199 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
200 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
201 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
202 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
205 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
206 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
207 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
208 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
210 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
211 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
213 /** The program key for Vertex Shaders. */
214 struct brw_vs_prog_key
{
215 unsigned program_string_id
;
218 * Per-attribute workaround flags
220 * For each attribute, a combination of BRW_ATTRIB_WA_*.
222 * For OpenGL, where we expose a maximum of 16 user input atttributes
223 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
224 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
225 * expose up to 28 user input vertex attributes that are mapped to slots
226 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
227 * enough to hold this many slots.
229 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
231 bool copy_edgeflag
:1;
233 bool clamp_vertex_color
:1;
236 * How many user clipping planes are being uploaded to the vertex shader as
239 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
242 unsigned nr_userclip_plane_consts
:4;
245 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
246 * are going to be replaced with point coordinates (as a consequence of a
247 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
248 * our SF thread requires exact matching between VS outputs and FS inputs,
249 * these texture coordinates will need to be unconditionally included in
250 * the VUE, even if they aren't written by the vertex shader.
252 uint8_t point_coord_replace
;
254 struct brw_sampler_prog_key_data tex
;
257 /** The program key for Tessellation Control Shaders. */
258 struct brw_tcs_prog_key
260 unsigned program_string_id
;
262 GLenum tes_primitive_mode
;
264 unsigned input_vertices
;
266 /** A bitfield of per-patch outputs written. */
267 uint32_t patch_outputs_written
;
269 /** A bitfield of per-vertex outputs written. */
270 uint64_t outputs_written
;
272 bool quads_workaround
;
274 struct brw_sampler_prog_key_data tex
;
277 /** The program key for Tessellation Evaluation Shaders. */
278 struct brw_tes_prog_key
280 unsigned program_string_id
;
282 /** A bitfield of per-patch inputs read. */
283 uint32_t patch_inputs_read
;
285 /** A bitfield of per-vertex inputs read. */
286 uint64_t inputs_read
;
288 struct brw_sampler_prog_key_data tex
;
291 /** The program key for Geometry Shaders. */
292 struct brw_gs_prog_key
294 unsigned program_string_id
;
296 struct brw_sampler_prog_key_data tex
;
299 enum brw_sf_primitive
{
300 BRW_SF_PRIM_POINTS
= 0,
301 BRW_SF_PRIM_LINES
= 1,
302 BRW_SF_PRIM_TRIANGLES
= 2,
303 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
306 struct brw_sf_prog_key
{
308 bool contains_flat_varying
;
309 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
310 uint8_t point_sprite_coord_replace
;
311 enum brw_sf_primitive primitive
:2;
312 bool do_twoside_color
:1;
313 bool frontface_ccw
:1;
314 bool do_point_sprite
:1;
315 bool do_point_coord
:1;
316 bool sprite_origin_lower_left
:1;
317 bool userclip_active
:1;
321 BRW_CLIP_MODE_NORMAL
= 0,
322 BRW_CLIP_MODE_CLIP_ALL
= 1,
323 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
324 BRW_CLIP_MODE_REJECT_ALL
= 3,
325 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
326 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
329 enum brw_clip_fill_mode
{
330 BRW_CLIP_FILL_MODE_LINE
= 0,
331 BRW_CLIP_FILL_MODE_POINT
= 1,
332 BRW_CLIP_FILL_MODE_FILL
= 2,
333 BRW_CLIP_FILL_MODE_CULL
= 3,
336 /* Note that if unfilled primitives are being emitted, we have to fix
337 * up polygon offset and flatshading at this point:
339 struct brw_clip_prog_key
{
341 bool contains_flat_varying
;
342 bool contains_noperspective_varying
;
343 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
344 unsigned primitive
:4;
345 unsigned nr_userclip
:4;
348 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
349 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
354 enum brw_clip_mode clip_mode
:3;
361 /* A big lookup table is used to figure out which and how many
362 * additional regs will inserted before the main payload in the WM
363 * program execution. These mainly relate to depth and stencil
364 * processing and the early-depth-test optimization.
366 enum brw_wm_iz_bits
{
367 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
368 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
369 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
370 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
371 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
372 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
373 BRW_WM_IZ_BIT_MAX
= 0x40
376 enum brw_wm_aa_enable
{
382 /** The program key for Fragment/Pixel Shaders. */
383 struct brw_wm_prog_key
{
384 /* Some collection of BRW_WM_IZ_* */
388 unsigned nr_color_regions
:5;
389 bool replicate_alpha
:1;
390 bool clamp_fragment_color
:1;
391 bool persample_interp
:1;
392 bool multisample_fbo
:1;
393 bool frag_coord_adds_sample_pos
:1;
394 enum brw_wm_aa_enable line_aa
:2;
395 bool high_quality_derivatives
:1;
396 bool force_dual_color_blend
:1;
397 bool coherent_fb_fetch
:1;
399 uint64_t input_slots_valid
;
400 unsigned program_string_id
;
401 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
402 float alpha_test_ref
;
404 struct brw_sampler_prog_key_data tex
;
407 struct brw_cs_prog_key
{
408 uint32_t program_string_id
;
409 struct brw_sampler_prog_key_data tex
;
412 /* brw_any_prog_key is any of the keys that map to an API stage */
413 union brw_any_prog_key
{
414 struct brw_vs_prog_key vs
;
415 struct brw_tcs_prog_key tcs
;
416 struct brw_tes_prog_key tes
;
417 struct brw_gs_prog_key gs
;
418 struct brw_wm_prog_key wm
;
419 struct brw_cs_prog_key cs
;
423 * Image metadata structure as laid out in the shader parameter
424 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
425 * able to use them. That's okay because the padding and any unused
426 * entries [most of them except when we're doing untyped surface
427 * access] will be removed by the uniform packing pass.
429 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
430 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
431 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
432 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
433 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
434 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
435 #define BRW_IMAGE_PARAM_SIZE 24
437 struct brw_image_param
{
438 /** Surface binding table index. */
439 uint32_t surface_idx
;
441 /** Offset applied to the X and Y surface coordinates. */
444 /** Surface X, Y and Z dimensions. */
447 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
448 * pixels, vertical slice stride in pixels.
452 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
456 * Right shift to apply for bit 6 address swizzling. Two different
457 * swizzles can be specified and will be applied one after the other. The
458 * resulting address will be:
460 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
461 * (addr >> swizzling[1])))
463 * Use \c 0xff if any of the swizzles is not required.
465 uint32_t swizzling
[2];
468 /** Max number of render targets in a shader */
469 #define BRW_MAX_DRAW_BUFFERS 8
472 * Max number of binding table entries used for stream output.
474 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
475 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
477 * On Gen6, the size of transform feedback data is limited not by the number
478 * of components but by the number of binding table entries we set aside. We
479 * use one binding table entry for a float, one entry for a vector, and one
480 * entry per matrix column. Since the only way we can communicate our
481 * transform feedback capabilities to the client is via
482 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
483 * worst case, in which all the varyings are floats, so we use up one binding
484 * table entry per component. Therefore we need to set aside at least 64
485 * binding table entries for use by transform feedback.
487 * Note: since we don't currently pack varyings, it is currently impossible
488 * for the client to actually use up all of these binding table entries--if
489 * all of their varyings were floats, they would run out of varying slots and
490 * fail to link. But that's a bug, so it seems prudent to go ahead and
491 * allocate the number of binding table entries we will need once the bug is
494 #define BRW_MAX_SOL_BINDINGS 64
497 * Binding table index for the first gen6 SOL binding.
499 #define BRW_GEN6_SOL_BINDING_START 0
502 * Stride in bytes between shader_time entries.
504 * We separate entries by a cacheline to reduce traffic between EUs writing to
507 #define BRW_SHADER_TIME_STRIDE 64
516 /* We reserve the first 2^16 values for builtins */
517 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
519 enum brw_param_builtin
{
520 BRW_PARAM_BUILTIN_ZERO
,
522 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
523 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
524 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
525 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
526 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
527 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
528 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
529 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
530 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
531 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
532 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
533 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
534 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
535 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
536 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
537 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
538 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
539 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
540 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
541 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
542 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
543 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
544 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
545 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
546 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
547 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
548 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
549 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
550 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
551 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
552 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
553 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
555 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
556 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
557 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
558 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
559 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
560 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
562 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
563 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
564 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
565 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
568 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
569 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
571 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
572 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
573 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
575 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
576 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
578 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
579 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
581 struct brw_stage_prog_data
{
583 /** size of our binding table. */
587 * surface indices for the various groups of surfaces
589 uint32_t pull_constants_start
;
590 uint32_t texture_start
;
591 uint32_t gather_texture_start
;
594 uint32_t image_start
;
595 uint32_t shader_time_start
;
596 uint32_t plane_start
[3];
600 struct brw_ubo_range ubo_ranges
[4];
602 GLuint nr_params
; /**< number of float params/constants */
603 GLuint nr_pull_params
;
605 unsigned curb_read_length
;
606 unsigned total_scratch
;
607 unsigned total_shared
;
609 unsigned program_size
;
612 * Register where the thread expects to find input data from the URB
613 * (typically uniforms, followed by vertex or fragment attributes).
615 unsigned dispatch_grf_start_reg
;
617 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
619 /* 32-bit identifiers for all push/pull parameters. These can be anything
620 * the driver wishes them to be; the core of the back-end compiler simply
621 * re-arranges them. The one restriction is that the bottom 2^16 values
622 * are reserved for builtins defined in the brw_param_builtin enum defined
626 uint32_t *pull_param
;
629 static inline uint32_t *
630 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
631 unsigned nr_new_params
)
633 unsigned old_nr_params
= prog_data
->nr_params
;
634 prog_data
->nr_params
+= nr_new_params
;
635 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
636 prog_data
->param
, uint32_t,
637 prog_data
->nr_params
);
638 return prog_data
->param
+ old_nr_params
;
642 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
645 /* A binding table index is 8 bits and the top 3 values are reserved for
646 * special things (stateless and SLM).
648 assert(surf_index
<= 252);
650 prog_data
->binding_table
.size_bytes
=
651 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
654 enum brw_barycentric_mode
{
655 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
656 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
657 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
658 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
659 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
660 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
661 BRW_BARYCENTRIC_MODE_COUNT
= 6
663 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
664 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
665 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
666 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
668 enum brw_pixel_shader_computed_depth_mode
{
669 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
670 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
671 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
672 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
675 /* Data about a particular attempt to compile a program. Note that
676 * there can be many of these, each in a different GL state
677 * corresponding to a different brw_wm_prog_key struct, with different
680 struct brw_wm_prog_data
{
681 struct brw_stage_prog_data base
;
683 GLuint num_varying_inputs
;
685 uint8_t reg_blocks_0
;
686 uint8_t reg_blocks_2
;
688 uint8_t dispatch_grf_start_reg_2
;
689 uint32_t prog_offset_2
;
693 * surface indices the WM-specific surfaces
695 uint32_t render_target_read_start
;
699 uint8_t computed_depth_mode
;
700 bool computed_stencil
;
702 bool early_fragment_tests
;
703 bool post_depth_coverage
;
708 bool persample_dispatch
;
709 bool uses_pos_offset
;
714 bool uses_sample_mask
;
715 bool has_render_target_reads
;
716 bool has_side_effects
;
719 bool contains_flat_varying
;
720 bool contains_noperspective_varying
;
723 * Mask of which interpolation modes are required by the fragment shader.
724 * Used in hardware setup on gen6+.
726 uint32_t barycentric_interp_modes
;
729 * Mask of which FS inputs are marked flat by the shader source. This is
730 * needed for setting up 3DSTATE_SF/SBE.
732 uint32_t flat_inputs
;
734 /* Mapping of VUE slots to interpolation modes.
735 * Used by the Gen4-5 clip/sf/wm stages.
737 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
740 * Map from gl_varying_slot to the position within the FS setup data
741 * payload where the varying's attribute vertex deltas should be delivered.
742 * For varying slots that are not used by the FS, the value is -1.
744 int urb_setup
[VARYING_SLOT_MAX
];
747 struct brw_push_const_block
{
748 unsigned dwords
; /* Dword count, not reg aligned */
750 unsigned size
; /* Bytes, register aligned */
753 struct brw_cs_prog_data
{
754 struct brw_stage_prog_data base
;
756 unsigned local_size
[3];
760 bool uses_num_work_groups
;
763 struct brw_push_const_block cross_thread
;
764 struct brw_push_const_block per_thread
;
765 struct brw_push_const_block total
;
770 * surface indices the CS-specific surfaces
772 uint32_t work_groups_start
;
778 * Enum representing the i965-specific vertex results that don't correspond
779 * exactly to any element of gl_varying_slot. The values of this enum are
780 * assigned such that they don't conflict with gl_varying_slot.
784 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
785 BRW_VARYING_SLOT_PAD
,
787 * Technically this is not a varying but just a placeholder that
788 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
789 * builtin variable to be compiled correctly. see compile_sf_prog() for
792 BRW_VARYING_SLOT_PNTC
,
793 BRW_VARYING_SLOT_COUNT
797 * We always program SF to start reading at an offset of 1 (2 varying slots)
798 * from the start of the vertex URB entry. This causes it to skip:
799 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
800 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
802 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
805 * Bitmask indicating which fragment shader inputs represent varyings (and
806 * hence have to be delivered to the fragment shader by the SF/SBE stage).
808 #define BRW_FS_VARYING_INPUT_MASK \
809 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
810 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
813 * Data structure recording the relationship between the gl_varying_slot enum
814 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
815 * single octaword within the VUE (128 bits).
817 * Note that each BRW register contains 256 bits (2 octawords), so when
818 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
819 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
820 * in a vertex shader), each register corresponds to a single VUE slot, since
821 * it contains data for two separate vertices.
825 * Bitfield representing all varying slots that are (a) stored in this VUE
826 * map, and (b) actually written by the shader. Does not include any of
827 * the additional varying slots defined in brw_varying_slot.
829 uint64_t slots_valid
;
832 * Is this VUE map for a separate shader pipeline?
834 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
835 * without the linker having a chance to dead code eliminate unused varyings.
837 * This means that we have to use a fixed slot layout, based on the output's
838 * location field, rather than assigning slots in a compact contiguous block.
843 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
844 * not stored in a slot (because they are not written, or because
845 * additional processing is applied before storing them in the VUE), the
848 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
851 * Map from VUE slot to gl_varying_slot value. For slots that do not
852 * directly correspond to a gl_varying_slot, the value comes from
855 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
857 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
860 * Total number of VUE slots in use
865 * Number of per-patch VUE slots. Only valid for tessellation control
866 * shader outputs and tessellation evaluation shader inputs.
868 int num_per_patch_slots
;
871 * Number of per-vertex VUE slots. Only valid for tessellation control
872 * shader outputs and tessellation evaluation shader inputs.
874 int num_per_vertex_slots
;
877 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
880 * Convert a VUE slot number into a byte offset within the VUE.
882 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
888 * Convert a vertex output (brw_varying_slot) into a byte offset within the
892 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
894 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
897 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
898 struct brw_vue_map
*vue_map
,
899 uint64_t slots_valid
,
900 bool separate_shader
);
902 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
903 uint64_t slots_valid
,
906 /* brw_interpolation_map.c */
907 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
908 struct nir_shader
*nir
,
909 struct brw_wm_prog_data
*prog_data
,
910 const struct gen_device_info
*devinfo
);
912 enum shader_dispatch_mode
{
913 DISPATCH_MODE_4X1_SINGLE
= 0,
914 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
915 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
916 DISPATCH_MODE_SIMD8
= 3,
920 * @defgroup Tessellator parameter enumerations.
922 * These correspond to the hardware values in 3DSTATE_TE, and are provided
923 * as part of the tessellation evaluation shader.
927 enum brw_tess_partitioning
{
928 BRW_TESS_PARTITIONING_INTEGER
= 0,
929 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
930 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
933 enum brw_tess_output_topology
{
934 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
935 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
936 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
937 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
940 enum brw_tess_domain
{
941 BRW_TESS_DOMAIN_QUAD
= 0,
942 BRW_TESS_DOMAIN_TRI
= 1,
943 BRW_TESS_DOMAIN_ISOLINE
= 2,
947 struct brw_vue_prog_data
{
948 struct brw_stage_prog_data base
;
949 struct brw_vue_map vue_map
;
951 /** Should the hardware deliver input VUE handles for URB pull loads? */
952 bool include_vue_handles
;
954 GLuint urb_read_length
;
957 uint32_t clip_distance_mask
;
958 uint32_t cull_distance_mask
;
960 /* Used for calculating urb partitions. In the VS, this is the size of the
961 * URB entry used for both input and output to the thread. In the GS, this
962 * is the size of the URB entry used for output.
964 GLuint urb_entry_size
;
966 enum shader_dispatch_mode dispatch_mode
;
969 struct brw_vs_prog_data
{
970 struct brw_vue_prog_data base
;
972 GLbitfield64 inputs_read
;
973 GLbitfield64 double_inputs_read
;
975 unsigned nr_attribute_slots
;
978 bool uses_instanceid
;
979 bool uses_basevertex
;
980 bool uses_baseinstance
;
984 struct brw_tcs_prog_data
986 struct brw_vue_prog_data base
;
988 /** Number vertices in output patch */
993 struct brw_tes_prog_data
995 struct brw_vue_prog_data base
;
997 enum brw_tess_partitioning partitioning
;
998 enum brw_tess_output_topology output_topology
;
999 enum brw_tess_domain domain
;
1002 struct brw_gs_prog_data
1004 struct brw_vue_prog_data base
;
1006 unsigned vertices_in
;
1009 * Size of an output vertex, measured in HWORDS (32 bytes).
1011 unsigned output_vertex_size_hwords
;
1013 unsigned output_topology
;
1016 * Size of the control data (cut bits or StreamID bits), in hwords (32
1017 * bytes). 0 if there is no control data.
1019 unsigned control_data_header_size_hwords
;
1022 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1023 * if the control data is StreamID bits, or
1024 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1025 * Ignored if control_data_header_size is 0.
1027 unsigned control_data_format
;
1029 bool include_primitive_id
;
1032 * The number of vertices emitted, if constant - otherwise -1.
1034 int static_vertex_count
;
1039 * Gen6: Provoking vertex convention for odd-numbered triangles
1045 * Gen6: Number of varyings that are output to transform feedback.
1047 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1050 * Gen6: Map from the index of a transform feedback binding table entry to the
1051 * gl_varying_slot that should be streamed out through that binding table
1054 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1057 * Gen6: Map from the index of a transform feedback binding table entry to the
1058 * swizzles that should be used when streaming out data through that
1059 * binding table entry.
1061 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1064 struct brw_sf_prog_data
{
1065 uint32_t urb_read_length
;
1068 /* Each vertex may have upto 12 attributes, 4 components each,
1069 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1072 * Actually we use 4 for each, so call it 12 rows.
1074 unsigned urb_entry_size
;
1077 struct brw_clip_prog_data
{
1078 uint32_t curb_read_length
; /* user planes? */
1080 uint32_t urb_read_length
;
1084 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1085 union brw_any_prog_data
{
1086 struct brw_stage_prog_data base
;
1087 struct brw_vue_prog_data vue
;
1088 struct brw_vs_prog_data vs
;
1089 struct brw_tcs_prog_data tcs
;
1090 struct brw_tes_prog_data tes
;
1091 struct brw_gs_prog_data gs
;
1092 struct brw_wm_prog_data wm
;
1093 struct brw_cs_prog_data cs
;
1096 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1097 static inline struct brw_##stage##_prog_data * \
1098 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1100 return (struct brw_##stage##_prog_data *) prog_data; \
1102 DEFINE_PROG_DATA_DOWNCAST(vue
)
1103 DEFINE_PROG_DATA_DOWNCAST(vs
)
1104 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1105 DEFINE_PROG_DATA_DOWNCAST(tes
)
1106 DEFINE_PROG_DATA_DOWNCAST(gs
)
1107 DEFINE_PROG_DATA_DOWNCAST(wm
)
1108 DEFINE_PROG_DATA_DOWNCAST(cs
)
1109 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1110 DEFINE_PROG_DATA_DOWNCAST(clip
)
1111 DEFINE_PROG_DATA_DOWNCAST(sf
)
1112 #undef DEFINE_PROG_DATA_DOWNCAST
1116 struct brw_compiler
*
1117 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1120 brw_prog_data_size(gl_shader_stage stage
);
1123 brw_prog_key_size(gl_shader_stage stage
);
1126 * Compile a vertex shader.
1128 * Returns the final assembly and the program's size.
1131 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1133 const struct brw_vs_prog_key
*key
,
1134 struct brw_vs_prog_data
*prog_data
,
1135 const struct nir_shader
*shader
,
1136 int shader_time_index
,
1140 * Compile a tessellation control shader.
1142 * Returns the final assembly and the program's size.
1145 brw_compile_tcs(const struct brw_compiler
*compiler
,
1148 const struct brw_tcs_prog_key
*key
,
1149 struct brw_tcs_prog_data
*prog_data
,
1150 const struct nir_shader
*nir
,
1151 int shader_time_index
,
1155 * Compile a tessellation evaluation shader.
1157 * Returns the final assembly and the program's size.
1160 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1162 const struct brw_tes_prog_key
*key
,
1163 const struct brw_vue_map
*input_vue_map
,
1164 struct brw_tes_prog_data
*prog_data
,
1165 const struct nir_shader
*shader
,
1166 struct gl_program
*prog
,
1167 int shader_time_index
,
1171 * Compile a vertex shader.
1173 * Returns the final assembly and the program's size.
1176 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1178 const struct brw_gs_prog_key
*key
,
1179 struct brw_gs_prog_data
*prog_data
,
1180 const struct nir_shader
*shader
,
1181 struct gl_program
*prog
,
1182 int shader_time_index
,
1186 * Compile a strips and fans shader.
1188 * This is a fixed-function shader determined entirely by the shader key and
1191 * Returns the final assembly and the program's size.
1194 brw_compile_sf(const struct brw_compiler
*compiler
,
1196 const struct brw_sf_prog_key
*key
,
1197 struct brw_sf_prog_data
*prog_data
,
1198 struct brw_vue_map
*vue_map
,
1199 unsigned *final_assembly_size
);
1202 * Compile a clipper shader.
1204 * This is a fixed-function shader determined entirely by the shader key and
1207 * Returns the final assembly and the program's size.
1210 brw_compile_clip(const struct brw_compiler
*compiler
,
1212 const struct brw_clip_prog_key
*key
,
1213 struct brw_clip_prog_data
*prog_data
,
1214 struct brw_vue_map
*vue_map
,
1215 unsigned *final_assembly_size
);
1218 * Compile a fragment shader.
1220 * Returns the final assembly and the program's size.
1223 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1225 const struct brw_wm_prog_key
*key
,
1226 struct brw_wm_prog_data
*prog_data
,
1227 const struct nir_shader
*shader
,
1228 struct gl_program
*prog
,
1229 int shader_time_index8
,
1230 int shader_time_index16
,
1231 bool allow_spilling
,
1232 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1236 * Compile a compute shader.
1238 * Returns the final assembly and the program's size.
1241 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1243 const struct brw_cs_prog_key
*key
,
1244 struct brw_cs_prog_data
*prog_data
,
1245 const struct nir_shader
*shader
,
1246 int shader_time_index
,
1249 static inline uint32_t
1250 encode_slm_size(unsigned gen
, uint32_t bytes
)
1252 uint32_t slm_size
= 0;
1254 /* Shared Local Memory is specified as powers of two, and encoded in
1255 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1257 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1258 * -------------------------------------------------------------------
1259 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1260 * -------------------------------------------------------------------
1261 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1263 assert(bytes
<= 64 * 1024);
1266 /* Shared Local Memory Size is specified as powers of two. */
1267 slm_size
= util_next_power_of_two(bytes
);
1270 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1271 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1273 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1274 slm_size
= MAX2(slm_size
, 4096) / 4096;
1282 * Return true if the given shader stage is dispatched contiguously by the
1283 * relevant fixed function starting from channel 0 of the SIMD thread, which
1284 * implies that the dispatch mask of a thread can be assumed to have the form
1285 * '2^n - 1' for some n.
1288 brw_stage_has_packed_dispatch(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
1289 gl_shader_stage stage
,
1290 const struct brw_stage_prog_data
*prog_data
)
1292 /* The code below makes assumptions about the hardware's thread dispatch
1293 * behavior that could be proven wrong in future generations -- Make sure
1294 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1295 * the NIR front-end before changing this assertion.
1297 assert(devinfo
->gen
<= 10);
1300 case MESA_SHADER_FRAGMENT
: {
1301 /* The PSD discards subspans coming in with no lit samples, which in the
1302 * per-pixel shading case implies that each subspan will either be fully
1303 * lit (due to the VMask being used to allow derivative computations),
1304 * or not dispatched at all. In per-sample dispatch mode individual
1305 * samples from the same subspan have a fixed relative location within
1306 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1307 * general and we should return false.
1309 const struct brw_wm_prog_data
*wm_prog_data
=
1310 (const struct brw_wm_prog_data
*)prog_data
;
1311 return !wm_prog_data
->persample_dispatch
;
1313 case MESA_SHADER_COMPUTE
:
1314 /* Compute shaders will be spawned with either a fully enabled dispatch
1315 * mask or with whatever bottom/right execution mask was given to the
1316 * GPGPU walker command to be used along the workgroup edges -- In both
1317 * cases the dispatch mask is required to be tightly packed for our
1318 * invocation index calculations to work.
1322 /* Most remaining fixed functions are limited to use a packed dispatch
1323 * mask due to the hardware representation of the dispatch mask as a
1324 * single counter representing the number of enabled channels.
1331 * Computes the first varying slot in the URB produced by the previous stage
1332 * that is used in the next stage. We do this by testing the varying slots in
1333 * the previous stage's vue map against the inputs read in the next stage.
1337 * - Each URB offset contains two varying slots and we can only skip a
1338 * full offset if both slots are unused, so the value we return here is always
1339 * rounded down to the closest multiple of two.
1341 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1342 * part of the vue header, so if these are read we can't skip anything.
1345 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1346 const struct brw_vue_map
*prev_stage_vue_map
)
1348 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1349 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1350 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1351 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1352 return ROUND_DOWN_TO(i
, 2);
1363 #endif /* BRW_COMPILER_H */