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24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "common/gen_device_info.h"
29 #include "main/mtypes.h"
30 #include "main/macros.h"
39 union gl_constant_value
;
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
107 * Program key structures.
109 * When drawing, we look for the currently bound shaders in the program
110 * cache. This is essentially a hash table lookup, and these are the keys.
112 * Sometimes OpenGL features specified as state need to be simulated via
113 * shader code, due to a mismatch between the API and the hardware. This
114 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
115 * in the program key so it's considered when searching for a program. If
116 * we haven't seen a particular combination before, we have to recompile a
117 * new specialized version.
119 * Shader compilation should not look up state in gl_context directly, but
120 * instead use the copy in the program key. This guarantees recompiles will
126 enum PACKED gen6_gather_sampler_wa
{
127 WA_SIGN
= 1, /* whether we need to sign extend */
128 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
129 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
133 * Sampler information needed by VS, WM, and GS program cache keys.
135 struct brw_sampler_prog_key_data
{
137 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
139 uint16_t swizzles
[MAX_SAMPLERS
];
141 uint32_t gl_clamp_mask
[3];
144 * For RG32F, gather4's channel select is broken.
146 uint32_t gather_channel_quirk_mask
;
149 * Whether this sampler uses the compressed multisample surface layout.
151 uint32_t compressed_multisample_layout_mask
;
154 * Whether this sampler is using 16x multisampling. If so fetching from
155 * this sampler will be handled with a different instruction, ld2dms_w
161 * For Sandybridge, which shader w/a we need for gather quirks.
163 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
166 * Texture units that have a YUV image bound.
168 uint32_t y_u_v_image_mask
;
169 uint32_t y_uv_image_mask
;
170 uint32_t yx_xuxv_image_mask
;
171 uint32_t xy_uxvx_image_mask
;
175 * The VF can't natively handle certain types of attributes, such as GL_FIXED
176 * or most 10_10_10_2 types. These flags enable various VS workarounds to
177 * "fix" attributes at the beginning of shaders.
179 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
180 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
181 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
182 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
183 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
185 /** The program key for Vertex Shaders. */
186 struct brw_vs_prog_key
{
187 unsigned program_string_id
;
190 * Per-attribute workaround flags
192 * For each attribute, a combination of BRW_ATTRIB_WA_*.
194 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
196 bool copy_edgeflag
:1;
198 bool clamp_vertex_color
:1;
201 * How many user clipping planes are being uploaded to the vertex shader as
204 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
207 unsigned nr_userclip_plane_consts
:4;
210 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
211 * are going to be replaced with point coordinates (as a consequence of a
212 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
213 * our SF thread requires exact matching between VS outputs and FS inputs,
214 * these texture coordinates will need to be unconditionally included in
215 * the VUE, even if they aren't written by the vertex shader.
217 uint8_t point_coord_replace
;
219 struct brw_sampler_prog_key_data tex
;
222 /** The program key for Tessellation Control Shaders. */
223 struct brw_tcs_prog_key
225 unsigned program_string_id
;
227 GLenum tes_primitive_mode
;
229 unsigned input_vertices
;
231 /** A bitfield of per-patch outputs written. */
232 uint32_t patch_outputs_written
;
234 /** A bitfield of per-vertex outputs written. */
235 uint64_t outputs_written
;
237 bool quads_workaround
;
239 struct brw_sampler_prog_key_data tex
;
242 /** The program key for Tessellation Evaluation Shaders. */
243 struct brw_tes_prog_key
245 unsigned program_string_id
;
247 /** A bitfield of per-patch inputs read. */
248 uint32_t patch_inputs_read
;
250 /** A bitfield of per-vertex inputs read. */
251 uint64_t inputs_read
;
253 struct brw_sampler_prog_key_data tex
;
256 /** The program key for Geometry Shaders. */
257 struct brw_gs_prog_key
259 unsigned program_string_id
;
261 struct brw_sampler_prog_key_data tex
;
264 enum brw_sf_primitive
{
265 BRW_SF_PRIM_POINTS
= 0,
266 BRW_SF_PRIM_LINES
= 1,
267 BRW_SF_PRIM_TRIANGLES
= 2,
268 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
271 struct brw_sf_prog_key
{
273 bool contains_flat_varying
;
274 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
275 uint8_t point_sprite_coord_replace
;
276 enum brw_sf_primitive primitive
:2;
277 bool do_twoside_color
:1;
278 bool frontface_ccw
:1;
279 bool do_point_sprite
:1;
280 bool do_point_coord
:1;
281 bool sprite_origin_lower_left
:1;
282 bool userclip_active
:1;
286 BRW_CLIP_MODE_NORMAL
= 0,
287 BRW_CLIP_MODE_CLIP_ALL
= 1,
288 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
289 BRW_CLIP_MODE_REJECT_ALL
= 3,
290 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
291 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
294 enum brw_clip_fill_mode
{
295 BRW_CLIP_FILL_MODE_LINE
= 0,
296 BRW_CLIP_FILL_MODE_POINT
= 1,
297 BRW_CLIP_FILL_MODE_FILL
= 2,
298 BRW_CLIP_FILL_MODE_CULL
= 3,
301 /* Note that if unfilled primitives are being emitted, we have to fix
302 * up polygon offset and flatshading at this point:
304 struct brw_clip_prog_key
{
306 bool contains_flat_varying
;
307 bool contains_noperspective_varying
;
308 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
309 unsigned primitive
:4;
310 unsigned nr_userclip
:4;
313 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
314 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
319 enum brw_clip_mode clip_mode
:3;
326 /* A big lookup table is used to figure out which and how many
327 * additional regs will inserted before the main payload in the WM
328 * program execution. These mainly relate to depth and stencil
329 * processing and the early-depth-test optimization.
331 enum brw_wm_iz_bits
{
332 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
333 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
334 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
335 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
336 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
337 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
338 BRW_WM_IZ_BIT_MAX
= 0x40
341 enum brw_wm_aa_enable
{
347 /** The program key for Fragment/Pixel Shaders. */
348 struct brw_wm_prog_key
{
349 /* Some collection of BRW_WM_IZ_* */
353 unsigned nr_color_regions
:5;
354 bool replicate_alpha
:1;
355 bool clamp_fragment_color
:1;
356 bool persample_interp
:1;
357 bool multisample_fbo
:1;
358 bool frag_coord_adds_sample_pos
:1;
359 enum brw_wm_aa_enable line_aa
:2;
360 bool high_quality_derivatives
:1;
361 bool force_dual_color_blend
:1;
362 bool coherent_fb_fetch
:1;
364 uint16_t drawable_height
;
365 uint64_t input_slots_valid
;
366 unsigned program_string_id
;
367 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
368 float alpha_test_ref
;
370 struct brw_sampler_prog_key_data tex
;
373 struct brw_cs_prog_key
{
374 uint32_t program_string_id
;
375 struct brw_sampler_prog_key_data tex
;
379 * Image metadata structure as laid out in the shader parameter
380 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
381 * able to use them. That's okay because the padding and any unused
382 * entries [most of them except when we're doing untyped surface
383 * access] will be removed by the uniform packing pass.
385 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
386 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
387 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
388 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
389 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
390 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
391 #define BRW_IMAGE_PARAM_SIZE 24
393 struct brw_image_param
{
394 /** Surface binding table index. */
395 uint32_t surface_idx
;
397 /** Offset applied to the X and Y surface coordinates. */
400 /** Surface X, Y and Z dimensions. */
403 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
404 * pixels, vertical slice stride in pixels.
408 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
412 * Right shift to apply for bit 6 address swizzling. Two different
413 * swizzles can be specified and will be applied one after the other. The
414 * resulting address will be:
416 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
417 * (addr >> swizzling[1])))
419 * Use \c 0xff if any of the swizzles is not required.
421 uint32_t swizzling
[2];
424 /** Max number of render targets in a shader */
425 #define BRW_MAX_DRAW_BUFFERS 8
428 * Max number of binding table entries used for stream output.
430 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
431 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
433 * On Gen6, the size of transform feedback data is limited not by the number
434 * of components but by the number of binding table entries we set aside. We
435 * use one binding table entry for a float, one entry for a vector, and one
436 * entry per matrix column. Since the only way we can communicate our
437 * transform feedback capabilities to the client is via
438 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
439 * worst case, in which all the varyings are floats, so we use up one binding
440 * table entry per component. Therefore we need to set aside at least 64
441 * binding table entries for use by transform feedback.
443 * Note: since we don't currently pack varyings, it is currently impossible
444 * for the client to actually use up all of these binding table entries--if
445 * all of their varyings were floats, they would run out of varying slots and
446 * fail to link. But that's a bug, so it seems prudent to go ahead and
447 * allocate the number of binding table entries we will need once the bug is
450 #define BRW_MAX_SOL_BINDINGS 64
453 * Binding table index for the first gen6 SOL binding.
455 #define BRW_GEN6_SOL_BINDING_START 0
458 * Stride in bytes between shader_time entries.
460 * We separate entries by a cacheline to reduce traffic between EUs writing to
463 #define BRW_SHADER_TIME_STRIDE 64
465 struct brw_stage_prog_data
{
467 /** size of our binding table. */
471 * surface indices for the various groups of surfaces
473 uint32_t pull_constants_start
;
474 uint32_t texture_start
;
475 uint32_t gather_texture_start
;
479 uint32_t image_start
;
480 uint32_t shader_time_start
;
481 uint32_t plane_start
[3];
485 GLuint nr_params
; /**< number of float params/constants */
486 GLuint nr_pull_params
;
487 unsigned nr_image_params
;
489 unsigned curb_read_length
;
490 unsigned total_scratch
;
491 unsigned total_shared
;
494 * Register where the thread expects to find input data from the URB
495 * (typically uniforms, followed by vertex or fragment attributes).
497 unsigned dispatch_grf_start_reg
;
499 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
501 /* Pointers to tracked values (only valid once
502 * _mesa_load_state_parameters has been called at runtime).
504 const union gl_constant_value
**param
;
505 const union gl_constant_value
**pull_param
;
507 /** Image metadata passed to the shader as uniforms. */
508 struct brw_image_param
*image_param
;
512 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
515 /* A binding table index is 8 bits and the top 3 values are reserved for
516 * special things (stateless and SLM).
518 assert(surf_index
<= 252);
520 prog_data
->binding_table
.size_bytes
=
521 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
524 enum brw_barycentric_mode
{
525 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
526 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
527 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
528 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
529 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
530 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
531 BRW_BARYCENTRIC_MODE_COUNT
= 6
533 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
534 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
535 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
536 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
538 enum brw_pixel_shader_computed_depth_mode
{
539 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
540 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
541 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
542 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
545 /* Data about a particular attempt to compile a program. Note that
546 * there can be many of these, each in a different GL state
547 * corresponding to a different brw_wm_prog_key struct, with different
550 struct brw_wm_prog_data
{
551 struct brw_stage_prog_data base
;
553 GLuint num_varying_inputs
;
555 uint8_t reg_blocks_0
;
556 uint8_t reg_blocks_2
;
558 uint8_t dispatch_grf_start_reg_2
;
559 uint32_t prog_offset_2
;
563 * surface indices the WM-specific surfaces
565 uint32_t render_target_start
;
566 uint32_t render_target_read_start
;
570 uint8_t computed_depth_mode
;
571 bool computed_stencil
;
573 bool early_fragment_tests
;
574 bool post_depth_coverage
;
579 bool persample_dispatch
;
580 bool uses_pos_offset
;
585 bool uses_sample_mask
;
586 bool has_side_effects
;
589 bool contains_flat_varying
;
590 bool contains_noperspective_varying
;
593 * Mask of which interpolation modes are required by the fragment shader.
594 * Used in hardware setup on gen6+.
596 uint32_t barycentric_interp_modes
;
599 * Mask of which FS inputs are marked flat by the shader source. This is
600 * needed for setting up 3DSTATE_SF/SBE.
602 uint32_t flat_inputs
;
604 /* Mapping of VUE slots to interpolation modes.
605 * Used by the Gen4-5 clip/sf/wm stages.
607 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
610 * Map from gl_varying_slot to the position within the FS setup data
611 * payload where the varying's attribute vertex deltas should be delivered.
612 * For varying slots that are not used by the FS, the value is -1.
614 int urb_setup
[VARYING_SLOT_MAX
];
617 struct brw_push_const_block
{
618 unsigned dwords
; /* Dword count, not reg aligned */
620 unsigned size
; /* Bytes, register aligned */
623 struct brw_cs_prog_data
{
624 struct brw_stage_prog_data base
;
626 GLuint dispatch_grf_start_reg_16
;
627 unsigned local_size
[3];
631 bool uses_num_work_groups
;
632 int thread_local_id_index
;
635 struct brw_push_const_block cross_thread
;
636 struct brw_push_const_block per_thread
;
637 struct brw_push_const_block total
;
642 * surface indices the CS-specific surfaces
644 uint32_t work_groups_start
;
650 * Enum representing the i965-specific vertex results that don't correspond
651 * exactly to any element of gl_varying_slot. The values of this enum are
652 * assigned such that they don't conflict with gl_varying_slot.
656 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
657 BRW_VARYING_SLOT_PAD
,
659 * Technically this is not a varying but just a placeholder that
660 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
661 * builtin variable to be compiled correctly. see compile_sf_prog() for
664 BRW_VARYING_SLOT_PNTC
,
665 BRW_VARYING_SLOT_COUNT
669 * We always program SF to start reading at an offset of 1 (2 varying slots)
670 * from the start of the vertex URB entry. This causes it to skip:
671 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
672 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
674 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
677 * Bitmask indicating which fragment shader inputs represent varyings (and
678 * hence have to be delivered to the fragment shader by the SF/SBE stage).
680 #define BRW_FS_VARYING_INPUT_MASK \
681 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
682 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
685 * Data structure recording the relationship between the gl_varying_slot enum
686 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
687 * single octaword within the VUE (128 bits).
689 * Note that each BRW register contains 256 bits (2 octawords), so when
690 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
691 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
692 * in a vertex shader), each register corresponds to a single VUE slot, since
693 * it contains data for two separate vertices.
697 * Bitfield representing all varying slots that are (a) stored in this VUE
698 * map, and (b) actually written by the shader. Does not include any of
699 * the additional varying slots defined in brw_varying_slot.
701 uint64_t slots_valid
;
704 * Is this VUE map for a separate shader pipeline?
706 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
707 * without the linker having a chance to dead code eliminate unused varyings.
709 * This means that we have to use a fixed slot layout, based on the output's
710 * location field, rather than assigning slots in a compact contiguous block.
715 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
716 * not stored in a slot (because they are not written, or because
717 * additional processing is applied before storing them in the VUE), the
720 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
723 * Map from VUE slot to gl_varying_slot value. For slots that do not
724 * directly correspond to a gl_varying_slot, the value comes from
727 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
729 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
732 * Total number of VUE slots in use
737 * Number of per-patch VUE slots. Only valid for tessellation control
738 * shader outputs and tessellation evaluation shader inputs.
740 int num_per_patch_slots
;
743 * Number of per-vertex VUE slots. Only valid for tessellation control
744 * shader outputs and tessellation evaluation shader inputs.
746 int num_per_vertex_slots
;
749 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
752 * Convert a VUE slot number into a byte offset within the VUE.
754 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
760 * Convert a vertex output (brw_varying_slot) into a byte offset within the
764 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
766 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
769 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
770 struct brw_vue_map
*vue_map
,
771 uint64_t slots_valid
,
772 bool separate_shader
);
774 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
775 uint64_t slots_valid
,
778 /* brw_interpolation_map.c */
779 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
780 struct nir_shader
*nir
,
781 struct brw_wm_prog_data
*prog_data
,
782 const struct gen_device_info
*devinfo
);
784 enum shader_dispatch_mode
{
785 DISPATCH_MODE_4X1_SINGLE
= 0,
786 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
787 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
788 DISPATCH_MODE_SIMD8
= 3,
792 * @defgroup Tessellator parameter enumerations.
794 * These correspond to the hardware values in 3DSTATE_TE, and are provided
795 * as part of the tessellation evaluation shader.
799 enum brw_tess_partitioning
{
800 BRW_TESS_PARTITIONING_INTEGER
= 0,
801 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
802 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
805 enum brw_tess_output_topology
{
806 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
807 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
808 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
809 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
812 enum brw_tess_domain
{
813 BRW_TESS_DOMAIN_QUAD
= 0,
814 BRW_TESS_DOMAIN_TRI
= 1,
815 BRW_TESS_DOMAIN_ISOLINE
= 2,
819 struct brw_vue_prog_data
{
820 struct brw_stage_prog_data base
;
821 struct brw_vue_map vue_map
;
823 /** Should the hardware deliver input VUE handles for URB pull loads? */
824 bool include_vue_handles
;
826 GLuint urb_read_length
;
829 uint32_t clip_distance_mask
;
830 uint32_t cull_distance_mask
;
832 /* Used for calculating urb partitions. In the VS, this is the size of the
833 * URB entry used for both input and output to the thread. In the GS, this
834 * is the size of the URB entry used for output.
836 GLuint urb_entry_size
;
838 enum shader_dispatch_mode dispatch_mode
;
841 struct brw_vs_prog_data
{
842 struct brw_vue_prog_data base
;
844 GLbitfield64 inputs_read
;
845 GLbitfield64 double_inputs_read
;
847 unsigned nr_attributes
;
848 unsigned nr_attribute_slots
;
851 bool uses_instanceid
;
852 bool uses_basevertex
;
853 bool uses_baseinstance
;
857 struct brw_tcs_prog_data
859 struct brw_vue_prog_data base
;
861 /** Number vertices in output patch */
866 struct brw_tes_prog_data
868 struct brw_vue_prog_data base
;
870 enum brw_tess_partitioning partitioning
;
871 enum brw_tess_output_topology output_topology
;
872 enum brw_tess_domain domain
;
875 struct brw_gs_prog_data
877 struct brw_vue_prog_data base
;
879 unsigned vertices_in
;
882 * Size of an output vertex, measured in HWORDS (32 bytes).
884 unsigned output_vertex_size_hwords
;
886 unsigned output_topology
;
889 * Size of the control data (cut bits or StreamID bits), in hwords (32
890 * bytes). 0 if there is no control data.
892 unsigned control_data_header_size_hwords
;
895 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
896 * if the control data is StreamID bits, or
897 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
898 * Ignored if control_data_header_size is 0.
900 unsigned control_data_format
;
902 bool include_primitive_id
;
905 * The number of vertices emitted, if constant - otherwise -1.
907 int static_vertex_count
;
912 * Gen6: Provoking vertex convention for odd-numbered triangles
918 * Gen6: Number of varyings that are output to transform feedback.
920 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
923 * Gen6: Map from the index of a transform feedback binding table entry to the
924 * gl_varying_slot that should be streamed out through that binding table
927 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
930 * Gen6: Map from the index of a transform feedback binding table entry to the
931 * swizzles that should be used when streaming out data through that
932 * binding table entry.
934 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
937 struct brw_sf_prog_data
{
938 uint32_t urb_read_length
;
941 /* Each vertex may have upto 12 attributes, 4 components each,
942 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
945 * Actually we use 4 for each, so call it 12 rows.
947 unsigned urb_entry_size
;
950 struct brw_clip_prog_data
{
951 uint32_t curb_read_length
; /* user planes? */
953 uint32_t urb_read_length
;
957 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
958 static inline struct brw_##stage##_prog_data * \
959 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
961 return (struct brw_##stage##_prog_data *) prog_data; \
963 DEFINE_PROG_DATA_DOWNCAST(vue
)
964 DEFINE_PROG_DATA_DOWNCAST(vs
)
965 DEFINE_PROG_DATA_DOWNCAST(tcs
)
966 DEFINE_PROG_DATA_DOWNCAST(tes
)
967 DEFINE_PROG_DATA_DOWNCAST(gs
)
968 DEFINE_PROG_DATA_DOWNCAST(wm
)
969 DEFINE_PROG_DATA_DOWNCAST(cs
)
970 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
971 DEFINE_PROG_DATA_DOWNCAST(clip
)
972 DEFINE_PROG_DATA_DOWNCAST(sf
)
973 #undef DEFINE_PROG_DATA_DOWNCAST
977 struct brw_compiler
*
978 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
981 * Compile a vertex shader.
983 * Returns the final assembly and the program's size.
986 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
988 const struct brw_vs_prog_key
*key
,
989 struct brw_vs_prog_data
*prog_data
,
990 const struct nir_shader
*shader
,
991 gl_clip_plane
*clip_planes
,
992 bool use_legacy_snorm_formula
,
993 int shader_time_index
,
994 unsigned *final_assembly_size
,
998 * Compile a tessellation control shader.
1000 * Returns the final assembly and the program's size.
1003 brw_compile_tcs(const struct brw_compiler
*compiler
,
1006 const struct brw_tcs_prog_key
*key
,
1007 struct brw_tcs_prog_data
*prog_data
,
1008 const struct nir_shader
*nir
,
1009 int shader_time_index
,
1010 unsigned *final_assembly_size
,
1014 * Compile a tessellation evaluation shader.
1016 * Returns the final assembly and the program's size.
1019 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1021 const struct brw_tes_prog_key
*key
,
1022 const struct brw_vue_map
*input_vue_map
,
1023 struct brw_tes_prog_data
*prog_data
,
1024 const struct nir_shader
*shader
,
1025 struct gl_program
*prog
,
1026 int shader_time_index
,
1027 unsigned *final_assembly_size
,
1031 * Compile a vertex shader.
1033 * Returns the final assembly and the program's size.
1036 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1038 const struct brw_gs_prog_key
*key
,
1039 struct brw_gs_prog_data
*prog_data
,
1040 const struct nir_shader
*shader
,
1041 struct gl_program
*prog
,
1042 int shader_time_index
,
1043 unsigned *final_assembly_size
,
1047 * Compile a strips and fans shader.
1049 * This is a fixed-function shader determined entirely by the shader key and
1052 * Returns the final assembly and the program's size.
1055 brw_compile_sf(const struct brw_compiler
*compiler
,
1057 const struct brw_sf_prog_key
*key
,
1058 struct brw_sf_prog_data
*prog_data
,
1059 struct brw_vue_map
*vue_map
,
1060 unsigned *final_assembly_size
);
1063 * Compile a clipper shader.
1065 * This is a fixed-function shader determined entirely by the shader key and
1068 * Returns the final assembly and the program's size.
1071 brw_compile_clip(const struct brw_compiler
*compiler
,
1073 const struct brw_clip_prog_key
*key
,
1074 struct brw_clip_prog_data
*prog_data
,
1075 struct brw_vue_map
*vue_map
,
1076 unsigned *final_assembly_size
);
1079 * Compile a fragment shader.
1081 * Returns the final assembly and the program's size.
1084 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1086 const struct brw_wm_prog_key
*key
,
1087 struct brw_wm_prog_data
*prog_data
,
1088 const struct nir_shader
*shader
,
1089 struct gl_program
*prog
,
1090 int shader_time_index8
,
1091 int shader_time_index16
,
1092 bool allow_spilling
,
1093 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1094 unsigned *final_assembly_size
,
1098 * Compile a compute shader.
1100 * Returns the final assembly and the program's size.
1103 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1105 const struct brw_cs_prog_key
*key
,
1106 struct brw_cs_prog_data
*prog_data
,
1107 const struct nir_shader
*shader
,
1108 int shader_time_index
,
1109 unsigned *final_assembly_size
,
1112 static inline uint32_t
1113 encode_slm_size(unsigned gen
, uint32_t bytes
)
1115 uint32_t slm_size
= 0;
1117 /* Shared Local Memory is specified as powers of two, and encoded in
1118 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1120 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1121 * -------------------------------------------------------------------
1122 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1123 * -------------------------------------------------------------------
1124 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1126 assert(bytes
<= 64 * 1024);
1129 /* Shared Local Memory Size is specified as powers of two. */
1130 slm_size
= util_next_power_of_two(bytes
);
1133 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1134 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1136 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1137 slm_size
= MAX2(slm_size
, 4096) / 4096;
1145 * Return true if the given shader stage is dispatched contiguously by the
1146 * relevant fixed function starting from channel 0 of the SIMD thread, which
1147 * implies that the dispatch mask of a thread can be assumed to have the form
1148 * '2^n - 1' for some n.
1151 brw_stage_has_packed_dispatch(const struct gen_device_info
*devinfo
,
1152 gl_shader_stage stage
,
1153 const struct brw_stage_prog_data
*prog_data
)
1155 /* The code below makes assumptions about the hardware's thread dispatch
1156 * behavior that could be proven wrong in future generations -- Make sure
1157 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1158 * the NIR front-end before changing this assertion.
1160 assert(devinfo
->gen
<= 10);
1163 case MESA_SHADER_FRAGMENT
: {
1164 /* The PSD discards subspans coming in with no lit samples, which in the
1165 * per-pixel shading case implies that each subspan will either be fully
1166 * lit (due to the VMask being used to allow derivative computations),
1167 * or not dispatched at all. In per-sample dispatch mode individual
1168 * samples from the same subspan have a fixed relative location within
1169 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1170 * general and we should return false.
1172 const struct brw_wm_prog_data
*wm_prog_data
=
1173 (const struct brw_wm_prog_data
*)prog_data
;
1174 return !wm_prog_data
->persample_dispatch
;
1176 case MESA_SHADER_COMPUTE
:
1177 /* Compute shaders will be spawned with either a fully enabled dispatch
1178 * mask or with whatever bottom/right execution mask was given to the
1179 * GPGPU walker command to be used along the workgroup edges -- In both
1180 * cases the dispatch mask is required to be tightly packed for our
1181 * invocation index calculations to work.
1185 /* Most remaining fixed functions are limited to use a packed dispatch
1186 * mask due to the hardware representation of the dispatch mask as a
1187 * single counter representing the number of enabled channels.
1197 #endif /* BRW_COMPILER_H */