2 * Copyright © 2010 - 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
97 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
100 * Apply workarounds for SIN and COS output range problems.
101 * This can negatively impact performance.
106 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
107 * Base Address? (If not, it's a normal GPU address.)
109 bool constant_buffer_0_is_relative
;
112 * Whether or not the driver supports pull constants. If not, the compiler
113 * will attempt to push everything.
115 bool supports_pull_constants
;
118 * Whether or not the driver supports NIR shader constants. This controls
119 * whether nir_opt_large_constants will be run.
121 bool supports_shader_constants
;
125 * We use a constant subgroup size of 32. It really only needs to be a
126 * maximum and, since we do SIMD32 for compute shaders in some cases, it
127 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
128 * subgroup size of 32 but will act as if 16 or 24 of those channels are
131 #define BRW_SUBGROUP_SIZE 32
134 * Program key structures.
136 * When drawing, we look for the currently bound shaders in the program
137 * cache. This is essentially a hash table lookup, and these are the keys.
139 * Sometimes OpenGL features specified as state need to be simulated via
140 * shader code, due to a mismatch between the API and the hardware. This
141 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
142 * in the program key so it's considered when searching for a program. If
143 * we haven't seen a particular combination before, we have to recompile a
144 * new specialized version.
146 * Shader compilation should not look up state in gl_context directly, but
147 * instead use the copy in the program key. This guarantees recompiles will
153 enum PACKED gen6_gather_sampler_wa
{
154 WA_SIGN
= 1, /* whether we need to sign extend */
155 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
156 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
160 * Sampler information needed by VS, WM, and GS program cache keys.
162 struct brw_sampler_prog_key_data
{
164 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
166 uint16_t swizzles
[MAX_SAMPLERS
];
168 uint32_t gl_clamp_mask
[3];
171 * For RG32F, gather4's channel select is broken.
173 uint32_t gather_channel_quirk_mask
;
176 * Whether this sampler uses the compressed multisample surface layout.
178 uint32_t compressed_multisample_layout_mask
;
181 * Whether this sampler is using 16x multisampling. If so fetching from
182 * this sampler will be handled with a different instruction, ld2dms_w
188 * For Sandybridge, which shader w/a we need for gather quirks.
190 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
193 * Texture units that have a YUV image bound.
195 uint32_t y_u_v_image_mask
;
196 uint32_t y_uv_image_mask
;
197 uint32_t yx_xuxv_image_mask
;
198 uint32_t xy_uxvx_image_mask
;
199 uint32_t ayuv_image_mask
;
200 uint32_t xyuv_image_mask
;
202 /* Scale factor for each texture. */
203 float scale_factors
[32];
206 /** An enum representing what kind of input gl_SubgroupSize is. */
207 enum PACKED brw_subgroup_size_type
209 BRW_SUBGROUP_SIZE_API_CONSTANT
, /**< Default Vulkan behavior */
210 BRW_SUBGROUP_SIZE_UNIFORM
, /**< OpenGL behavior */
211 BRW_SUBGROUP_SIZE_VARYING
, /**< VK_EXT_subgroup_size_control */
213 /* These enums are specifically chosen so that the value of the enum is
214 * also the subgroup size. If any new values are added, they must respect
217 BRW_SUBGROUP_SIZE_REQUIRE_8
= 8, /**< VK_EXT_subgroup_size_control */
218 BRW_SUBGROUP_SIZE_REQUIRE_16
= 16, /**< VK_EXT_subgroup_size_control */
219 BRW_SUBGROUP_SIZE_REQUIRE_32
= 32, /**< VK_EXT_subgroup_size_control */
222 struct brw_base_prog_key
{
223 unsigned program_string_id
;
225 enum brw_subgroup_size_type subgroup_size_type
;
227 struct brw_sampler_prog_key_data tex
;
231 * The VF can't natively handle certain types of attributes, such as GL_FIXED
232 * or most 10_10_10_2 types. These flags enable various VS workarounds to
233 * "fix" attributes at the beginning of shaders.
235 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
236 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
237 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
238 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
239 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
242 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
243 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
244 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
245 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
247 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
248 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
250 /** The program key for Vertex Shaders. */
251 struct brw_vs_prog_key
{
252 struct brw_base_prog_key base
;
255 * Per-attribute workaround flags
257 * For each attribute, a combination of BRW_ATTRIB_WA_*.
259 * For OpenGL, where we expose a maximum of 16 user input atttributes
260 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
261 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
262 * expose up to 28 user input vertex attributes that are mapped to slots
263 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
264 * enough to hold this many slots.
266 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
268 bool copy_edgeflag
:1;
270 bool clamp_vertex_color
:1;
273 * How many user clipping planes are being uploaded to the vertex shader as
276 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
279 unsigned nr_userclip_plane_consts
:4;
282 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
283 * are going to be replaced with point coordinates (as a consequence of a
284 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
285 * our SF thread requires exact matching between VS outputs and FS inputs,
286 * these texture coordinates will need to be unconditionally included in
287 * the VUE, even if they aren't written by the vertex shader.
289 uint8_t point_coord_replace
;
292 /** The program key for Tessellation Control Shaders. */
293 struct brw_tcs_prog_key
295 struct brw_base_prog_key base
;
297 GLenum tes_primitive_mode
;
299 unsigned input_vertices
;
301 /** A bitfield of per-patch outputs written. */
302 uint32_t patch_outputs_written
;
304 /** A bitfield of per-vertex outputs written. */
305 uint64_t outputs_written
;
307 bool quads_workaround
;
310 /** The program key for Tessellation Evaluation Shaders. */
311 struct brw_tes_prog_key
313 struct brw_base_prog_key base
;
315 /** A bitfield of per-patch inputs read. */
316 uint32_t patch_inputs_read
;
318 /** A bitfield of per-vertex inputs read. */
319 uint64_t inputs_read
;
322 /** The program key for Geometry Shaders. */
323 struct brw_gs_prog_key
325 struct brw_base_prog_key base
;
328 enum brw_sf_primitive
{
329 BRW_SF_PRIM_POINTS
= 0,
330 BRW_SF_PRIM_LINES
= 1,
331 BRW_SF_PRIM_TRIANGLES
= 2,
332 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
335 struct brw_sf_prog_key
{
337 bool contains_flat_varying
;
338 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
339 uint8_t point_sprite_coord_replace
;
340 enum brw_sf_primitive primitive
:2;
341 bool do_twoside_color
:1;
342 bool frontface_ccw
:1;
343 bool do_point_sprite
:1;
344 bool do_point_coord
:1;
345 bool sprite_origin_lower_left
:1;
346 bool userclip_active
:1;
350 BRW_CLIP_MODE_NORMAL
= 0,
351 BRW_CLIP_MODE_CLIP_ALL
= 1,
352 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
353 BRW_CLIP_MODE_REJECT_ALL
= 3,
354 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
355 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
358 enum brw_clip_fill_mode
{
359 BRW_CLIP_FILL_MODE_LINE
= 0,
360 BRW_CLIP_FILL_MODE_POINT
= 1,
361 BRW_CLIP_FILL_MODE_FILL
= 2,
362 BRW_CLIP_FILL_MODE_CULL
= 3,
365 /* Note that if unfilled primitives are being emitted, we have to fix
366 * up polygon offset and flatshading at this point:
368 struct brw_clip_prog_key
{
370 bool contains_flat_varying
;
371 bool contains_noperspective_varying
;
372 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
373 unsigned primitive
:4;
374 unsigned nr_userclip
:4;
377 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
378 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
383 enum brw_clip_mode clip_mode
:3;
390 /* A big lookup table is used to figure out which and how many
391 * additional regs will inserted before the main payload in the WM
392 * program execution. These mainly relate to depth and stencil
393 * processing and the early-depth-test optimization.
395 enum brw_wm_iz_bits
{
396 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
397 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
398 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
399 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
400 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
401 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
402 BRW_WM_IZ_BIT_MAX
= 0x40
405 enum brw_wm_aa_enable
{
411 /** The program key for Fragment/Pixel Shaders. */
412 struct brw_wm_prog_key
{
413 struct brw_base_prog_key base
;
415 /* Some collection of BRW_WM_IZ_* */
419 unsigned nr_color_regions
:5;
420 bool alpha_test_replicate_alpha
:1;
421 bool alpha_to_coverage
:1;
422 bool clamp_fragment_color
:1;
423 bool persample_interp
:1;
424 bool multisample_fbo
:1;
425 bool frag_coord_adds_sample_pos
:1;
426 enum brw_wm_aa_enable line_aa
:2;
427 bool high_quality_derivatives
:1;
428 bool force_dual_color_blend
:1;
429 bool coherent_fb_fetch
:1;
431 uint8_t color_outputs_valid
;
432 uint64_t input_slots_valid
;
433 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
434 float alpha_test_ref
;
437 struct brw_cs_prog_key
{
438 struct brw_base_prog_key base
;
441 /* brw_any_prog_key is any of the keys that map to an API stage */
442 union brw_any_prog_key
{
443 struct brw_base_prog_key base
;
444 struct brw_vs_prog_key vs
;
445 struct brw_tcs_prog_key tcs
;
446 struct brw_tes_prog_key tes
;
447 struct brw_gs_prog_key gs
;
448 struct brw_wm_prog_key wm
;
449 struct brw_cs_prog_key cs
;
453 * Image metadata structure as laid out in the shader parameter
454 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
455 * able to use them. That's okay because the padding and any unused
456 * entries [most of them except when we're doing untyped surface
457 * access] will be removed by the uniform packing pass.
459 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
460 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
461 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
462 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
463 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
464 #define BRW_IMAGE_PARAM_SIZE 20
466 struct brw_image_param
{
467 /** Offset applied to the X and Y surface coordinates. */
470 /** Surface X, Y and Z dimensions. */
473 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
474 * pixels, vertical slice stride in pixels.
478 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
482 * Right shift to apply for bit 6 address swizzling. Two different
483 * swizzles can be specified and will be applied one after the other. The
484 * resulting address will be:
486 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
487 * (addr >> swizzling[1])))
489 * Use \c 0xff if any of the swizzles is not required.
491 uint32_t swizzling
[2];
494 /** Max number of render targets in a shader */
495 #define BRW_MAX_DRAW_BUFFERS 8
498 * Max number of binding table entries used for stream output.
500 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
501 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
503 * On Gen6, the size of transform feedback data is limited not by the number
504 * of components but by the number of binding table entries we set aside. We
505 * use one binding table entry for a float, one entry for a vector, and one
506 * entry per matrix column. Since the only way we can communicate our
507 * transform feedback capabilities to the client is via
508 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
509 * worst case, in which all the varyings are floats, so we use up one binding
510 * table entry per component. Therefore we need to set aside at least 64
511 * binding table entries for use by transform feedback.
513 * Note: since we don't currently pack varyings, it is currently impossible
514 * for the client to actually use up all of these binding table entries--if
515 * all of their varyings were floats, they would run out of varying slots and
516 * fail to link. But that's a bug, so it seems prudent to go ahead and
517 * allocate the number of binding table entries we will need once the bug is
520 #define BRW_MAX_SOL_BINDINGS 64
523 * Binding table index for the first gen6 SOL binding.
525 #define BRW_GEN6_SOL_BINDING_START 0
528 * Stride in bytes between shader_time entries.
530 * We separate entries by a cacheline to reduce traffic between EUs writing to
533 #define BRW_SHADER_TIME_STRIDE 64
542 /* We reserve the first 2^16 values for builtins */
543 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
545 enum brw_param_builtin
{
546 BRW_PARAM_BUILTIN_ZERO
,
548 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
549 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
550 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
551 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
552 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
553 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
554 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
555 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
556 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
557 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
558 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
559 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
560 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
561 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
562 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
563 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
564 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
565 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
566 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
567 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
568 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
569 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
570 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
571 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
572 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
573 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
574 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
575 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
576 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
577 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
578 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
579 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
581 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
582 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
583 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
584 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
585 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
586 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
588 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
,
590 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
591 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
592 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
593 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
596 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
597 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
599 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
600 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
601 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
603 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
604 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
606 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
607 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
609 struct brw_stage_prog_data
{
611 /** size of our binding table. */
615 * surface indices for the various groups of surfaces
617 uint32_t pull_constants_start
;
618 uint32_t texture_start
;
619 uint32_t gather_texture_start
;
622 uint32_t image_start
;
623 uint32_t shader_time_start
;
624 uint32_t plane_start
[3];
628 struct brw_ubo_range ubo_ranges
[4];
630 GLuint nr_params
; /**< number of float params/constants */
631 GLuint nr_pull_params
;
633 unsigned curb_read_length
;
634 unsigned total_scratch
;
635 unsigned total_shared
;
637 unsigned program_size
;
640 * Register where the thread expects to find input data from the URB
641 * (typically uniforms, followed by vertex or fragment attributes).
643 unsigned dispatch_grf_start_reg
;
645 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
647 /* 32-bit identifiers for all push/pull parameters. These can be anything
648 * the driver wishes them to be; the core of the back-end compiler simply
649 * re-arranges them. The one restriction is that the bottom 2^16 values
650 * are reserved for builtins defined in the brw_param_builtin enum defined
654 uint32_t *pull_param
;
657 static inline uint32_t *
658 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
659 unsigned nr_new_params
)
661 unsigned old_nr_params
= prog_data
->nr_params
;
662 prog_data
->nr_params
+= nr_new_params
;
663 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
664 prog_data
->param
, uint32_t,
665 prog_data
->nr_params
);
666 return prog_data
->param
+ old_nr_params
;
669 enum brw_barycentric_mode
{
670 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
671 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
672 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
673 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
674 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
675 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
676 BRW_BARYCENTRIC_MODE_COUNT
= 6
678 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
679 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
680 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
681 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
683 enum brw_pixel_shader_computed_depth_mode
{
684 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
685 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
686 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
687 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
690 /* Data about a particular attempt to compile a program. Note that
691 * there can be many of these, each in a different GL state
692 * corresponding to a different brw_wm_prog_key struct, with different
695 struct brw_wm_prog_data
{
696 struct brw_stage_prog_data base
;
698 GLuint num_varying_inputs
;
700 uint8_t reg_blocks_8
;
701 uint8_t reg_blocks_16
;
702 uint8_t reg_blocks_32
;
704 uint8_t dispatch_grf_start_reg_16
;
705 uint8_t dispatch_grf_start_reg_32
;
706 uint32_t prog_offset_16
;
707 uint32_t prog_offset_32
;
711 * surface indices the WM-specific surfaces
713 uint32_t render_target_read_start
;
717 uint8_t computed_depth_mode
;
718 bool computed_stencil
;
720 bool early_fragment_tests
;
721 bool post_depth_coverage
;
727 bool replicate_alpha
;
728 bool persample_dispatch
;
729 bool uses_pos_offset
;
734 bool uses_sample_mask
;
735 bool has_render_target_reads
;
736 bool has_side_effects
;
739 bool contains_flat_varying
;
740 bool contains_noperspective_varying
;
743 * Mask of which interpolation modes are required by the fragment shader.
744 * Used in hardware setup on gen6+.
746 uint32_t barycentric_interp_modes
;
749 * Mask of which FS inputs are marked flat by the shader source. This is
750 * needed for setting up 3DSTATE_SF/SBE.
752 uint32_t flat_inputs
;
754 /* Mapping of VUE slots to interpolation modes.
755 * Used by the Gen4-5 clip/sf/wm stages.
757 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
760 * Map from gl_varying_slot to the position within the FS setup data
761 * payload where the varying's attribute vertex deltas should be delivered.
762 * For varying slots that are not used by the FS, the value is -1.
764 int urb_setup
[VARYING_SLOT_MAX
];
767 /** Returns the SIMD width corresponding to a given KSP index
769 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
770 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
771 * kernel start pointer (KSP) indices that is based on what dispatch widths
772 * are enabled. This function provides, effectively, the reverse mapping.
774 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
775 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
777 static inline unsigned
778 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
779 bool simd16_enabled
, bool simd32_enabled
)
781 /* This function strictly ignores contiguous dispatch */
784 return simd8_enabled
? 8 :
785 (simd16_enabled
&& !simd32_enabled
) ? 16 :
786 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
788 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
790 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
792 unreachable("Invalid KSP index");
796 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
797 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
798 (wm_state)._16PixelDispatchEnable, \
799 (wm_state)._32PixelDispatchEnable)
801 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
802 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
804 static inline uint32_t
805 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
808 switch (simd_width
) {
810 case 16: return prog_data
->prog_offset_16
;
811 case 32: return prog_data
->prog_offset_32
;
816 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
817 _brw_wm_prog_data_prog_offset(prog_data, \
818 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
820 static inline uint8_t
821 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
824 switch (simd_width
) {
825 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
826 case 16: return prog_data
->dispatch_grf_start_reg_16
;
827 case 32: return prog_data
->dispatch_grf_start_reg_32
;
832 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
833 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
834 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
836 static inline uint8_t
837 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
840 switch (simd_width
) {
841 case 8: return prog_data
->reg_blocks_8
;
842 case 16: return prog_data
->reg_blocks_16
;
843 case 32: return prog_data
->reg_blocks_32
;
848 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
849 _brw_wm_prog_data_reg_blocks(prog_data, \
850 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
852 struct brw_push_const_block
{
853 unsigned dwords
; /* Dword count, not reg aligned */
855 unsigned size
; /* Bytes, register aligned */
858 struct brw_cs_prog_data
{
859 struct brw_stage_prog_data base
;
861 unsigned local_size
[3];
865 bool uses_num_work_groups
;
868 struct brw_push_const_block cross_thread
;
869 struct brw_push_const_block per_thread
;
870 struct brw_push_const_block total
;
875 * surface indices the CS-specific surfaces
877 uint32_t work_groups_start
;
883 * Enum representing the i965-specific vertex results that don't correspond
884 * exactly to any element of gl_varying_slot. The values of this enum are
885 * assigned such that they don't conflict with gl_varying_slot.
889 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
890 BRW_VARYING_SLOT_PAD
,
892 * Technically this is not a varying but just a placeholder that
893 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
894 * builtin variable to be compiled correctly. see compile_sf_prog() for
897 BRW_VARYING_SLOT_PNTC
,
898 BRW_VARYING_SLOT_COUNT
902 * We always program SF to start reading at an offset of 1 (2 varying slots)
903 * from the start of the vertex URB entry. This causes it to skip:
904 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
905 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
907 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
910 * Bitmask indicating which fragment shader inputs represent varyings (and
911 * hence have to be delivered to the fragment shader by the SF/SBE stage).
913 #define BRW_FS_VARYING_INPUT_MASK \
914 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
915 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
918 * Data structure recording the relationship between the gl_varying_slot enum
919 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
920 * single octaword within the VUE (128 bits).
922 * Note that each BRW register contains 256 bits (2 octawords), so when
923 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
924 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
925 * in a vertex shader), each register corresponds to a single VUE slot, since
926 * it contains data for two separate vertices.
930 * Bitfield representing all varying slots that are (a) stored in this VUE
931 * map, and (b) actually written by the shader. Does not include any of
932 * the additional varying slots defined in brw_varying_slot.
934 uint64_t slots_valid
;
937 * Is this VUE map for a separate shader pipeline?
939 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
940 * without the linker having a chance to dead code eliminate unused varyings.
942 * This means that we have to use a fixed slot layout, based on the output's
943 * location field, rather than assigning slots in a compact contiguous block.
948 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
949 * not stored in a slot (because they are not written, or because
950 * additional processing is applied before storing them in the VUE), the
953 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
956 * Map from VUE slot to gl_varying_slot value. For slots that do not
957 * directly correspond to a gl_varying_slot, the value comes from
960 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
962 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
965 * Total number of VUE slots in use
970 * Number of per-patch VUE slots. Only valid for tessellation control
971 * shader outputs and tessellation evaluation shader inputs.
973 int num_per_patch_slots
;
976 * Number of per-vertex VUE slots. Only valid for tessellation control
977 * shader outputs and tessellation evaluation shader inputs.
979 int num_per_vertex_slots
;
982 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
985 * Convert a VUE slot number into a byte offset within the VUE.
987 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
993 * Convert a vertex output (brw_varying_slot) into a byte offset within the
997 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
999 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
1002 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
1003 struct brw_vue_map
*vue_map
,
1004 uint64_t slots_valid
,
1005 bool separate_shader
);
1007 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
1008 uint64_t slots_valid
,
1011 /* brw_interpolation_map.c */
1012 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
1013 struct nir_shader
*nir
,
1014 struct brw_wm_prog_data
*prog_data
);
1016 enum shader_dispatch_mode
{
1017 DISPATCH_MODE_4X1_SINGLE
= 0,
1018 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
1019 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
1020 DISPATCH_MODE_SIMD8
= 3,
1022 DISPATCH_MODE_TCS_SINGLE_PATCH
= 0,
1023 DISPATCH_MODE_TCS_8_PATCH
= 2,
1027 * @defgroup Tessellator parameter enumerations.
1029 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1030 * as part of the tessellation evaluation shader.
1034 enum brw_tess_partitioning
{
1035 BRW_TESS_PARTITIONING_INTEGER
= 0,
1036 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1037 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1040 enum brw_tess_output_topology
{
1041 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1042 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1043 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1044 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1047 enum brw_tess_domain
{
1048 BRW_TESS_DOMAIN_QUAD
= 0,
1049 BRW_TESS_DOMAIN_TRI
= 1,
1050 BRW_TESS_DOMAIN_ISOLINE
= 2,
1054 struct brw_vue_prog_data
{
1055 struct brw_stage_prog_data base
;
1056 struct brw_vue_map vue_map
;
1058 /** Should the hardware deliver input VUE handles for URB pull loads? */
1059 bool include_vue_handles
;
1061 GLuint urb_read_length
;
1064 uint32_t clip_distance_mask
;
1065 uint32_t cull_distance_mask
;
1067 /* Used for calculating urb partitions. In the VS, this is the size of the
1068 * URB entry used for both input and output to the thread. In the GS, this
1069 * is the size of the URB entry used for output.
1071 GLuint urb_entry_size
;
1073 enum shader_dispatch_mode dispatch_mode
;
1076 struct brw_vs_prog_data
{
1077 struct brw_vue_prog_data base
;
1079 GLbitfield64 inputs_read
;
1080 GLbitfield64 double_inputs_read
;
1082 unsigned nr_attribute_slots
;
1085 bool uses_instanceid
;
1086 bool uses_is_indexed_draw
;
1087 bool uses_firstvertex
;
1088 bool uses_baseinstance
;
1092 struct brw_tcs_prog_data
1094 struct brw_vue_prog_data base
;
1096 /** Should the non-SINGLE_PATCH payload provide primitive ID? */
1097 bool include_primitive_id
;
1099 /** Number vertices in output patch */
1104 struct brw_tes_prog_data
1106 struct brw_vue_prog_data base
;
1108 enum brw_tess_partitioning partitioning
;
1109 enum brw_tess_output_topology output_topology
;
1110 enum brw_tess_domain domain
;
1113 struct brw_gs_prog_data
1115 struct brw_vue_prog_data base
;
1117 unsigned vertices_in
;
1120 * Size of an output vertex, measured in HWORDS (32 bytes).
1122 unsigned output_vertex_size_hwords
;
1124 unsigned output_topology
;
1127 * Size of the control data (cut bits or StreamID bits), in hwords (32
1128 * bytes). 0 if there is no control data.
1130 unsigned control_data_header_size_hwords
;
1133 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1134 * if the control data is StreamID bits, or
1135 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1136 * Ignored if control_data_header_size is 0.
1138 unsigned control_data_format
;
1140 bool include_primitive_id
;
1143 * The number of vertices emitted, if constant - otherwise -1.
1145 int static_vertex_count
;
1150 * Gen6: Provoking vertex convention for odd-numbered triangles
1156 * Gen6: Number of varyings that are output to transform feedback.
1158 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1161 * Gen6: Map from the index of a transform feedback binding table entry to the
1162 * gl_varying_slot that should be streamed out through that binding table
1165 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1168 * Gen6: Map from the index of a transform feedback binding table entry to the
1169 * swizzles that should be used when streaming out data through that
1170 * binding table entry.
1172 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1175 struct brw_sf_prog_data
{
1176 uint32_t urb_read_length
;
1179 /* Each vertex may have upto 12 attributes, 4 components each,
1180 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1183 * Actually we use 4 for each, so call it 12 rows.
1185 unsigned urb_entry_size
;
1188 struct brw_clip_prog_data
{
1189 uint32_t curb_read_length
; /* user planes? */
1191 uint32_t urb_read_length
;
1195 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1196 union brw_any_prog_data
{
1197 struct brw_stage_prog_data base
;
1198 struct brw_vue_prog_data vue
;
1199 struct brw_vs_prog_data vs
;
1200 struct brw_tcs_prog_data tcs
;
1201 struct brw_tes_prog_data tes
;
1202 struct brw_gs_prog_data gs
;
1203 struct brw_wm_prog_data wm
;
1204 struct brw_cs_prog_data cs
;
1207 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1208 static inline struct brw_##stage##_prog_data * \
1209 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1211 return (struct brw_##stage##_prog_data *) prog_data; \
1213 DEFINE_PROG_DATA_DOWNCAST(vue
)
1214 DEFINE_PROG_DATA_DOWNCAST(vs
)
1215 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1216 DEFINE_PROG_DATA_DOWNCAST(tes
)
1217 DEFINE_PROG_DATA_DOWNCAST(gs
)
1218 DEFINE_PROG_DATA_DOWNCAST(wm
)
1219 DEFINE_PROG_DATA_DOWNCAST(cs
)
1220 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1221 DEFINE_PROG_DATA_DOWNCAST(clip
)
1222 DEFINE_PROG_DATA_DOWNCAST(sf
)
1223 #undef DEFINE_PROG_DATA_DOWNCAST
1227 struct brw_compiler
*
1228 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1231 * Returns a compiler configuration for use with disk shader cache
1233 * This value only needs to change for settings that can cause different
1234 * program generation between two runs on the same hardware.
1236 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1237 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1240 brw_get_compiler_config_value(const struct brw_compiler
*compiler
);
1243 brw_prog_data_size(gl_shader_stage stage
);
1246 brw_prog_key_size(gl_shader_stage stage
);
1249 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage
, unsigned id
);
1252 * Compile a vertex shader.
1254 * Returns the final assembly and the program's size.
1257 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1259 const struct brw_vs_prog_key
*key
,
1260 struct brw_vs_prog_data
*prog_data
,
1261 struct nir_shader
*shader
,
1262 int shader_time_index
,
1266 * Compile a tessellation control shader.
1268 * Returns the final assembly and the program's size.
1271 brw_compile_tcs(const struct brw_compiler
*compiler
,
1274 const struct brw_tcs_prog_key
*key
,
1275 struct brw_tcs_prog_data
*prog_data
,
1276 struct nir_shader
*nir
,
1277 int shader_time_index
,
1281 * Compile a tessellation evaluation shader.
1283 * Returns the final assembly and the program's size.
1286 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1288 const struct brw_tes_prog_key
*key
,
1289 const struct brw_vue_map
*input_vue_map
,
1290 struct brw_tes_prog_data
*prog_data
,
1291 struct nir_shader
*shader
,
1292 struct gl_program
*prog
,
1293 int shader_time_index
,
1297 * Compile a vertex shader.
1299 * Returns the final assembly and the program's size.
1302 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1304 const struct brw_gs_prog_key
*key
,
1305 struct brw_gs_prog_data
*prog_data
,
1306 struct nir_shader
*shader
,
1307 struct gl_program
*prog
,
1308 int shader_time_index
,
1312 * Compile a strips and fans shader.
1314 * This is a fixed-function shader determined entirely by the shader key and
1317 * Returns the final assembly and the program's size.
1320 brw_compile_sf(const struct brw_compiler
*compiler
,
1322 const struct brw_sf_prog_key
*key
,
1323 struct brw_sf_prog_data
*prog_data
,
1324 struct brw_vue_map
*vue_map
,
1325 unsigned *final_assembly_size
);
1328 * Compile a clipper shader.
1330 * This is a fixed-function shader determined entirely by the shader key and
1333 * Returns the final assembly and the program's size.
1336 brw_compile_clip(const struct brw_compiler
*compiler
,
1338 const struct brw_clip_prog_key
*key
,
1339 struct brw_clip_prog_data
*prog_data
,
1340 struct brw_vue_map
*vue_map
,
1341 unsigned *final_assembly_size
);
1344 * Compile a fragment shader.
1346 * Returns the final assembly and the program's size.
1349 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1351 const struct brw_wm_prog_key
*key
,
1352 struct brw_wm_prog_data
*prog_data
,
1353 struct nir_shader
*shader
,
1354 struct gl_program
*prog
,
1355 int shader_time_index8
,
1356 int shader_time_index16
,
1357 int shader_time_index32
,
1358 bool allow_spilling
,
1359 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1363 * Compile a compute shader.
1365 * Returns the final assembly and the program's size.
1368 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1370 const struct brw_cs_prog_key
*key
,
1371 struct brw_cs_prog_data
*prog_data
,
1372 const struct nir_shader
*shader
,
1373 int shader_time_index
,
1376 void brw_debug_key_recompile(const struct brw_compiler
*c
, void *log
,
1377 gl_shader_stage stage
,
1378 const struct brw_base_prog_key
*old_key
,
1379 const struct brw_base_prog_key
*key
);
1381 static inline uint32_t
1382 encode_slm_size(unsigned gen
, uint32_t bytes
)
1384 uint32_t slm_size
= 0;
1386 /* Shared Local Memory is specified as powers of two, and encoded in
1387 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1389 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1390 * -------------------------------------------------------------------
1391 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1392 * -------------------------------------------------------------------
1393 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1395 assert(bytes
<= 64 * 1024);
1398 /* Shared Local Memory Size is specified as powers of two. */
1399 slm_size
= util_next_power_of_two(bytes
);
1402 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1403 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1405 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1406 slm_size
= MAX2(slm_size
, 4096) / 4096;
1414 * Return true if the given shader stage is dispatched contiguously by the
1415 * relevant fixed function starting from channel 0 of the SIMD thread, which
1416 * implies that the dispatch mask of a thread can be assumed to have the form
1417 * '2^n - 1' for some n.
1420 brw_stage_has_packed_dispatch(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
1421 gl_shader_stage stage
,
1422 const struct brw_stage_prog_data
*prog_data
)
1424 /* The code below makes assumptions about the hardware's thread dispatch
1425 * behavior that could be proven wrong in future generations -- Make sure
1426 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1427 * the NIR front-end before changing this assertion.
1429 assert(devinfo
->gen
<= 11);
1432 case MESA_SHADER_FRAGMENT
: {
1433 /* The PSD discards subspans coming in with no lit samples, which in the
1434 * per-pixel shading case implies that each subspan will either be fully
1435 * lit (due to the VMask being used to allow derivative computations),
1436 * or not dispatched at all. In per-sample dispatch mode individual
1437 * samples from the same subspan have a fixed relative location within
1438 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1439 * general and we should return false.
1441 const struct brw_wm_prog_data
*wm_prog_data
=
1442 (const struct brw_wm_prog_data
*)prog_data
;
1443 return !wm_prog_data
->persample_dispatch
;
1445 case MESA_SHADER_COMPUTE
:
1446 /* Compute shaders will be spawned with either a fully enabled dispatch
1447 * mask or with whatever bottom/right execution mask was given to the
1448 * GPGPU walker command to be used along the workgroup edges -- In both
1449 * cases the dispatch mask is required to be tightly packed for our
1450 * invocation index calculations to work.
1454 /* Most remaining fixed functions are limited to use a packed dispatch
1455 * mask due to the hardware representation of the dispatch mask as a
1456 * single counter representing the number of enabled channels.
1463 * Computes the first varying slot in the URB produced by the previous stage
1464 * that is used in the next stage. We do this by testing the varying slots in
1465 * the previous stage's vue map against the inputs read in the next stage.
1469 * - Each URB offset contains two varying slots and we can only skip a
1470 * full offset if both slots are unused, so the value we return here is always
1471 * rounded down to the closest multiple of two.
1473 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1474 * part of the vue header, so if these are read we can't skip anything.
1477 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1478 const struct brw_vue_map
*prev_stage_vue_map
)
1480 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1481 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1482 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1483 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1484 return ROUND_DOWN_TO(i
, 2);
1495 #endif /* BRW_COMPILER_H */