2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
41 typedef struct nir_shader nir_shader
;
44 const struct gen_device_info
*devinfo
;
50 * Array of the ra classes for the unaligned contiguous register
56 * Mapping for register-allocated objects in *regs to the first
57 * GRF for that object.
59 uint8_t *ra_reg_to_grf
;
66 * Array of the ra classes for the unaligned contiguous register
67 * block sizes used, indexed by register size.
72 * Mapping from classes to ra_reg ranges. Each of the per-size
73 * classes corresponds to a range of ra_reg nodes. This array stores
74 * those ranges in the form of first ra_reg in each class and the
75 * total number of ra_reg elements in the last array element. This
76 * way the range of the i'th class is given by:
77 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
79 int class_to_ra_reg_range
[17];
82 * Mapping for register-allocated objects in *regs to the first
83 * GRF for that object.
85 uint8_t *ra_reg_to_grf
;
88 * ra class for the aligned barycentrics we use for PLN, which doesn't
91 int aligned_bary_class
;
94 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
97 bool scalar_stage
[MESA_ALL_SHADER_STAGES
];
99 struct gl_shader_compiler_options glsl_compiler_options
[MESA_ALL_SHADER_STAGES
];
102 * Apply workarounds for SIN and COS output range problems.
103 * This can negatively impact performance.
108 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
109 * Base Address? (If not, it's a normal GPU address.)
111 bool constant_buffer_0_is_relative
;
114 * Whether or not the driver supports pull constants. If not, the compiler
115 * will attempt to push everything.
117 bool supports_pull_constants
;
120 * Whether or not the driver supports NIR shader constants. This controls
121 * whether nir_opt_large_constants will be run.
123 bool supports_shader_constants
;
126 * Whether or not the driver wants uniform params to be compacted by the
132 * Whether or not the driver wants variable group size to be lowered by the
135 bool lower_variable_group_size
;
139 * We use a constant subgroup size of 32. It really only needs to be a
140 * maximum and, since we do SIMD32 for compute shaders in some cases, it
141 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
142 * subgroup size of 32 but will act as if 16 or 24 of those channels are
145 #define BRW_SUBGROUP_SIZE 32
148 * Program key structures.
150 * When drawing, we look for the currently bound shaders in the program
151 * cache. This is essentially a hash table lookup, and these are the keys.
153 * Sometimes OpenGL features specified as state need to be simulated via
154 * shader code, due to a mismatch between the API and the hardware. This
155 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
156 * in the program key so it's considered when searching for a program. If
157 * we haven't seen a particular combination before, we have to recompile a
158 * new specialized version.
160 * Shader compilation should not look up state in gl_context directly, but
161 * instead use the copy in the program key. This guarantees recompiles will
167 enum PACKED gen6_gather_sampler_wa
{
168 WA_SIGN
= 1, /* whether we need to sign extend */
169 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
170 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
174 * Sampler information needed by VS, WM, and GS program cache keys.
176 struct brw_sampler_prog_key_data
{
178 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
180 uint16_t swizzles
[MAX_SAMPLERS
];
182 uint32_t gl_clamp_mask
[3];
185 * For RG32F, gather4's channel select is broken.
187 uint32_t gather_channel_quirk_mask
;
190 * Whether this sampler uses the compressed multisample surface layout.
192 uint32_t compressed_multisample_layout_mask
;
195 * Whether this sampler is using 16x multisampling. If so fetching from
196 * this sampler will be handled with a different instruction, ld2dms_w
202 * For Sandybridge, which shader w/a we need for gather quirks.
204 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
207 * Texture units that have a YUV image bound.
209 uint32_t y_u_v_image_mask
;
210 uint32_t y_uv_image_mask
;
211 uint32_t yx_xuxv_image_mask
;
212 uint32_t xy_uxvx_image_mask
;
213 uint32_t ayuv_image_mask
;
214 uint32_t xyuv_image_mask
;
216 uint32_t bt2020_mask
;
218 /* Scale factor for each texture. */
219 float scale_factors
[32];
222 /** An enum representing what kind of input gl_SubgroupSize is. */
223 enum PACKED brw_subgroup_size_type
225 BRW_SUBGROUP_SIZE_API_CONSTANT
, /**< Default Vulkan behavior */
226 BRW_SUBGROUP_SIZE_UNIFORM
, /**< OpenGL behavior */
227 BRW_SUBGROUP_SIZE_VARYING
, /**< VK_EXT_subgroup_size_control */
229 /* These enums are specifically chosen so that the value of the enum is
230 * also the subgroup size. If any new values are added, they must respect
233 BRW_SUBGROUP_SIZE_REQUIRE_8
= 8, /**< VK_EXT_subgroup_size_control */
234 BRW_SUBGROUP_SIZE_REQUIRE_16
= 16, /**< VK_EXT_subgroup_size_control */
235 BRW_SUBGROUP_SIZE_REQUIRE_32
= 32, /**< VK_EXT_subgroup_size_control */
238 struct brw_base_prog_key
{
239 unsigned program_string_id
;
241 enum brw_subgroup_size_type subgroup_size_type
;
243 struct brw_sampler_prog_key_data tex
;
247 * The VF can't natively handle certain types of attributes, such as GL_FIXED
248 * or most 10_10_10_2 types. These flags enable various VS workarounds to
249 * "fix" attributes at the beginning of shaders.
251 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
252 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
253 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
254 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
255 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
258 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
259 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
260 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
261 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
263 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
264 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
266 /** The program key for Vertex Shaders. */
267 struct brw_vs_prog_key
{
268 struct brw_base_prog_key base
;
271 * Per-attribute workaround flags
273 * For each attribute, a combination of BRW_ATTRIB_WA_*.
275 * For OpenGL, where we expose a maximum of 16 user input atttributes
276 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
277 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
278 * expose up to 28 user input vertex attributes that are mapped to slots
279 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
280 * enough to hold this many slots.
282 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
284 bool copy_edgeflag
:1;
286 bool clamp_vertex_color
:1;
289 * How many user clipping planes are being uploaded to the vertex shader as
292 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
295 unsigned nr_userclip_plane_consts
:4;
298 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
299 * are going to be replaced with point coordinates (as a consequence of a
300 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
301 * our SF thread requires exact matching between VS outputs and FS inputs,
302 * these texture coordinates will need to be unconditionally included in
303 * the VUE, even if they aren't written by the vertex shader.
305 uint8_t point_coord_replace
;
308 /** The program key for Tessellation Control Shaders. */
309 struct brw_tcs_prog_key
311 struct brw_base_prog_key base
;
313 GLenum tes_primitive_mode
;
315 unsigned input_vertices
;
317 /** A bitfield of per-patch outputs written. */
318 uint32_t patch_outputs_written
;
320 /** A bitfield of per-vertex outputs written. */
321 uint64_t outputs_written
;
323 bool quads_workaround
;
326 /** The program key for Tessellation Evaluation Shaders. */
327 struct brw_tes_prog_key
329 struct brw_base_prog_key base
;
331 /** A bitfield of per-patch inputs read. */
332 uint32_t patch_inputs_read
;
334 /** A bitfield of per-vertex inputs read. */
335 uint64_t inputs_read
;
338 * How many user clipping planes are being uploaded to the tessellation
339 * evaluation shader as push constants.
341 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
344 unsigned nr_userclip_plane_consts
:4;
347 /** The program key for Geometry Shaders. */
348 struct brw_gs_prog_key
350 struct brw_base_prog_key base
;
353 * How many user clipping planes are being uploaded to the geometry shader
356 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
359 unsigned nr_userclip_plane_consts
:4;
362 enum brw_sf_primitive
{
363 BRW_SF_PRIM_POINTS
= 0,
364 BRW_SF_PRIM_LINES
= 1,
365 BRW_SF_PRIM_TRIANGLES
= 2,
366 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
369 struct brw_sf_prog_key
{
371 bool contains_flat_varying
;
372 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
373 uint8_t point_sprite_coord_replace
;
374 enum brw_sf_primitive primitive
:2;
375 bool do_twoside_color
:1;
376 bool frontface_ccw
:1;
377 bool do_point_sprite
:1;
378 bool do_point_coord
:1;
379 bool sprite_origin_lower_left
:1;
380 bool userclip_active
:1;
384 BRW_CLIP_MODE_NORMAL
= 0,
385 BRW_CLIP_MODE_CLIP_ALL
= 1,
386 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
387 BRW_CLIP_MODE_REJECT_ALL
= 3,
388 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
389 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
392 enum brw_clip_fill_mode
{
393 BRW_CLIP_FILL_MODE_LINE
= 0,
394 BRW_CLIP_FILL_MODE_POINT
= 1,
395 BRW_CLIP_FILL_MODE_FILL
= 2,
396 BRW_CLIP_FILL_MODE_CULL
= 3,
399 /* Note that if unfilled primitives are being emitted, we have to fix
400 * up polygon offset and flatshading at this point:
402 struct brw_clip_prog_key
{
404 bool contains_flat_varying
;
405 bool contains_noperspective_varying
;
406 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
407 unsigned primitive
:4;
408 unsigned nr_userclip
:4;
411 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
412 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
417 enum brw_clip_mode clip_mode
:3;
424 /* A big lookup table is used to figure out which and how many
425 * additional regs will inserted before the main payload in the WM
426 * program execution. These mainly relate to depth and stencil
427 * processing and the early-depth-test optimization.
429 enum brw_wm_iz_bits
{
430 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
431 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
432 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
433 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
434 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
435 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
436 BRW_WM_IZ_BIT_MAX
= 0x40
439 enum brw_wm_aa_enable
{
445 /** The program key for Fragment/Pixel Shaders. */
446 struct brw_wm_prog_key
{
447 struct brw_base_prog_key base
;
449 /* Some collection of BRW_WM_IZ_* */
453 unsigned nr_color_regions
:5;
454 bool alpha_test_replicate_alpha
:1;
455 bool alpha_to_coverage
:1;
456 bool clamp_fragment_color
:1;
457 bool persample_interp
:1;
458 bool multisample_fbo
:1;
459 bool frag_coord_adds_sample_pos
:1;
460 enum brw_wm_aa_enable line_aa
:2;
461 bool high_quality_derivatives
:1;
462 bool force_dual_color_blend
:1;
463 bool coherent_fb_fetch
:1;
464 bool ignore_sample_mask_out
:1;
466 uint8_t color_outputs_valid
;
467 uint64_t input_slots_valid
;
468 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
469 float alpha_test_ref
;
472 struct brw_cs_prog_key
{
473 struct brw_base_prog_key base
;
476 /* brw_any_prog_key is any of the keys that map to an API stage */
477 union brw_any_prog_key
{
478 struct brw_base_prog_key base
;
479 struct brw_vs_prog_key vs
;
480 struct brw_tcs_prog_key tcs
;
481 struct brw_tes_prog_key tes
;
482 struct brw_gs_prog_key gs
;
483 struct brw_wm_prog_key wm
;
484 struct brw_cs_prog_key cs
;
488 * Image metadata structure as laid out in the shader parameter
489 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
490 * able to use them. That's okay because the padding and any unused
491 * entries [most of them except when we're doing untyped surface
492 * access] will be removed by the uniform packing pass.
494 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
495 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
496 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
497 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
498 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
499 #define BRW_IMAGE_PARAM_SIZE 20
501 struct brw_image_param
{
502 /** Offset applied to the X and Y surface coordinates. */
505 /** Surface X, Y and Z dimensions. */
508 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
509 * pixels, vertical slice stride in pixels.
513 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
517 * Right shift to apply for bit 6 address swizzling. Two different
518 * swizzles can be specified and will be applied one after the other. The
519 * resulting address will be:
521 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
522 * (addr >> swizzling[1])))
524 * Use \c 0xff if any of the swizzles is not required.
526 uint32_t swizzling
[2];
529 /** Max number of render targets in a shader */
530 #define BRW_MAX_DRAW_BUFFERS 8
533 * Max number of binding table entries used for stream output.
535 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
536 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
538 * On Gen6, the size of transform feedback data is limited not by the number
539 * of components but by the number of binding table entries we set aside. We
540 * use one binding table entry for a float, one entry for a vector, and one
541 * entry per matrix column. Since the only way we can communicate our
542 * transform feedback capabilities to the client is via
543 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
544 * worst case, in which all the varyings are floats, so we use up one binding
545 * table entry per component. Therefore we need to set aside at least 64
546 * binding table entries for use by transform feedback.
548 * Note: since we don't currently pack varyings, it is currently impossible
549 * for the client to actually use up all of these binding table entries--if
550 * all of their varyings were floats, they would run out of varying slots and
551 * fail to link. But that's a bug, so it seems prudent to go ahead and
552 * allocate the number of binding table entries we will need once the bug is
555 #define BRW_MAX_SOL_BINDINGS 64
558 * Binding table index for the first gen6 SOL binding.
560 #define BRW_GEN6_SOL_BINDING_START 0
563 * Stride in bytes between shader_time entries.
565 * We separate entries by a cacheline to reduce traffic between EUs writing to
568 #define BRW_SHADER_TIME_STRIDE 64
577 /* We reserve the first 2^16 values for builtins */
578 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
580 enum brw_param_builtin
{
581 BRW_PARAM_BUILTIN_ZERO
,
583 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
584 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
585 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
586 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
587 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
588 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
589 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
590 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
591 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
592 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
593 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
594 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
595 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
596 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
597 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
598 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
599 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
600 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
601 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
602 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
603 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
604 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
605 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
606 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
607 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
608 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
609 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
610 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
611 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
612 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
613 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
614 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
616 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
617 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
618 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
619 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
620 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
621 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
623 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
,
625 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
626 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
627 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
628 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
629 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
,
630 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Y
,
631 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z
,
634 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
635 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
637 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
638 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
639 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
641 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
642 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
644 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
645 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
647 /** Represents a code relocation
649 * Relocatable constants are immediates in the code which we want to be able
650 * to replace post-compile with the actual value.
652 struct brw_shader_reloc
{
653 /** The 32-bit ID of the relocatable constant */
656 /** The offset in the shader to the relocatable instruction
658 * This is the offset to the instruction rather than the immediate value
659 * itself. This allows us to do some sanity checking while we relocate.
664 /** A value to write to a relocation */
665 struct brw_shader_reloc_value
{
666 /** The 32-bit ID of the relocatable constant */
669 /** The value with which to replace the relocated immediate */
673 struct brw_stage_prog_data
{
675 /** size of our binding table. */
679 * surface indices for the various groups of surfaces
681 uint32_t pull_constants_start
;
682 uint32_t texture_start
;
683 uint32_t gather_texture_start
;
686 uint32_t image_start
;
687 uint32_t shader_time_start
;
688 uint32_t plane_start
[3];
692 struct brw_ubo_range ubo_ranges
[4];
694 GLuint nr_params
; /**< number of float params/constants */
695 GLuint nr_pull_params
;
697 /* zero_push_reg is a bitfield which indicates what push registers (if any)
698 * should be zeroed by SW at the start of the shader. The corresponding
699 * push_reg_mask_param specifies the param index (in 32-bit units) where
700 * the actual runtime 64-bit mask will be pushed. The shader will zero
703 * reg_used & zero_push_reg & ~*push_reg_mask_param & (1ull << i)
705 * If this field is set, brw_compiler::compact_params must be false.
707 uint64_t zero_push_reg
;
708 unsigned push_reg_mask_param
;
710 unsigned curb_read_length
;
711 unsigned total_scratch
;
712 unsigned total_shared
;
714 unsigned program_size
;
716 unsigned const_data_size
;
717 unsigned const_data_offset
;
720 const struct brw_shader_reloc
*relocs
;
722 /** Does this program pull from any UBO or other constant buffers? */
726 * Register where the thread expects to find input data from the URB
727 * (typically uniforms, followed by vertex or fragment attributes).
729 unsigned dispatch_grf_start_reg
;
731 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
733 /* 32-bit identifiers for all push/pull parameters. These can be anything
734 * the driver wishes them to be; the core of the back-end compiler simply
735 * re-arranges them. The one restriction is that the bottom 2^16 values
736 * are reserved for builtins defined in the brw_param_builtin enum defined
740 uint32_t *pull_param
;
742 /* Whether shader uses atomic operations. */
743 bool uses_atomic_load_store
;
746 static inline uint32_t *
747 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
748 unsigned nr_new_params
)
750 unsigned old_nr_params
= prog_data
->nr_params
;
751 prog_data
->nr_params
+= nr_new_params
;
752 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
753 prog_data
->param
, uint32_t,
754 prog_data
->nr_params
);
755 return prog_data
->param
+ old_nr_params
;
758 enum brw_barycentric_mode
{
759 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
760 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
761 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
762 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
763 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
764 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
765 BRW_BARYCENTRIC_MODE_COUNT
= 6
767 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
768 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
769 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
770 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
772 enum brw_pixel_shader_computed_depth_mode
{
773 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
774 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
775 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
776 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
779 /* Data about a particular attempt to compile a program. Note that
780 * there can be many of these, each in a different GL state
781 * corresponding to a different brw_wm_prog_key struct, with different
784 struct brw_wm_prog_data
{
785 struct brw_stage_prog_data base
;
787 GLuint num_varying_inputs
;
789 uint8_t reg_blocks_8
;
790 uint8_t reg_blocks_16
;
791 uint8_t reg_blocks_32
;
793 uint8_t dispatch_grf_start_reg_16
;
794 uint8_t dispatch_grf_start_reg_32
;
795 uint32_t prog_offset_16
;
796 uint32_t prog_offset_32
;
800 * surface indices the WM-specific surfaces
802 uint32_t render_target_read_start
;
806 uint8_t computed_depth_mode
;
807 bool computed_stencil
;
809 bool early_fragment_tests
;
810 bool post_depth_coverage
;
816 bool persample_dispatch
;
817 bool uses_pos_offset
;
822 bool uses_sample_mask
;
823 bool has_render_target_reads
;
824 bool has_side_effects
;
827 bool contains_flat_varying
;
828 bool contains_noperspective_varying
;
831 * Mask of which interpolation modes are required by the fragment shader.
832 * Used in hardware setup on gen6+.
834 uint32_t barycentric_interp_modes
;
837 * Mask of which FS inputs are marked flat by the shader source. This is
838 * needed for setting up 3DSTATE_SF/SBE.
840 uint32_t flat_inputs
;
847 /* Mapping of VUE slots to interpolation modes.
848 * Used by the Gen4-5 clip/sf/wm stages.
850 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
853 * Map from gl_varying_slot to the position within the FS setup data
854 * payload where the varying's attribute vertex deltas should be delivered.
855 * For varying slots that are not used by the FS, the value is -1.
857 int urb_setup
[VARYING_SLOT_MAX
];
860 * Cache structure into the urb_setup array above that contains the
861 * attribute numbers of active varyings out of urb_setup.
862 * The actual count is stored in urb_setup_attribs_count.
864 uint8_t urb_setup_attribs
[VARYING_SLOT_MAX
];
865 uint8_t urb_setup_attribs_count
;
868 /** Returns the SIMD width corresponding to a given KSP index
870 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
871 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
872 * kernel start pointer (KSP) indices that is based on what dispatch widths
873 * are enabled. This function provides, effectively, the reverse mapping.
875 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
876 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
878 static inline unsigned
879 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
880 bool simd16_enabled
, bool simd32_enabled
)
882 /* This function strictly ignores contiguous dispatch */
885 return simd8_enabled
? 8 :
886 (simd16_enabled
&& !simd32_enabled
) ? 16 :
887 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
889 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
891 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
893 unreachable("Invalid KSP index");
897 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
898 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
899 (wm_state)._16PixelDispatchEnable, \
900 (wm_state)._32PixelDispatchEnable)
902 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
903 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
905 static inline uint32_t
906 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
909 switch (simd_width
) {
911 case 16: return prog_data
->prog_offset_16
;
912 case 32: return prog_data
->prog_offset_32
;
917 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
918 _brw_wm_prog_data_prog_offset(prog_data, \
919 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
921 static inline uint8_t
922 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
925 switch (simd_width
) {
926 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
927 case 16: return prog_data
->dispatch_grf_start_reg_16
;
928 case 32: return prog_data
->dispatch_grf_start_reg_32
;
933 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
934 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
935 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
937 static inline uint8_t
938 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
941 switch (simd_width
) {
942 case 8: return prog_data
->reg_blocks_8
;
943 case 16: return prog_data
->reg_blocks_16
;
944 case 32: return prog_data
->reg_blocks_32
;
949 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
950 _brw_wm_prog_data_reg_blocks(prog_data, \
951 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
953 struct brw_push_const_block
{
954 unsigned dwords
; /* Dword count, not reg aligned */
956 unsigned size
; /* Bytes, register aligned */
959 struct brw_cs_prog_data
{
960 struct brw_stage_prog_data base
;
962 unsigned local_size
[3];
965 /* Program offsets for the 8/16/32 SIMD variants. Multiple variants are
966 * kept when using variable group size, and the right one can only be
967 * decided at dispatch time.
969 unsigned prog_offset
[3];
971 /* Bitmask indicating which program offsets are valid. */
974 /* Bitmask indicating which programs have spilled. */
975 unsigned prog_spilled
;
978 bool uses_num_work_groups
;
981 struct brw_push_const_block cross_thread
;
982 struct brw_push_const_block per_thread
;
987 * surface indices the CS-specific surfaces
989 uint32_t work_groups_start
;
994 static inline uint32_t
995 brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data
*prog_data
,
996 unsigned dispatch_width
)
998 assert(dispatch_width
== 8 ||
999 dispatch_width
== 16 ||
1000 dispatch_width
== 32);
1001 const unsigned index
= dispatch_width
/ 16;
1002 assert(prog_data
->prog_mask
& (1 << index
));
1003 return prog_data
->prog_offset
[index
];
1007 * Enum representing the i965-specific vertex results that don't correspond
1008 * exactly to any element of gl_varying_slot. The values of this enum are
1009 * assigned such that they don't conflict with gl_varying_slot.
1013 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
1014 BRW_VARYING_SLOT_PAD
,
1016 * Technically this is not a varying but just a placeholder that
1017 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
1018 * builtin variable to be compiled correctly. see compile_sf_prog() for
1021 BRW_VARYING_SLOT_PNTC
,
1022 BRW_VARYING_SLOT_COUNT
1026 * We always program SF to start reading at an offset of 1 (2 varying slots)
1027 * from the start of the vertex URB entry. This causes it to skip:
1028 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1029 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
1031 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
1034 * Bitmask indicating which fragment shader inputs represent varyings (and
1035 * hence have to be delivered to the fragment shader by the SF/SBE stage).
1037 #define BRW_FS_VARYING_INPUT_MASK \
1038 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
1039 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
1042 * Data structure recording the relationship between the gl_varying_slot enum
1043 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
1044 * single octaword within the VUE (128 bits).
1046 * Note that each BRW register contains 256 bits (2 octawords), so when
1047 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
1048 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
1049 * in a vertex shader), each register corresponds to a single VUE slot, since
1050 * it contains data for two separate vertices.
1052 struct brw_vue_map
{
1054 * Bitfield representing all varying slots that are (a) stored in this VUE
1055 * map, and (b) actually written by the shader. Does not include any of
1056 * the additional varying slots defined in brw_varying_slot.
1058 uint64_t slots_valid
;
1061 * Is this VUE map for a separate shader pipeline?
1063 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
1064 * without the linker having a chance to dead code eliminate unused varyings.
1066 * This means that we have to use a fixed slot layout, based on the output's
1067 * location field, rather than assigning slots in a compact contiguous block.
1072 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
1073 * not stored in a slot (because they are not written, or because
1074 * additional processing is applied before storing them in the VUE), the
1077 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
1080 * Map from VUE slot to gl_varying_slot value. For slots that do not
1081 * directly correspond to a gl_varying_slot, the value comes from
1084 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
1086 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
1089 * Total number of VUE slots in use
1094 * Number of per-patch VUE slots. Only valid for tessellation control
1095 * shader outputs and tessellation evaluation shader inputs.
1097 int num_per_patch_slots
;
1100 * Number of per-vertex VUE slots. Only valid for tessellation control
1101 * shader outputs and tessellation evaluation shader inputs.
1103 int num_per_vertex_slots
;
1106 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
1109 * Convert a VUE slot number into a byte offset within the VUE.
1111 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
1117 * Convert a vertex output (brw_varying_slot) into a byte offset within the
1121 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
1123 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
1126 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
1127 struct brw_vue_map
*vue_map
,
1128 uint64_t slots_valid
,
1129 bool separate_shader
,
1130 uint32_t pos_slots
);
1132 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
1133 uint64_t slots_valid
,
1136 /* brw_interpolation_map.c */
1137 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
1138 struct nir_shader
*nir
,
1139 struct brw_wm_prog_data
*prog_data
);
1141 enum shader_dispatch_mode
{
1142 DISPATCH_MODE_4X1_SINGLE
= 0,
1143 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
1144 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
1145 DISPATCH_MODE_SIMD8
= 3,
1147 DISPATCH_MODE_TCS_SINGLE_PATCH
= 0,
1148 DISPATCH_MODE_TCS_8_PATCH
= 2,
1152 * @defgroup Tessellator parameter enumerations.
1154 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1155 * as part of the tessellation evaluation shader.
1159 enum brw_tess_partitioning
{
1160 BRW_TESS_PARTITIONING_INTEGER
= 0,
1161 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1162 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1165 enum brw_tess_output_topology
{
1166 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1167 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1168 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1169 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1172 enum brw_tess_domain
{
1173 BRW_TESS_DOMAIN_QUAD
= 0,
1174 BRW_TESS_DOMAIN_TRI
= 1,
1175 BRW_TESS_DOMAIN_ISOLINE
= 2,
1179 struct brw_vue_prog_data
{
1180 struct brw_stage_prog_data base
;
1181 struct brw_vue_map vue_map
;
1183 /** Should the hardware deliver input VUE handles for URB pull loads? */
1184 bool include_vue_handles
;
1186 GLuint urb_read_length
;
1189 uint32_t clip_distance_mask
;
1190 uint32_t cull_distance_mask
;
1192 /* Used for calculating urb partitions. In the VS, this is the size of the
1193 * URB entry used for both input and output to the thread. In the GS, this
1194 * is the size of the URB entry used for output.
1196 GLuint urb_entry_size
;
1198 enum shader_dispatch_mode dispatch_mode
;
1201 struct brw_vs_prog_data
{
1202 struct brw_vue_prog_data base
;
1204 GLbitfield64 inputs_read
;
1205 GLbitfield64 double_inputs_read
;
1207 unsigned nr_attribute_slots
;
1210 bool uses_instanceid
;
1211 bool uses_is_indexed_draw
;
1212 bool uses_firstvertex
;
1213 bool uses_baseinstance
;
1217 struct brw_tcs_prog_data
1219 struct brw_vue_prog_data base
;
1221 /** Should the non-SINGLE_PATCH payload provide primitive ID? */
1222 bool include_primitive_id
;
1224 /** Number vertices in output patch */
1227 /** Track patch count threshold */
1228 int patch_count_threshold
;
1232 struct brw_tes_prog_data
1234 struct brw_vue_prog_data base
;
1236 enum brw_tess_partitioning partitioning
;
1237 enum brw_tess_output_topology output_topology
;
1238 enum brw_tess_domain domain
;
1241 struct brw_gs_prog_data
1243 struct brw_vue_prog_data base
;
1245 unsigned vertices_in
;
1248 * Size of an output vertex, measured in HWORDS (32 bytes).
1250 unsigned output_vertex_size_hwords
;
1252 unsigned output_topology
;
1255 * Size of the control data (cut bits or StreamID bits), in hwords (32
1256 * bytes). 0 if there is no control data.
1258 unsigned control_data_header_size_hwords
;
1261 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1262 * if the control data is StreamID bits, or
1263 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1264 * Ignored if control_data_header_size is 0.
1266 unsigned control_data_format
;
1268 bool include_primitive_id
;
1271 * The number of vertices emitted, if constant - otherwise -1.
1273 int static_vertex_count
;
1278 * Gen6: Provoking vertex convention for odd-numbered triangles
1284 * Gen6: Number of varyings that are output to transform feedback.
1286 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1289 * Gen6: Map from the index of a transform feedback binding table entry to the
1290 * gl_varying_slot that should be streamed out through that binding table
1293 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1296 * Gen6: Map from the index of a transform feedback binding table entry to the
1297 * swizzles that should be used when streaming out data through that
1298 * binding table entry.
1300 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1303 struct brw_sf_prog_data
{
1304 uint32_t urb_read_length
;
1307 /* Each vertex may have upto 12 attributes, 4 components each,
1308 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1311 * Actually we use 4 for each, so call it 12 rows.
1313 unsigned urb_entry_size
;
1316 struct brw_clip_prog_data
{
1317 uint32_t curb_read_length
; /* user planes? */
1319 uint32_t urb_read_length
;
1323 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1324 union brw_any_prog_data
{
1325 struct brw_stage_prog_data base
;
1326 struct brw_vue_prog_data vue
;
1327 struct brw_vs_prog_data vs
;
1328 struct brw_tcs_prog_data tcs
;
1329 struct brw_tes_prog_data tes
;
1330 struct brw_gs_prog_data gs
;
1331 struct brw_wm_prog_data wm
;
1332 struct brw_cs_prog_data cs
;
1335 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1336 static inline struct brw_##stage##_prog_data * \
1337 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1339 return (struct brw_##stage##_prog_data *) prog_data; \
1341 static inline const struct brw_##stage##_prog_data * \
1342 brw_##stage##_prog_data_const(const struct brw_stage_prog_data *prog_data) \
1344 return (const struct brw_##stage##_prog_data *) prog_data; \
1346 DEFINE_PROG_DATA_DOWNCAST(vue
)
1347 DEFINE_PROG_DATA_DOWNCAST(vs
)
1348 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1349 DEFINE_PROG_DATA_DOWNCAST(tes
)
1350 DEFINE_PROG_DATA_DOWNCAST(gs
)
1351 DEFINE_PROG_DATA_DOWNCAST(wm
)
1352 DEFINE_PROG_DATA_DOWNCAST(cs
)
1353 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1354 DEFINE_PROG_DATA_DOWNCAST(clip
)
1355 DEFINE_PROG_DATA_DOWNCAST(sf
)
1356 #undef DEFINE_PROG_DATA_DOWNCAST
1358 struct brw_compile_stats
{
1359 uint32_t dispatch_width
; /**< 0 for vec4 */
1360 uint32_t instructions
;
1370 struct brw_compiler
*
1371 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1374 * Returns a compiler configuration for use with disk shader cache
1376 * This value only needs to change for settings that can cause different
1377 * program generation between two runs on the same hardware.
1379 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1380 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1383 brw_get_compiler_config_value(const struct brw_compiler
*compiler
);
1386 brw_prog_data_size(gl_shader_stage stage
);
1389 brw_prog_key_size(gl_shader_stage stage
);
1392 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage
, unsigned id
);
1395 * Compile a vertex shader.
1397 * Returns the final assembly and the program's size.
1400 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1402 const struct brw_vs_prog_key
*key
,
1403 struct brw_vs_prog_data
*prog_data
,
1405 int shader_time_index
,
1406 struct brw_compile_stats
*stats
,
1410 * Compile a tessellation control shader.
1412 * Returns the final assembly and the program's size.
1415 brw_compile_tcs(const struct brw_compiler
*compiler
,
1418 const struct brw_tcs_prog_key
*key
,
1419 struct brw_tcs_prog_data
*prog_data
,
1421 int shader_time_index
,
1422 struct brw_compile_stats
*stats
,
1426 * Compile a tessellation evaluation shader.
1428 * Returns the final assembly and the program's size.
1431 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1433 const struct brw_tes_prog_key
*key
,
1434 const struct brw_vue_map
*input_vue_map
,
1435 struct brw_tes_prog_data
*prog_data
,
1437 int shader_time_index
,
1438 struct brw_compile_stats
*stats
,
1442 * Compile a vertex shader.
1444 * Returns the final assembly and the program's size.
1447 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1449 const struct brw_gs_prog_key
*key
,
1450 struct brw_gs_prog_data
*prog_data
,
1452 struct gl_program
*prog
,
1453 int shader_time_index
,
1454 struct brw_compile_stats
*stats
,
1458 * Compile a strips and fans shader.
1460 * This is a fixed-function shader determined entirely by the shader key and
1463 * Returns the final assembly and the program's size.
1466 brw_compile_sf(const struct brw_compiler
*compiler
,
1468 const struct brw_sf_prog_key
*key
,
1469 struct brw_sf_prog_data
*prog_data
,
1470 struct brw_vue_map
*vue_map
,
1471 unsigned *final_assembly_size
);
1474 * Compile a clipper shader.
1476 * This is a fixed-function shader determined entirely by the shader key and
1479 * Returns the final assembly and the program's size.
1482 brw_compile_clip(const struct brw_compiler
*compiler
,
1484 const struct brw_clip_prog_key
*key
,
1485 struct brw_clip_prog_data
*prog_data
,
1486 struct brw_vue_map
*vue_map
,
1487 unsigned *final_assembly_size
);
1490 * Compile a fragment shader.
1492 * Returns the final assembly and the program's size.
1495 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1497 const struct brw_wm_prog_key
*key
,
1498 struct brw_wm_prog_data
*prog_data
,
1500 int shader_time_index8
,
1501 int shader_time_index16
,
1502 int shader_time_index32
,
1503 bool allow_spilling
,
1504 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1505 struct brw_compile_stats
*stats
, /**< Array of three stats */
1509 * Compile a compute shader.
1511 * Returns the final assembly and the program's size.
1514 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1516 const struct brw_cs_prog_key
*key
,
1517 struct brw_cs_prog_data
*prog_data
,
1518 const nir_shader
*nir
,
1519 int shader_time_index
,
1520 struct brw_compile_stats
*stats
,
1523 void brw_debug_key_recompile(const struct brw_compiler
*c
, void *log
,
1524 gl_shader_stage stage
,
1525 const struct brw_base_prog_key
*old_key
,
1526 const struct brw_base_prog_key
*key
);
1528 static inline uint32_t
1529 encode_slm_size(unsigned gen
, uint32_t bytes
)
1531 uint32_t slm_size
= 0;
1533 /* Shared Local Memory is specified as powers of two, and encoded in
1534 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1536 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1537 * -------------------------------------------------------------------
1538 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1539 * -------------------------------------------------------------------
1540 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1542 assert(bytes
<= 64 * 1024);
1545 /* Shared Local Memory Size is specified as powers of two. */
1546 slm_size
= util_next_power_of_two(bytes
);
1549 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1550 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1552 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1553 slm_size
= MAX2(slm_size
, 4096) / 4096;
1561 brw_cs_push_const_total_size(const struct brw_cs_prog_data
*cs_prog_data
,
1565 brw_cs_simd_size_for_group_size(const struct gen_device_info
*devinfo
,
1566 const struct brw_cs_prog_data
*cs_prog_data
,
1567 unsigned group_size
);
1570 brw_write_shader_relocs(const struct gen_device_info
*devinfo
,
1572 const struct brw_stage_prog_data
*prog_data
,
1573 struct brw_shader_reloc_value
*values
,
1574 unsigned num_values
);
1577 * Calculate the RightExecutionMask field used in GPGPU_WALKER.
1579 static inline unsigned
1580 brw_cs_right_mask(unsigned group_size
, unsigned simd_size
)
1582 const uint32_t remainder
= group_size
& (simd_size
- 1);
1584 return ~0u >> (32 - remainder
);
1586 return ~0u >> (32 - simd_size
);
1590 * Return true if the given shader stage is dispatched contiguously by the
1591 * relevant fixed function starting from channel 0 of the SIMD thread, which
1592 * implies that the dispatch mask of a thread can be assumed to have the form
1593 * '2^n - 1' for some n.
1596 brw_stage_has_packed_dispatch(ASSERTED
const struct gen_device_info
*devinfo
,
1597 gl_shader_stage stage
,
1598 const struct brw_stage_prog_data
*prog_data
)
1600 /* The code below makes assumptions about the hardware's thread dispatch
1601 * behavior that could be proven wrong in future generations -- Make sure
1602 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1603 * the NIR front-end before changing this assertion.
1605 assert(devinfo
->gen
<= 12);
1608 case MESA_SHADER_FRAGMENT
: {
1609 /* The PSD discards subspans coming in with no lit samples, which in the
1610 * per-pixel shading case implies that each subspan will either be fully
1611 * lit (due to the VMask being used to allow derivative computations),
1612 * or not dispatched at all. In per-sample dispatch mode individual
1613 * samples from the same subspan have a fixed relative location within
1614 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1615 * general and we should return false.
1617 const struct brw_wm_prog_data
*wm_prog_data
=
1618 (const struct brw_wm_prog_data
*)prog_data
;
1619 return !wm_prog_data
->persample_dispatch
;
1621 case MESA_SHADER_COMPUTE
:
1622 /* Compute shaders will be spawned with either a fully enabled dispatch
1623 * mask or with whatever bottom/right execution mask was given to the
1624 * GPGPU walker command to be used along the workgroup edges -- In both
1625 * cases the dispatch mask is required to be tightly packed for our
1626 * invocation index calculations to work.
1630 /* Most remaining fixed functions are limited to use a packed dispatch
1631 * mask due to the hardware representation of the dispatch mask as a
1632 * single counter representing the number of enabled channels.
1639 * Computes the first varying slot in the URB produced by the previous stage
1640 * that is used in the next stage. We do this by testing the varying slots in
1641 * the previous stage's vue map against the inputs read in the next stage.
1645 * - Each URB offset contains two varying slots and we can only skip a
1646 * full offset if both slots are unused, so the value we return here is always
1647 * rounded down to the closest multiple of two.
1649 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1650 * part of the vue header, so if these are read we can't skip anything.
1653 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1654 const struct brw_vue_map
*prev_stage_vue_map
)
1656 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1657 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1658 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1659 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1660 return ROUND_DOWN_TO(i
, 2);
1671 #endif /* BRW_COMPILER_H */