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[mesa.git] / src / intel / compiler / brw_eu.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_EU_H
34 #define BRW_EU_H
35
36 #include <stdbool.h>
37 #include <stdio.h>
38 #include "brw_inst.h"
39 #include "brw_eu_defines.h"
40 #include "brw_reg.h"
41 #include "brw_disasm_info.h"
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 #define BRW_EU_MAX_INSN_STACK 5
48
49 struct brw_insn_state {
50 /* One of BRW_EXECUTE_* */
51 unsigned exec_size:3;
52
53 /* Group in units of channels */
54 unsigned group:5;
55
56 /* Compression control on gen4-5 */
57 bool compressed:1;
58
59 /* One of BRW_MASK_* */
60 unsigned mask_control:1;
61
62 /* Scheduling info for Gen12+ */
63 struct tgl_swsb swsb;
64
65 bool saturate:1;
66
67 /* One of BRW_ALIGN_* */
68 unsigned access_mode:1;
69
70 /* One of BRW_PREDICATE_* */
71 enum brw_predicate predicate:4;
72
73 bool pred_inv:1;
74
75 /* Flag subreg. Bottom bit is subreg, top bit is reg */
76 unsigned flag_subreg:2;
77
78 bool acc_wr_control:1;
79 };
80
81
82 /* A helper for accessing the last instruction emitted. This makes it easy
83 * to set various bits on an instruction without having to create temporary
84 * variable and assign the emitted instruction to those.
85 */
86 #define brw_last_inst (&p->store[p->nr_insn - 1])
87
88 struct brw_codegen {
89 brw_inst *store;
90 int store_size;
91 unsigned nr_insn;
92 unsigned int next_insn_offset;
93
94 void *mem_ctx;
95
96 /* Allow clients to push/pop instruction state:
97 */
98 struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK];
99 struct brw_insn_state *current;
100
101 /** Whether or not the user wants automatic exec sizes
102 *
103 * If true, codegen will try to automatically infer the exec size of an
104 * instruction from the width of the destination register. If false, it
105 * will take whatever is set by brw_set_default_exec_size verbatim.
106 *
107 * This is set to true by default in brw_init_codegen.
108 */
109 bool automatic_exec_sizes;
110
111 bool single_program_flow;
112 const struct gen_device_info *devinfo;
113
114 /* Control flow stacks:
115 * - if_stack contains IF and ELSE instructions which must be patched
116 * (and popped) once the matching ENDIF instruction is encountered.
117 *
118 * Just store the instruction pointer(an index).
119 */
120 int *if_stack;
121 int if_stack_depth;
122 int if_stack_array_size;
123
124 /**
125 * loop_stack contains the instruction pointers of the starts of loops which
126 * must be patched (and popped) once the matching WHILE instruction is
127 * encountered.
128 */
129 int *loop_stack;
130 /**
131 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
132 * blocks they were popping out of, to fix up the mask stack. This tracks
133 * the IF/ENDIF nesting in each current nested loop level.
134 */
135 int *if_depth_in_loop;
136 int loop_stack_depth;
137 int loop_stack_array_size;
138 };
139
140 void brw_pop_insn_state( struct brw_codegen *p );
141 void brw_push_insn_state( struct brw_codegen *p );
142 unsigned brw_get_default_exec_size(struct brw_codegen *p);
143 unsigned brw_get_default_group(struct brw_codegen *p);
144 unsigned brw_get_default_access_mode(struct brw_codegen *p);
145 struct tgl_swsb brw_get_default_swsb(struct brw_codegen *p);
146 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
147 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
148 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
149 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
150 void brw_inst_set_compression(const struct gen_device_info *devinfo,
151 brw_inst *inst, bool on);
152 void brw_set_default_compression(struct brw_codegen *p, bool on);
153 void brw_inst_set_group(const struct gen_device_info *devinfo,
154 brw_inst *inst, unsigned group);
155 void brw_set_default_group(struct brw_codegen *p, unsigned group);
156 void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
157 void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc);
158 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
159 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
160 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
161 void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
162
163 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
164 void *mem_ctx);
165 bool brw_has_jip(const struct gen_device_info *devinfo, enum opcode opcode);
166 bool brw_has_uip(const struct gen_device_info *devinfo, enum opcode opcode);
167 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
168 const struct brw_inst *inst, bool is_compacted);
169 void brw_disassemble(const struct gen_device_info *devinfo,
170 const void *assembly, int start, int end, FILE *out);
171 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
172
173 bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
174 const char *identifier);
175
176 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
177 void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest);
178 void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
179
180 void gen6_resolve_implied_move(struct brw_codegen *p,
181 struct brw_reg *src,
182 unsigned msg_reg_nr);
183
184 /* Helpers for regular instructions:
185 */
186 #define ALU1(OP) \
187 brw_inst *brw_##OP(struct brw_codegen *p, \
188 struct brw_reg dest, \
189 struct brw_reg src0);
190
191 #define ALU2(OP) \
192 brw_inst *brw_##OP(struct brw_codegen *p, \
193 struct brw_reg dest, \
194 struct brw_reg src0, \
195 struct brw_reg src1);
196
197 #define ALU3(OP) \
198 brw_inst *brw_##OP(struct brw_codegen *p, \
199 struct brw_reg dest, \
200 struct brw_reg src0, \
201 struct brw_reg src1, \
202 struct brw_reg src2);
203
204 ALU1(MOV)
205 ALU2(SEL)
206 ALU1(NOT)
207 ALU2(AND)
208 ALU2(OR)
209 ALU2(XOR)
210 ALU2(SHR)
211 ALU2(SHL)
212 ALU1(DIM)
213 ALU2(ASR)
214 ALU2(ROL)
215 ALU2(ROR)
216 ALU3(CSEL)
217 ALU1(F32TO16)
218 ALU1(F16TO32)
219 ALU2(ADD)
220 ALU2(AVG)
221 ALU2(MUL)
222 ALU1(FRC)
223 ALU1(RNDD)
224 ALU1(RNDE)
225 ALU1(RNDU)
226 ALU1(RNDZ)
227 ALU2(MAC)
228 ALU2(MACH)
229 ALU1(LZD)
230 ALU2(DP4)
231 ALU2(DPH)
232 ALU2(DP3)
233 ALU2(DP2)
234 ALU2(LINE)
235 ALU2(PLN)
236 ALU3(MAD)
237 ALU3(LRP)
238 ALU1(BFREV)
239 ALU3(BFE)
240 ALU2(BFI1)
241 ALU3(BFI2)
242 ALU1(FBH)
243 ALU1(FBL)
244 ALU1(CBIT)
245 ALU2(ADDC)
246 ALU2(SUBB)
247 ALU2(MAC)
248
249 #undef ALU1
250 #undef ALU2
251 #undef ALU3
252
253
254 /* Helpers for SEND instruction:
255 */
256
257 /**
258 * Construct a message descriptor immediate with the specified common
259 * descriptor controls.
260 */
261 static inline uint32_t
262 brw_message_desc(const struct gen_device_info *devinfo,
263 unsigned msg_length,
264 unsigned response_length,
265 bool header_present)
266 {
267 if (devinfo->gen >= 5) {
268 return (SET_BITS(msg_length, 28, 25) |
269 SET_BITS(response_length, 24, 20) |
270 SET_BITS(header_present, 19, 19));
271 } else {
272 return (SET_BITS(msg_length, 23, 20) |
273 SET_BITS(response_length, 19, 16));
274 }
275 }
276
277 static inline unsigned
278 brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
279 {
280 if (devinfo->gen >= 5)
281 return GET_BITS(desc, 28, 25);
282 else
283 return GET_BITS(desc, 23, 20);
284 }
285
286 static inline unsigned
287 brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
288 {
289 if (devinfo->gen >= 5)
290 return GET_BITS(desc, 24, 20);
291 else
292 return GET_BITS(desc, 19, 16);
293 }
294
295 static inline bool
296 brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
297 uint32_t desc)
298 {
299 assert(devinfo->gen >= 5);
300 return GET_BITS(desc, 19, 19);
301 }
302
303 static inline unsigned
304 brw_message_ex_desc(UNUSED const struct gen_device_info *devinfo,
305 unsigned ex_msg_length)
306 {
307 return SET_BITS(ex_msg_length, 9, 6);
308 }
309
310 static inline unsigned
311 brw_message_ex_desc_ex_mlen(UNUSED const struct gen_device_info *devinfo,
312 uint32_t ex_desc)
313 {
314 return GET_BITS(ex_desc, 9, 6);
315 }
316
317 static inline uint32_t
318 brw_urb_desc(const struct gen_device_info *devinfo,
319 unsigned msg_type,
320 bool per_slot_offset_present,
321 bool channel_mask_present,
322 unsigned global_offset)
323 {
324 if (devinfo->gen >= 8) {
325 return (SET_BITS(per_slot_offset_present, 17, 17) |
326 SET_BITS(channel_mask_present, 15, 15) |
327 SET_BITS(global_offset, 14, 4) |
328 SET_BITS(msg_type, 3, 0));
329 } else if (devinfo->gen >= 7) {
330 assert(!channel_mask_present);
331 return (SET_BITS(per_slot_offset_present, 16, 16) |
332 SET_BITS(global_offset, 13, 3) |
333 SET_BITS(msg_type, 3, 0));
334 } else {
335 unreachable("unhandled URB write generation");
336 }
337 }
338
339 static inline uint32_t
340 brw_urb_desc_msg_type(ASSERTED const struct gen_device_info *devinfo,
341 uint32_t desc)
342 {
343 assert(devinfo->gen >= 7);
344 return GET_BITS(desc, 3, 0);
345 }
346
347 /**
348 * Construct a message descriptor immediate with the specified sampler
349 * function controls.
350 */
351 static inline uint32_t
352 brw_sampler_desc(const struct gen_device_info *devinfo,
353 unsigned binding_table_index,
354 unsigned sampler,
355 unsigned msg_type,
356 unsigned simd_mode,
357 unsigned return_format)
358 {
359 const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
360 SET_BITS(sampler, 11, 8));
361 if (devinfo->gen >= 7)
362 return (desc | SET_BITS(msg_type, 16, 12) |
363 SET_BITS(simd_mode, 18, 17));
364 else if (devinfo->gen >= 5)
365 return (desc | SET_BITS(msg_type, 15, 12) |
366 SET_BITS(simd_mode, 17, 16));
367 else if (devinfo->is_g4x)
368 return desc | SET_BITS(msg_type, 15, 12);
369 else
370 return (desc | SET_BITS(return_format, 13, 12) |
371 SET_BITS(msg_type, 15, 14));
372 }
373
374 static inline unsigned
375 brw_sampler_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
376 uint32_t desc)
377 {
378 return GET_BITS(desc, 7, 0);
379 }
380
381 static inline unsigned
382 brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t desc)
383 {
384 return GET_BITS(desc, 11, 8);
385 }
386
387 static inline unsigned
388 brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
389 {
390 if (devinfo->gen >= 7)
391 return GET_BITS(desc, 16, 12);
392 else if (devinfo->gen >= 5 || devinfo->is_g4x)
393 return GET_BITS(desc, 15, 12);
394 else
395 return GET_BITS(desc, 15, 14);
396 }
397
398 static inline unsigned
399 brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
400 {
401 assert(devinfo->gen >= 5);
402 if (devinfo->gen >= 7)
403 return GET_BITS(desc, 18, 17);
404 else
405 return GET_BITS(desc, 17, 16);
406 }
407
408 static inline unsigned
409 brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
410 uint32_t desc)
411 {
412 assert(devinfo->gen == 4 && !devinfo->is_g4x);
413 return GET_BITS(desc, 13, 12);
414 }
415
416 /**
417 * Construct a message descriptor for the dataport
418 */
419 static inline uint32_t
420 brw_dp_desc(const struct gen_device_info *devinfo,
421 unsigned binding_table_index,
422 unsigned msg_type,
423 unsigned msg_control)
424 {
425 /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
426 * helpers instead.
427 */
428 assert(devinfo->gen >= 6);
429 const unsigned desc = SET_BITS(binding_table_index, 7, 0);
430 if (devinfo->gen >= 8) {
431 return (desc | SET_BITS(msg_control, 13, 8) |
432 SET_BITS(msg_type, 18, 14));
433 } else if (devinfo->gen >= 7) {
434 return (desc | SET_BITS(msg_control, 13, 8) |
435 SET_BITS(msg_type, 17, 14));
436 } else {
437 return (desc | SET_BITS(msg_control, 12, 8) |
438 SET_BITS(msg_type, 16, 13));
439 }
440 }
441
442 static inline unsigned
443 brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
444 uint32_t desc)
445 {
446 return GET_BITS(desc, 7, 0);
447 }
448
449 static inline unsigned
450 brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
451 {
452 assert(devinfo->gen >= 6);
453 if (devinfo->gen >= 8)
454 return GET_BITS(desc, 18, 14);
455 else if (devinfo->gen >= 7)
456 return GET_BITS(desc, 17, 14);
457 else
458 return GET_BITS(desc, 16, 13);
459 }
460
461 static inline unsigned
462 brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
463 {
464 assert(devinfo->gen >= 6);
465 if (devinfo->gen >= 7)
466 return GET_BITS(desc, 13, 8);
467 else
468 return GET_BITS(desc, 12, 8);
469 }
470
471 /**
472 * Construct a message descriptor immediate with the specified dataport read
473 * function controls.
474 */
475 static inline uint32_t
476 brw_dp_read_desc(const struct gen_device_info *devinfo,
477 unsigned binding_table_index,
478 unsigned msg_control,
479 unsigned msg_type,
480 unsigned target_cache)
481 {
482 if (devinfo->gen >= 6)
483 return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
484 else if (devinfo->gen >= 5 || devinfo->is_g4x)
485 return (SET_BITS(binding_table_index, 7, 0) |
486 SET_BITS(msg_control, 10, 8) |
487 SET_BITS(msg_type, 13, 11) |
488 SET_BITS(target_cache, 15, 14));
489 else
490 return (SET_BITS(binding_table_index, 7, 0) |
491 SET_BITS(msg_control, 11, 8) |
492 SET_BITS(msg_type, 13, 12) |
493 SET_BITS(target_cache, 15, 14));
494 }
495
496 static inline unsigned
497 brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
498 {
499 if (devinfo->gen >= 6)
500 return brw_dp_desc_msg_type(devinfo, desc);
501 else if (devinfo->gen >= 5 || devinfo->is_g4x)
502 return GET_BITS(desc, 13, 11);
503 else
504 return GET_BITS(desc, 13, 12);
505 }
506
507 static inline unsigned
508 brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
509 uint32_t desc)
510 {
511 if (devinfo->gen >= 6)
512 return brw_dp_desc_msg_control(devinfo, desc);
513 else if (devinfo->gen >= 5 || devinfo->is_g4x)
514 return GET_BITS(desc, 10, 8);
515 else
516 return GET_BITS(desc, 11, 8);
517 }
518
519 /**
520 * Construct a message descriptor immediate with the specified dataport write
521 * function controls.
522 */
523 static inline uint32_t
524 brw_dp_write_desc(const struct gen_device_info *devinfo,
525 unsigned binding_table_index,
526 unsigned msg_control,
527 unsigned msg_type,
528 unsigned last_render_target,
529 unsigned send_commit_msg)
530 {
531 assert(devinfo->gen <= 6 || !send_commit_msg);
532 if (devinfo->gen >= 6)
533 return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) |
534 SET_BITS(last_render_target, 12, 12) |
535 SET_BITS(send_commit_msg, 17, 17);
536 else
537 return (SET_BITS(binding_table_index, 7, 0) |
538 SET_BITS(msg_control, 11, 8) |
539 SET_BITS(last_render_target, 11, 11) |
540 SET_BITS(msg_type, 14, 12) |
541 SET_BITS(send_commit_msg, 15, 15));
542 }
543
544 static inline unsigned
545 brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
546 uint32_t desc)
547 {
548 if (devinfo->gen >= 6)
549 return brw_dp_desc_msg_type(devinfo, desc);
550 else
551 return GET_BITS(desc, 14, 12);
552 }
553
554 static inline unsigned
555 brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
556 uint32_t desc)
557 {
558 if (devinfo->gen >= 6)
559 return brw_dp_desc_msg_control(devinfo, desc);
560 else
561 return GET_BITS(desc, 11, 8);
562 }
563
564 static inline bool
565 brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
566 uint32_t desc)
567 {
568 if (devinfo->gen >= 6)
569 return GET_BITS(desc, 12, 12);
570 else
571 return GET_BITS(desc, 11, 11);
572 }
573
574 static inline bool
575 brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
576 uint32_t desc)
577 {
578 assert(devinfo->gen <= 6);
579 if (devinfo->gen >= 6)
580 return GET_BITS(desc, 17, 17);
581 else
582 return GET_BITS(desc, 15, 15);
583 }
584
585 /**
586 * Construct a message descriptor immediate with the specified dataport
587 * surface function controls.
588 */
589 static inline uint32_t
590 brw_dp_surface_desc(const struct gen_device_info *devinfo,
591 unsigned msg_type,
592 unsigned msg_control)
593 {
594 assert(devinfo->gen >= 7);
595 /* We'll OR in the binding table index later */
596 return brw_dp_desc(devinfo, 0, msg_type, msg_control);
597 }
598
599 static inline uint32_t
600 brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
601 unsigned exec_size, /**< 0 for SIMD4x2 */
602 unsigned atomic_op,
603 bool response_expected)
604 {
605 assert(exec_size <= 8 || exec_size == 16);
606
607 unsigned msg_type;
608 if (devinfo->gen >= 8 || devinfo->is_haswell) {
609 if (exec_size > 0) {
610 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
611 } else {
612 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
613 }
614 } else {
615 msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
616 }
617
618 const unsigned msg_control =
619 SET_BITS(atomic_op, 3, 0) |
620 SET_BITS(0 < exec_size && exec_size <= 8, 4, 4) |
621 SET_BITS(response_expected, 5, 5);
622
623 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
624 }
625
626 static inline uint32_t
627 brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
628 unsigned exec_size,
629 unsigned atomic_op,
630 bool response_expected)
631 {
632 assert(exec_size <= 8 || exec_size == 16);
633 assert(devinfo->gen >= 9);
634
635 assert(exec_size > 0);
636 const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
637
638 const unsigned msg_control =
639 SET_BITS(atomic_op, 1, 0) |
640 SET_BITS(exec_size <= 8, 4, 4) |
641 SET_BITS(response_expected, 5, 5);
642
643 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
644 }
645
646 static inline unsigned
647 brw_mdc_cmask(unsigned num_channels)
648 {
649 /* See also MDC_CMASK in the SKL PRM Vol 2d. */
650 return 0xf & (0xf << num_channels);
651 }
652
653 static inline uint32_t
654 brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
655 unsigned exec_size, /**< 0 for SIMD4x2 */
656 unsigned num_channels,
657 bool write)
658 {
659 assert(exec_size <= 8 || exec_size == 16);
660
661 unsigned msg_type;
662 if (write) {
663 if (devinfo->gen >= 8 || devinfo->is_haswell) {
664 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
665 } else {
666 msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
667 }
668 } else {
669 /* Read */
670 if (devinfo->gen >= 8 || devinfo->is_haswell) {
671 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
672 } else {
673 msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
674 }
675 }
676
677 /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
678 if (write && devinfo->gen == 7 && !devinfo->is_haswell && exec_size == 0)
679 exec_size = 8;
680
681 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
682 const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
683 exec_size <= 8 ? 2 : 1;
684
685 const unsigned msg_control =
686 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
687 SET_BITS(simd_mode, 5, 4);
688
689 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
690 }
691
692 static inline unsigned
693 brw_mdc_ds(unsigned bit_size)
694 {
695 switch (bit_size) {
696 case 8:
697 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
698 case 16:
699 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
700 case 32:
701 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
702 default:
703 unreachable("Unsupported bit_size for byte scattered messages");
704 }
705 }
706
707 static inline uint32_t
708 brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
709 unsigned exec_size,
710 unsigned bit_size,
711 bool write)
712 {
713 assert(exec_size <= 8 || exec_size == 16);
714
715 assert(devinfo->gen > 7 || devinfo->is_haswell);
716 const unsigned msg_type =
717 write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
718 HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
719
720 assert(exec_size > 0);
721 const unsigned msg_control =
722 SET_BITS(exec_size == 16, 0, 0) |
723 SET_BITS(brw_mdc_ds(bit_size), 3, 2);
724
725 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
726 }
727
728 static inline uint32_t
729 brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
730 unsigned exec_size,
731 bool write)
732 {
733 assert(exec_size == 8 || exec_size == 16);
734
735 unsigned msg_type;
736 if (write) {
737 if (devinfo->gen >= 6) {
738 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
739 } else {
740 msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
741 }
742 } else {
743 if (devinfo->gen >= 7) {
744 msg_type = GEN7_DATAPORT_DC_DWORD_SCATTERED_READ;
745 } else if (devinfo->gen > 4 || devinfo->is_g4x) {
746 msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
747 } else {
748 msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
749 }
750 }
751
752 const unsigned msg_control =
753 SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */
754 SET_BITS(exec_size == 16, 0, 0);
755
756 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
757 }
758
759 static inline uint32_t
760 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
761 unsigned exec_size, /**< 0 for SIMD4x2 */
762 unsigned num_channels,
763 bool write)
764 {
765 assert(exec_size <= 8 || exec_size == 16);
766 assert(devinfo->gen >= 8);
767
768 unsigned msg_type =
769 write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
770 GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
771
772 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
773 const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
774 exec_size <= 8 ? 2 : 1;
775
776 const unsigned msg_control =
777 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
778 SET_BITS(simd_mode, 5, 4);
779
780 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
781 msg_type, msg_control);
782 }
783
784 /**
785 * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
786 * Skylake PRM).
787 */
788 static inline uint32_t
789 brw_mdc_a64_ds(unsigned elems)
790 {
791 switch (elems) {
792 case 1: return 0;
793 case 2: return 1;
794 case 4: return 2;
795 case 8: return 3;
796 default:
797 unreachable("Unsupported elmeent count for A64 scattered message");
798 }
799 }
800
801 static inline uint32_t
802 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
803 unsigned exec_size, /**< 0 for SIMD4x2 */
804 unsigned bit_size,
805 bool write)
806 {
807 assert(exec_size <= 8 || exec_size == 16);
808 assert(devinfo->gen >= 8);
809
810 unsigned msg_type =
811 write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
812 GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
813
814 const unsigned msg_control =
815 SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
816 SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) |
817 SET_BITS(exec_size == 16, 4, 4);
818
819 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
820 msg_type, msg_control);
821 }
822
823 static inline uint32_t
824 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
825 ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */
826 unsigned bit_size,
827 unsigned atomic_op,
828 bool response_expected)
829 {
830 assert(exec_size == 8);
831 assert(devinfo->gen >= 8);
832 assert(bit_size == 32 || bit_size == 64);
833
834 const unsigned msg_type = GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
835
836 const unsigned msg_control =
837 SET_BITS(atomic_op, 3, 0) |
838 SET_BITS(bit_size == 64, 4, 4) |
839 SET_BITS(response_expected, 5, 5);
840
841 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
842 msg_type, msg_control);
843 }
844
845 static inline uint32_t
846 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
847 ASSERTED unsigned exec_size,
848 unsigned atomic_op,
849 bool response_expected)
850 {
851 assert(exec_size == 8);
852 assert(devinfo->gen >= 9);
853
854 assert(exec_size > 0);
855 const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP;
856
857 const unsigned msg_control =
858 SET_BITS(atomic_op, 1, 0) |
859 SET_BITS(response_expected, 5, 5);
860
861 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
862 msg_type, msg_control);
863 }
864
865 static inline uint32_t
866 brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
867 unsigned exec_size,
868 unsigned exec_group,
869 unsigned atomic_op,
870 bool response_expected)
871 {
872 assert(exec_size > 0 || exec_group == 0);
873 assert(exec_group % 8 == 0);
874
875 unsigned msg_type;
876 if (devinfo->gen >= 8 || devinfo->is_haswell) {
877 if (exec_size == 0) {
878 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
879 } else {
880 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
881 }
882 } else {
883 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
884 assert(exec_size > 0);
885 msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
886 }
887
888 const bool high_sample_mask = (exec_group / 8) % 2 == 1;
889
890 const unsigned msg_control =
891 SET_BITS(atomic_op, 3, 0) |
892 SET_BITS(high_sample_mask, 4, 4) |
893 SET_BITS(response_expected, 5, 5);
894
895 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
896 }
897
898 static inline uint32_t
899 brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
900 unsigned exec_size,
901 unsigned exec_group,
902 unsigned num_channels,
903 bool write)
904 {
905 assert(exec_size > 0 || exec_group == 0);
906 assert(exec_group % 8 == 0);
907
908 /* Typed surface reads and writes don't support SIMD16 */
909 assert(exec_size <= 8);
910
911 unsigned msg_type;
912 if (write) {
913 if (devinfo->gen >= 8 || devinfo->is_haswell) {
914 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
915 } else {
916 msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
917 }
918 } else {
919 if (devinfo->gen >= 8 || devinfo->is_haswell) {
920 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
921 } else {
922 msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
923 }
924 }
925
926 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
927 unsigned msg_control;
928 if (devinfo->gen >= 8 || devinfo->is_haswell) {
929 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
930 const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
931 1 + ((exec_group / 8) % 2);
932
933 msg_control =
934 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
935 SET_BITS(slot_group, 5, 4);
936 } else {
937 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
938 assert(exec_size > 0);
939 const unsigned slot_group = ((exec_group / 8) % 2);
940
941 msg_control =
942 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
943 SET_BITS(slot_group, 5, 5);
944 }
945
946 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
947 }
948
949 /**
950 * Construct a message descriptor immediate with the specified pixel
951 * interpolator function controls.
952 */
953 static inline uint32_t
954 brw_pixel_interp_desc(UNUSED const struct gen_device_info *devinfo,
955 unsigned msg_type,
956 bool noperspective,
957 unsigned simd_mode,
958 unsigned slot_group)
959 {
960 return (SET_BITS(slot_group, 11, 11) |
961 SET_BITS(msg_type, 13, 12) |
962 SET_BITS(!!noperspective, 14, 14) |
963 SET_BITS(simd_mode, 16, 16));
964 }
965
966 void brw_urb_WRITE(struct brw_codegen *p,
967 struct brw_reg dest,
968 unsigned msg_reg_nr,
969 struct brw_reg src0,
970 enum brw_urb_write_flags flags,
971 unsigned msg_length,
972 unsigned response_length,
973 unsigned offset,
974 unsigned swizzle);
975
976 /**
977 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
978 * desc. If \p desc is not an immediate it will be transparently loaded to an
979 * address register using an OR instruction.
980 */
981 void
982 brw_send_indirect_message(struct brw_codegen *p,
983 unsigned sfid,
984 struct brw_reg dst,
985 struct brw_reg payload,
986 struct brw_reg desc,
987 unsigned desc_imm,
988 bool eot);
989
990 void
991 brw_send_indirect_split_message(struct brw_codegen *p,
992 unsigned sfid,
993 struct brw_reg dst,
994 struct brw_reg payload0,
995 struct brw_reg payload1,
996 struct brw_reg desc,
997 unsigned desc_imm,
998 struct brw_reg ex_desc,
999 unsigned ex_desc_imm,
1000 bool eot);
1001
1002 void brw_ff_sync(struct brw_codegen *p,
1003 struct brw_reg dest,
1004 unsigned msg_reg_nr,
1005 struct brw_reg src0,
1006 bool allocate,
1007 unsigned response_length,
1008 bool eot);
1009
1010 void brw_svb_write(struct brw_codegen *p,
1011 struct brw_reg dest,
1012 unsigned msg_reg_nr,
1013 struct brw_reg src0,
1014 unsigned binding_table_index,
1015 bool send_commit_msg);
1016
1017 brw_inst *brw_fb_WRITE(struct brw_codegen *p,
1018 struct brw_reg payload,
1019 struct brw_reg implied_header,
1020 unsigned msg_control,
1021 unsigned binding_table_index,
1022 unsigned msg_length,
1023 unsigned response_length,
1024 bool eot,
1025 bool last_render_target,
1026 bool header_present);
1027
1028 brw_inst *gen9_fb_READ(struct brw_codegen *p,
1029 struct brw_reg dst,
1030 struct brw_reg payload,
1031 unsigned binding_table_index,
1032 unsigned msg_length,
1033 unsigned response_length,
1034 bool per_sample);
1035
1036 void brw_SAMPLE(struct brw_codegen *p,
1037 struct brw_reg dest,
1038 unsigned msg_reg_nr,
1039 struct brw_reg src0,
1040 unsigned binding_table_index,
1041 unsigned sampler,
1042 unsigned msg_type,
1043 unsigned response_length,
1044 unsigned msg_length,
1045 unsigned header_present,
1046 unsigned simd_mode,
1047 unsigned return_format);
1048
1049 void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
1050 struct brw_reg header,
1051 struct brw_reg sampler_index);
1052
1053 void gen4_math(struct brw_codegen *p,
1054 struct brw_reg dest,
1055 unsigned function,
1056 unsigned msg_reg_nr,
1057 struct brw_reg src,
1058 unsigned precision );
1059
1060 void gen6_math(struct brw_codegen *p,
1061 struct brw_reg dest,
1062 unsigned function,
1063 struct brw_reg src0,
1064 struct brw_reg src1);
1065
1066 void brw_oword_block_read(struct brw_codegen *p,
1067 struct brw_reg dest,
1068 struct brw_reg mrf,
1069 uint32_t offset,
1070 uint32_t bind_table_index);
1071
1072 unsigned brw_scratch_surface_idx(const struct brw_codegen *p);
1073
1074 void brw_oword_block_read_scratch(struct brw_codegen *p,
1075 struct brw_reg dest,
1076 struct brw_reg mrf,
1077 int num_regs,
1078 unsigned offset);
1079
1080 void brw_oword_block_write_scratch(struct brw_codegen *p,
1081 struct brw_reg mrf,
1082 int num_regs,
1083 unsigned offset);
1084
1085 void gen7_block_read_scratch(struct brw_codegen *p,
1086 struct brw_reg dest,
1087 int num_regs,
1088 unsigned offset);
1089
1090 void brw_shader_time_add(struct brw_codegen *p,
1091 struct brw_reg payload,
1092 uint32_t surf_index);
1093
1094 /**
1095 * Return the generation-specific jump distance scaling factor.
1096 *
1097 * Given the number of instructions to jump, we need to scale by
1098 * some number to obtain the actual jump distance to program in an
1099 * instruction.
1100 */
1101 static inline unsigned
1102 brw_jump_scale(const struct gen_device_info *devinfo)
1103 {
1104 /* Broadwell measures jump targets in bytes. */
1105 if (devinfo->gen >= 8)
1106 return 16;
1107
1108 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1109 * (to support compaction), so each 128-bit instruction requires 2 chunks.
1110 */
1111 if (devinfo->gen >= 5)
1112 return 2;
1113
1114 /* Gen4 simply uses the number of 128-bit instructions. */
1115 return 1;
1116 }
1117
1118 void brw_barrier(struct brw_codegen *p, struct brw_reg src);
1119
1120 /* If/else/endif. Works by manipulating the execution flags on each
1121 * channel.
1122 */
1123 brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size);
1124 brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
1125 struct brw_reg src0, struct brw_reg src1);
1126
1127 void brw_ELSE(struct brw_codegen *p);
1128 void brw_ENDIF(struct brw_codegen *p);
1129
1130 /* DO/WHILE loops:
1131 */
1132 brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size);
1133
1134 brw_inst *brw_WHILE(struct brw_codegen *p);
1135
1136 brw_inst *brw_BREAK(struct brw_codegen *p);
1137 brw_inst *brw_CONT(struct brw_codegen *p);
1138 brw_inst *brw_HALT(struct brw_codegen *p);
1139
1140 /* Forward jumps:
1141 */
1142 void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx);
1143
1144 brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index,
1145 unsigned predicate_control);
1146
1147 void brw_NOP(struct brw_codegen *p);
1148
1149 void brw_WAIT(struct brw_codegen *p);
1150
1151 void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func);
1152
1153 /* Special case: there is never a destination, execution size will be
1154 * taken from src0:
1155 */
1156 void brw_CMP(struct brw_codegen *p,
1157 struct brw_reg dest,
1158 unsigned conditional,
1159 struct brw_reg src0,
1160 struct brw_reg src1);
1161
1162 void
1163 brw_untyped_atomic(struct brw_codegen *p,
1164 struct brw_reg dst,
1165 struct brw_reg payload,
1166 struct brw_reg surface,
1167 unsigned atomic_op,
1168 unsigned msg_length,
1169 bool response_expected,
1170 bool header_present);
1171
1172 void
1173 brw_untyped_surface_read(struct brw_codegen *p,
1174 struct brw_reg dst,
1175 struct brw_reg payload,
1176 struct brw_reg surface,
1177 unsigned msg_length,
1178 unsigned num_channels);
1179
1180 void
1181 brw_untyped_surface_write(struct brw_codegen *p,
1182 struct brw_reg payload,
1183 struct brw_reg surface,
1184 unsigned msg_length,
1185 unsigned num_channels,
1186 bool header_present);
1187
1188 void
1189 brw_memory_fence(struct brw_codegen *p,
1190 struct brw_reg dst,
1191 struct brw_reg src,
1192 enum opcode send_op,
1193 enum brw_message_target sfid,
1194 bool commit_enable,
1195 unsigned bti);
1196
1197 void
1198 brw_pixel_interpolator_query(struct brw_codegen *p,
1199 struct brw_reg dest,
1200 struct brw_reg mrf,
1201 bool noperspective,
1202 unsigned mode,
1203 struct brw_reg data,
1204 unsigned msg_length,
1205 unsigned response_length);
1206
1207 void
1208 brw_find_live_channel(struct brw_codegen *p,
1209 struct brw_reg dst,
1210 struct brw_reg mask);
1211
1212 void
1213 brw_broadcast(struct brw_codegen *p,
1214 struct brw_reg dst,
1215 struct brw_reg src,
1216 struct brw_reg idx);
1217
1218 void
1219 brw_float_controls_mode(struct brw_codegen *p,
1220 unsigned mode, unsigned mask);
1221
1222 /***********************************************************************
1223 * brw_eu_util.c:
1224 */
1225
1226 void brw_copy_indirect_to_indirect(struct brw_codegen *p,
1227 struct brw_indirect dst_ptr,
1228 struct brw_indirect src_ptr,
1229 unsigned count);
1230
1231 void brw_copy_from_indirect(struct brw_codegen *p,
1232 struct brw_reg dst,
1233 struct brw_indirect ptr,
1234 unsigned count);
1235
1236 void brw_copy4(struct brw_codegen *p,
1237 struct brw_reg dst,
1238 struct brw_reg src,
1239 unsigned count);
1240
1241 void brw_copy8(struct brw_codegen *p,
1242 struct brw_reg dst,
1243 struct brw_reg src,
1244 unsigned count);
1245
1246 void brw_math_invert( struct brw_codegen *p,
1247 struct brw_reg dst,
1248 struct brw_reg src);
1249
1250 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
1251
1252 void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn,
1253 unsigned desc, unsigned ex_desc);
1254
1255 static inline void
1256 brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc)
1257 {
1258 brw_set_desc_ex(p, insn, desc, 0);
1259 }
1260
1261 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
1262
1263 enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod);
1264 enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
1265
1266 /* brw_eu_compact.c */
1267 void brw_init_compaction_tables(const struct gen_device_info *devinfo);
1268 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
1269 struct disasm_info *disasm);
1270 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
1271 brw_inst *dst, brw_compact_inst *src);
1272 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
1273 brw_compact_inst *dst, const brw_inst *src);
1274
1275 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
1276 brw_inst *orig, brw_inst *uncompacted);
1277
1278 /* brw_eu_validate.c */
1279 bool brw_validate_instruction(const struct gen_device_info *devinfo,
1280 const brw_inst *inst, int offset,
1281 struct disasm_info *disasm);
1282 bool brw_validate_instructions(const struct gen_device_info *devinfo,
1283 const void *assembly, int start_offset, int end_offset,
1284 struct disasm_info *disasm);
1285
1286 static inline int
1287 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
1288 {
1289 brw_inst *insn = (brw_inst *)((char *)store + offset);
1290
1291 if (brw_inst_cmpt_control(devinfo, insn))
1292 return offset + 8;
1293 else
1294 return offset + 16;
1295 }
1296
1297 struct opcode_desc {
1298 unsigned ir;
1299 unsigned hw;
1300 const char *name;
1301 int nsrc;
1302 int ndst;
1303 int gens;
1304 };
1305
1306 const struct opcode_desc *
1307 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
1308
1309 const struct opcode_desc *
1310 brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw);
1311
1312 static inline unsigned
1313 brw_opcode_encode(const struct gen_device_info *devinfo, enum opcode opcode)
1314 {
1315 return brw_opcode_desc(devinfo, opcode)->hw;
1316 }
1317
1318 static inline enum opcode
1319 brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
1320 {
1321 const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
1322 return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
1323 }
1324
1325 static inline void
1326 brw_inst_set_opcode(const struct gen_device_info *devinfo,
1327 brw_inst *inst, enum opcode opcode)
1328 {
1329 brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
1330 }
1331
1332 static inline enum opcode
1333 brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
1334 {
1335 return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
1336 }
1337
1338 static inline bool
1339 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
1340 {
1341 const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1342 return desc && desc->nsrc == 3;
1343 }
1344
1345 /** Maximum SEND message length */
1346 #define BRW_MAX_MSG_LENGTH 15
1347
1348 /** First MRF register used by pull loads */
1349 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1350
1351 /** First MRF register used by spills */
1352 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
1353
1354 #ifdef __cplusplus
1355 }
1356 #endif
1357
1358 #endif