intel/eu: Include brw_compiler.h in brw_eu.h
[mesa.git] / src / intel / compiler / brw_eu.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_EU_H
34 #define BRW_EU_H
35
36 #include <stdbool.h>
37 #include <stdio.h>
38 #include "brw_inst.h"
39 #include "brw_compiler.h"
40 #include "brw_eu_defines.h"
41 #include "brw_reg.h"
42 #include "brw_disasm_info.h"
43
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47
48 #define BRW_EU_MAX_INSN_STACK 5
49
50 struct brw_insn_state {
51 /* One of BRW_EXECUTE_* */
52 unsigned exec_size:3;
53
54 /* Group in units of channels */
55 unsigned group:5;
56
57 /* Compression control on gen4-5 */
58 bool compressed:1;
59
60 /* One of BRW_MASK_* */
61 unsigned mask_control:1;
62
63 /* Scheduling info for Gen12+ */
64 struct tgl_swsb swsb;
65
66 bool saturate:1;
67
68 /* One of BRW_ALIGN_* */
69 unsigned access_mode:1;
70
71 /* One of BRW_PREDICATE_* */
72 enum brw_predicate predicate:4;
73
74 bool pred_inv:1;
75
76 /* Flag subreg. Bottom bit is subreg, top bit is reg */
77 unsigned flag_subreg:2;
78
79 bool acc_wr_control:1;
80 };
81
82
83 /* A helper for accessing the last instruction emitted. This makes it easy
84 * to set various bits on an instruction without having to create temporary
85 * variable and assign the emitted instruction to those.
86 */
87 #define brw_last_inst (&p->store[p->nr_insn - 1])
88
89 struct brw_codegen {
90 brw_inst *store;
91 int store_size;
92 unsigned nr_insn;
93 unsigned int next_insn_offset;
94
95 void *mem_ctx;
96
97 /* Allow clients to push/pop instruction state:
98 */
99 struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK];
100 struct brw_insn_state *current;
101
102 /** Whether or not the user wants automatic exec sizes
103 *
104 * If true, codegen will try to automatically infer the exec size of an
105 * instruction from the width of the destination register. If false, it
106 * will take whatever is set by brw_set_default_exec_size verbatim.
107 *
108 * This is set to true by default in brw_init_codegen.
109 */
110 bool automatic_exec_sizes;
111
112 bool single_program_flow;
113 const struct gen_device_info *devinfo;
114
115 /* Control flow stacks:
116 * - if_stack contains IF and ELSE instructions which must be patched
117 * (and popped) once the matching ENDIF instruction is encountered.
118 *
119 * Just store the instruction pointer(an index).
120 */
121 int *if_stack;
122 int if_stack_depth;
123 int if_stack_array_size;
124
125 /**
126 * loop_stack contains the instruction pointers of the starts of loops which
127 * must be patched (and popped) once the matching WHILE instruction is
128 * encountered.
129 */
130 int *loop_stack;
131 /**
132 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
133 * blocks they were popping out of, to fix up the mask stack. This tracks
134 * the IF/ENDIF nesting in each current nested loop level.
135 */
136 int *if_depth_in_loop;
137 int loop_stack_depth;
138 int loop_stack_array_size;
139 };
140
141 struct brw_label {
142 int offset;
143 int number;
144 struct brw_label *next;
145 };
146
147 void brw_pop_insn_state( struct brw_codegen *p );
148 void brw_push_insn_state( struct brw_codegen *p );
149 unsigned brw_get_default_exec_size(struct brw_codegen *p);
150 unsigned brw_get_default_group(struct brw_codegen *p);
151 unsigned brw_get_default_access_mode(struct brw_codegen *p);
152 struct tgl_swsb brw_get_default_swsb(struct brw_codegen *p);
153 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
154 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
155 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
156 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
157 void brw_inst_set_compression(const struct gen_device_info *devinfo,
158 brw_inst *inst, bool on);
159 void brw_set_default_compression(struct brw_codegen *p, bool on);
160 void brw_inst_set_group(const struct gen_device_info *devinfo,
161 brw_inst *inst, unsigned group);
162 void brw_set_default_group(struct brw_codegen *p, unsigned group);
163 void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
164 void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc);
165 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
166 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
167 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
168 void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
169
170 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
171 void *mem_ctx);
172 bool brw_has_jip(const struct gen_device_info *devinfo, enum opcode opcode);
173 bool brw_has_uip(const struct gen_device_info *devinfo, enum opcode opcode);
174 const struct brw_label *brw_find_label(const struct brw_label *root, int offset);
175 void brw_create_label(struct brw_label **labels, int offset, void *mem_ctx);
176 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
177 const struct brw_inst *inst, bool is_compacted,
178 int offset, const struct brw_label *root_label);
179 const struct brw_label *brw_label_assembly(const struct gen_device_info *devinfo,
180 const void *assembly, int start, int end,
181 void *mem_ctx);
182 void brw_disassemble_with_labels(const struct gen_device_info *devinfo,
183 const void *assembly, int start, int end, FILE *out);
184 void brw_disassemble(const struct gen_device_info *devinfo,
185 const void *assembly, int start, int end,
186 const struct brw_label *root_label, FILE *out);
187 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
188
189 bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
190 const char *identifier);
191
192 void brw_realign(struct brw_codegen *p, unsigned align);
193 int brw_append_data(struct brw_codegen *p, void *data,
194 unsigned size, unsigned align);
195 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
196 void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest);
197 void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
198
199 void gen6_resolve_implied_move(struct brw_codegen *p,
200 struct brw_reg *src,
201 unsigned msg_reg_nr);
202
203 /* Helpers for regular instructions:
204 */
205 #define ALU1(OP) \
206 brw_inst *brw_##OP(struct brw_codegen *p, \
207 struct brw_reg dest, \
208 struct brw_reg src0);
209
210 #define ALU2(OP) \
211 brw_inst *brw_##OP(struct brw_codegen *p, \
212 struct brw_reg dest, \
213 struct brw_reg src0, \
214 struct brw_reg src1);
215
216 #define ALU3(OP) \
217 brw_inst *brw_##OP(struct brw_codegen *p, \
218 struct brw_reg dest, \
219 struct brw_reg src0, \
220 struct brw_reg src1, \
221 struct brw_reg src2);
222
223 ALU1(MOV)
224 ALU2(SEL)
225 ALU1(NOT)
226 ALU2(AND)
227 ALU2(OR)
228 ALU2(XOR)
229 ALU2(SHR)
230 ALU2(SHL)
231 ALU1(DIM)
232 ALU2(ASR)
233 ALU2(ROL)
234 ALU2(ROR)
235 ALU3(CSEL)
236 ALU1(F32TO16)
237 ALU1(F16TO32)
238 ALU2(ADD)
239 ALU2(AVG)
240 ALU2(MUL)
241 ALU1(FRC)
242 ALU1(RNDD)
243 ALU1(RNDE)
244 ALU1(RNDU)
245 ALU1(RNDZ)
246 ALU2(MAC)
247 ALU2(MACH)
248 ALU1(LZD)
249 ALU2(DP4)
250 ALU2(DPH)
251 ALU2(DP3)
252 ALU2(DP2)
253 ALU2(LINE)
254 ALU2(PLN)
255 ALU3(MAD)
256 ALU3(LRP)
257 ALU1(BFREV)
258 ALU3(BFE)
259 ALU2(BFI1)
260 ALU3(BFI2)
261 ALU1(FBH)
262 ALU1(FBL)
263 ALU1(CBIT)
264 ALU2(ADDC)
265 ALU2(SUBB)
266 ALU2(MAC)
267
268 #undef ALU1
269 #undef ALU2
270 #undef ALU3
271
272
273 /* Helpers for SEND instruction:
274 */
275
276 /**
277 * Construct a message descriptor immediate with the specified common
278 * descriptor controls.
279 */
280 static inline uint32_t
281 brw_message_desc(const struct gen_device_info *devinfo,
282 unsigned msg_length,
283 unsigned response_length,
284 bool header_present)
285 {
286 if (devinfo->gen >= 5) {
287 return (SET_BITS(msg_length, 28, 25) |
288 SET_BITS(response_length, 24, 20) |
289 SET_BITS(header_present, 19, 19));
290 } else {
291 return (SET_BITS(msg_length, 23, 20) |
292 SET_BITS(response_length, 19, 16));
293 }
294 }
295
296 static inline unsigned
297 brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
298 {
299 if (devinfo->gen >= 5)
300 return GET_BITS(desc, 28, 25);
301 else
302 return GET_BITS(desc, 23, 20);
303 }
304
305 static inline unsigned
306 brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
307 {
308 if (devinfo->gen >= 5)
309 return GET_BITS(desc, 24, 20);
310 else
311 return GET_BITS(desc, 19, 16);
312 }
313
314 static inline bool
315 brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
316 uint32_t desc)
317 {
318 assert(devinfo->gen >= 5);
319 return GET_BITS(desc, 19, 19);
320 }
321
322 static inline unsigned
323 brw_message_ex_desc(UNUSED const struct gen_device_info *devinfo,
324 unsigned ex_msg_length)
325 {
326 return SET_BITS(ex_msg_length, 9, 6);
327 }
328
329 static inline unsigned
330 brw_message_ex_desc_ex_mlen(UNUSED const struct gen_device_info *devinfo,
331 uint32_t ex_desc)
332 {
333 return GET_BITS(ex_desc, 9, 6);
334 }
335
336 static inline uint32_t
337 brw_urb_desc(const struct gen_device_info *devinfo,
338 unsigned msg_type,
339 bool per_slot_offset_present,
340 bool channel_mask_present,
341 unsigned global_offset)
342 {
343 if (devinfo->gen >= 8) {
344 return (SET_BITS(per_slot_offset_present, 17, 17) |
345 SET_BITS(channel_mask_present, 15, 15) |
346 SET_BITS(global_offset, 14, 4) |
347 SET_BITS(msg_type, 3, 0));
348 } else if (devinfo->gen >= 7) {
349 assert(!channel_mask_present);
350 return (SET_BITS(per_slot_offset_present, 16, 16) |
351 SET_BITS(global_offset, 13, 3) |
352 SET_BITS(msg_type, 3, 0));
353 } else {
354 unreachable("unhandled URB write generation");
355 }
356 }
357
358 static inline uint32_t
359 brw_urb_desc_msg_type(ASSERTED const struct gen_device_info *devinfo,
360 uint32_t desc)
361 {
362 assert(devinfo->gen >= 7);
363 return GET_BITS(desc, 3, 0);
364 }
365
366 /**
367 * Construct a message descriptor immediate with the specified sampler
368 * function controls.
369 */
370 static inline uint32_t
371 brw_sampler_desc(const struct gen_device_info *devinfo,
372 unsigned binding_table_index,
373 unsigned sampler,
374 unsigned msg_type,
375 unsigned simd_mode,
376 unsigned return_format)
377 {
378 const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
379 SET_BITS(sampler, 11, 8));
380 if (devinfo->gen >= 7)
381 return (desc | SET_BITS(msg_type, 16, 12) |
382 SET_BITS(simd_mode, 18, 17));
383 else if (devinfo->gen >= 5)
384 return (desc | SET_BITS(msg_type, 15, 12) |
385 SET_BITS(simd_mode, 17, 16));
386 else if (devinfo->is_g4x)
387 return desc | SET_BITS(msg_type, 15, 12);
388 else
389 return (desc | SET_BITS(return_format, 13, 12) |
390 SET_BITS(msg_type, 15, 14));
391 }
392
393 static inline unsigned
394 brw_sampler_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
395 uint32_t desc)
396 {
397 return GET_BITS(desc, 7, 0);
398 }
399
400 static inline unsigned
401 brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t desc)
402 {
403 return GET_BITS(desc, 11, 8);
404 }
405
406 static inline unsigned
407 brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
408 {
409 if (devinfo->gen >= 7)
410 return GET_BITS(desc, 16, 12);
411 else if (devinfo->gen >= 5 || devinfo->is_g4x)
412 return GET_BITS(desc, 15, 12);
413 else
414 return GET_BITS(desc, 15, 14);
415 }
416
417 static inline unsigned
418 brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
419 {
420 assert(devinfo->gen >= 5);
421 if (devinfo->gen >= 7)
422 return GET_BITS(desc, 18, 17);
423 else
424 return GET_BITS(desc, 17, 16);
425 }
426
427 static inline unsigned
428 brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
429 uint32_t desc)
430 {
431 assert(devinfo->gen == 4 && !devinfo->is_g4x);
432 return GET_BITS(desc, 13, 12);
433 }
434
435 /**
436 * Construct a message descriptor for the dataport
437 */
438 static inline uint32_t
439 brw_dp_desc(const struct gen_device_info *devinfo,
440 unsigned binding_table_index,
441 unsigned msg_type,
442 unsigned msg_control)
443 {
444 /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
445 * helpers instead.
446 */
447 assert(devinfo->gen >= 6);
448 const unsigned desc = SET_BITS(binding_table_index, 7, 0);
449 if (devinfo->gen >= 8) {
450 return (desc | SET_BITS(msg_control, 13, 8) |
451 SET_BITS(msg_type, 18, 14));
452 } else if (devinfo->gen >= 7) {
453 return (desc | SET_BITS(msg_control, 13, 8) |
454 SET_BITS(msg_type, 17, 14));
455 } else {
456 return (desc | SET_BITS(msg_control, 12, 8) |
457 SET_BITS(msg_type, 16, 13));
458 }
459 }
460
461 static inline unsigned
462 brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
463 uint32_t desc)
464 {
465 return GET_BITS(desc, 7, 0);
466 }
467
468 static inline unsigned
469 brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
470 {
471 assert(devinfo->gen >= 6);
472 if (devinfo->gen >= 8)
473 return GET_BITS(desc, 18, 14);
474 else if (devinfo->gen >= 7)
475 return GET_BITS(desc, 17, 14);
476 else
477 return GET_BITS(desc, 16, 13);
478 }
479
480 static inline unsigned
481 brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
482 {
483 assert(devinfo->gen >= 6);
484 if (devinfo->gen >= 7)
485 return GET_BITS(desc, 13, 8);
486 else
487 return GET_BITS(desc, 12, 8);
488 }
489
490 /**
491 * Construct a message descriptor immediate with the specified dataport read
492 * function controls.
493 */
494 static inline uint32_t
495 brw_dp_read_desc(const struct gen_device_info *devinfo,
496 unsigned binding_table_index,
497 unsigned msg_control,
498 unsigned msg_type,
499 unsigned target_cache)
500 {
501 if (devinfo->gen >= 6)
502 return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
503 else if (devinfo->gen >= 5 || devinfo->is_g4x)
504 return (SET_BITS(binding_table_index, 7, 0) |
505 SET_BITS(msg_control, 10, 8) |
506 SET_BITS(msg_type, 13, 11) |
507 SET_BITS(target_cache, 15, 14));
508 else
509 return (SET_BITS(binding_table_index, 7, 0) |
510 SET_BITS(msg_control, 11, 8) |
511 SET_BITS(msg_type, 13, 12) |
512 SET_BITS(target_cache, 15, 14));
513 }
514
515 static inline unsigned
516 brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
517 {
518 if (devinfo->gen >= 6)
519 return brw_dp_desc_msg_type(devinfo, desc);
520 else if (devinfo->gen >= 5 || devinfo->is_g4x)
521 return GET_BITS(desc, 13, 11);
522 else
523 return GET_BITS(desc, 13, 12);
524 }
525
526 static inline unsigned
527 brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
528 uint32_t desc)
529 {
530 if (devinfo->gen >= 6)
531 return brw_dp_desc_msg_control(devinfo, desc);
532 else if (devinfo->gen >= 5 || devinfo->is_g4x)
533 return GET_BITS(desc, 10, 8);
534 else
535 return GET_BITS(desc, 11, 8);
536 }
537
538 /**
539 * Construct a message descriptor immediate with the specified dataport write
540 * function controls.
541 */
542 static inline uint32_t
543 brw_dp_write_desc(const struct gen_device_info *devinfo,
544 unsigned binding_table_index,
545 unsigned msg_control,
546 unsigned msg_type,
547 unsigned last_render_target,
548 unsigned send_commit_msg)
549 {
550 assert(devinfo->gen <= 6 || !send_commit_msg);
551 if (devinfo->gen >= 6)
552 return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) |
553 SET_BITS(last_render_target, 12, 12) |
554 SET_BITS(send_commit_msg, 17, 17);
555 else
556 return (SET_BITS(binding_table_index, 7, 0) |
557 SET_BITS(msg_control, 11, 8) |
558 SET_BITS(last_render_target, 11, 11) |
559 SET_BITS(msg_type, 14, 12) |
560 SET_BITS(send_commit_msg, 15, 15));
561 }
562
563 static inline unsigned
564 brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
565 uint32_t desc)
566 {
567 if (devinfo->gen >= 6)
568 return brw_dp_desc_msg_type(devinfo, desc);
569 else
570 return GET_BITS(desc, 14, 12);
571 }
572
573 static inline unsigned
574 brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
575 uint32_t desc)
576 {
577 if (devinfo->gen >= 6)
578 return brw_dp_desc_msg_control(devinfo, desc);
579 else
580 return GET_BITS(desc, 11, 8);
581 }
582
583 static inline bool
584 brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
585 uint32_t desc)
586 {
587 if (devinfo->gen >= 6)
588 return GET_BITS(desc, 12, 12);
589 else
590 return GET_BITS(desc, 11, 11);
591 }
592
593 static inline bool
594 brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
595 uint32_t desc)
596 {
597 assert(devinfo->gen <= 6);
598 if (devinfo->gen >= 6)
599 return GET_BITS(desc, 17, 17);
600 else
601 return GET_BITS(desc, 15, 15);
602 }
603
604 /**
605 * Construct a message descriptor immediate with the specified dataport
606 * surface function controls.
607 */
608 static inline uint32_t
609 brw_dp_surface_desc(const struct gen_device_info *devinfo,
610 unsigned msg_type,
611 unsigned msg_control)
612 {
613 assert(devinfo->gen >= 7);
614 /* We'll OR in the binding table index later */
615 return brw_dp_desc(devinfo, 0, msg_type, msg_control);
616 }
617
618 static inline uint32_t
619 brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
620 unsigned exec_size, /**< 0 for SIMD4x2 */
621 unsigned atomic_op,
622 bool response_expected)
623 {
624 assert(exec_size <= 8 || exec_size == 16);
625
626 unsigned msg_type;
627 if (devinfo->gen >= 8 || devinfo->is_haswell) {
628 if (exec_size > 0) {
629 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
630 } else {
631 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
632 }
633 } else {
634 msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
635 }
636
637 const unsigned msg_control =
638 SET_BITS(atomic_op, 3, 0) |
639 SET_BITS(0 < exec_size && exec_size <= 8, 4, 4) |
640 SET_BITS(response_expected, 5, 5);
641
642 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
643 }
644
645 static inline uint32_t
646 brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
647 unsigned exec_size,
648 unsigned atomic_op,
649 bool response_expected)
650 {
651 assert(exec_size <= 8 || exec_size == 16);
652 assert(devinfo->gen >= 9);
653
654 assert(exec_size > 0);
655 const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
656
657 const unsigned msg_control =
658 SET_BITS(atomic_op, 1, 0) |
659 SET_BITS(exec_size <= 8, 4, 4) |
660 SET_BITS(response_expected, 5, 5);
661
662 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
663 }
664
665 static inline unsigned
666 brw_mdc_cmask(unsigned num_channels)
667 {
668 /* See also MDC_CMASK in the SKL PRM Vol 2d. */
669 return 0xf & (0xf << num_channels);
670 }
671
672 static inline uint32_t
673 brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
674 unsigned exec_size, /**< 0 for SIMD4x2 */
675 unsigned num_channels,
676 bool write)
677 {
678 assert(exec_size <= 8 || exec_size == 16);
679
680 unsigned msg_type;
681 if (write) {
682 if (devinfo->gen >= 8 || devinfo->is_haswell) {
683 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
684 } else {
685 msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
686 }
687 } else {
688 /* Read */
689 if (devinfo->gen >= 8 || devinfo->is_haswell) {
690 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
691 } else {
692 msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
693 }
694 }
695
696 /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
697 if (write && devinfo->gen == 7 && !devinfo->is_haswell && exec_size == 0)
698 exec_size = 8;
699
700 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
701 const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
702 exec_size <= 8 ? 2 : 1;
703
704 const unsigned msg_control =
705 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
706 SET_BITS(simd_mode, 5, 4);
707
708 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
709 }
710
711 static inline unsigned
712 brw_mdc_ds(unsigned bit_size)
713 {
714 switch (bit_size) {
715 case 8:
716 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
717 case 16:
718 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
719 case 32:
720 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
721 default:
722 unreachable("Unsupported bit_size for byte scattered messages");
723 }
724 }
725
726 static inline uint32_t
727 brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
728 unsigned exec_size,
729 unsigned bit_size,
730 bool write)
731 {
732 assert(exec_size <= 8 || exec_size == 16);
733
734 assert(devinfo->gen > 7 || devinfo->is_haswell);
735 const unsigned msg_type =
736 write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
737 HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
738
739 assert(exec_size > 0);
740 const unsigned msg_control =
741 SET_BITS(exec_size == 16, 0, 0) |
742 SET_BITS(brw_mdc_ds(bit_size), 3, 2);
743
744 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
745 }
746
747 static inline uint32_t
748 brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
749 unsigned exec_size,
750 bool write)
751 {
752 assert(exec_size == 8 || exec_size == 16);
753
754 unsigned msg_type;
755 if (write) {
756 if (devinfo->gen >= 6) {
757 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
758 } else {
759 msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
760 }
761 } else {
762 if (devinfo->gen >= 7) {
763 msg_type = GEN7_DATAPORT_DC_DWORD_SCATTERED_READ;
764 } else if (devinfo->gen > 4 || devinfo->is_g4x) {
765 msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
766 } else {
767 msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
768 }
769 }
770
771 const unsigned msg_control =
772 SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */
773 SET_BITS(exec_size == 16, 0, 0);
774
775 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
776 }
777
778 static inline uint32_t
779 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
780 unsigned exec_size, /**< 0 for SIMD4x2 */
781 unsigned num_channels,
782 bool write)
783 {
784 assert(exec_size <= 8 || exec_size == 16);
785 assert(devinfo->gen >= 8);
786
787 unsigned msg_type =
788 write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
789 GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
790
791 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
792 const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
793 exec_size <= 8 ? 2 : 1;
794
795 const unsigned msg_control =
796 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
797 SET_BITS(simd_mode, 5, 4);
798
799 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
800 msg_type, msg_control);
801 }
802
803 /**
804 * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
805 * Skylake PRM).
806 */
807 static inline uint32_t
808 brw_mdc_a64_ds(unsigned elems)
809 {
810 switch (elems) {
811 case 1: return 0;
812 case 2: return 1;
813 case 4: return 2;
814 case 8: return 3;
815 default:
816 unreachable("Unsupported elmeent count for A64 scattered message");
817 }
818 }
819
820 static inline uint32_t
821 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
822 unsigned exec_size, /**< 0 for SIMD4x2 */
823 unsigned bit_size,
824 bool write)
825 {
826 assert(exec_size <= 8 || exec_size == 16);
827 assert(devinfo->gen >= 8);
828
829 unsigned msg_type =
830 write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
831 GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
832
833 const unsigned msg_control =
834 SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
835 SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) |
836 SET_BITS(exec_size == 16, 4, 4);
837
838 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
839 msg_type, msg_control);
840 }
841
842 static inline uint32_t
843 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
844 ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */
845 unsigned bit_size,
846 unsigned atomic_op,
847 bool response_expected)
848 {
849 assert(exec_size == 8);
850 assert(devinfo->gen >= 8);
851 assert(bit_size == 32 || bit_size == 64);
852
853 const unsigned msg_type = GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
854
855 const unsigned msg_control =
856 SET_BITS(atomic_op, 3, 0) |
857 SET_BITS(bit_size == 64, 4, 4) |
858 SET_BITS(response_expected, 5, 5);
859
860 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
861 msg_type, msg_control);
862 }
863
864 static inline uint32_t
865 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
866 ASSERTED unsigned exec_size,
867 unsigned atomic_op,
868 bool response_expected)
869 {
870 assert(exec_size == 8);
871 assert(devinfo->gen >= 9);
872
873 assert(exec_size > 0);
874 const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP;
875
876 const unsigned msg_control =
877 SET_BITS(atomic_op, 1, 0) |
878 SET_BITS(response_expected, 5, 5);
879
880 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
881 msg_type, msg_control);
882 }
883
884 static inline uint32_t
885 brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
886 unsigned exec_size,
887 unsigned exec_group,
888 unsigned atomic_op,
889 bool response_expected)
890 {
891 assert(exec_size > 0 || exec_group == 0);
892 assert(exec_group % 8 == 0);
893
894 unsigned msg_type;
895 if (devinfo->gen >= 8 || devinfo->is_haswell) {
896 if (exec_size == 0) {
897 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
898 } else {
899 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
900 }
901 } else {
902 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
903 assert(exec_size > 0);
904 msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
905 }
906
907 const bool high_sample_mask = (exec_group / 8) % 2 == 1;
908
909 const unsigned msg_control =
910 SET_BITS(atomic_op, 3, 0) |
911 SET_BITS(high_sample_mask, 4, 4) |
912 SET_BITS(response_expected, 5, 5);
913
914 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
915 }
916
917 static inline uint32_t
918 brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
919 unsigned exec_size,
920 unsigned exec_group,
921 unsigned num_channels,
922 bool write)
923 {
924 assert(exec_size > 0 || exec_group == 0);
925 assert(exec_group % 8 == 0);
926
927 /* Typed surface reads and writes don't support SIMD16 */
928 assert(exec_size <= 8);
929
930 unsigned msg_type;
931 if (write) {
932 if (devinfo->gen >= 8 || devinfo->is_haswell) {
933 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
934 } else {
935 msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
936 }
937 } else {
938 if (devinfo->gen >= 8 || devinfo->is_haswell) {
939 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
940 } else {
941 msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
942 }
943 }
944
945 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
946 unsigned msg_control;
947 if (devinfo->gen >= 8 || devinfo->is_haswell) {
948 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
949 const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
950 1 + ((exec_group / 8) % 2);
951
952 msg_control =
953 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
954 SET_BITS(slot_group, 5, 4);
955 } else {
956 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
957 assert(exec_size > 0);
958 const unsigned slot_group = ((exec_group / 8) % 2);
959
960 msg_control =
961 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
962 SET_BITS(slot_group, 5, 5);
963 }
964
965 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
966 }
967
968 /**
969 * Construct a message descriptor immediate with the specified pixel
970 * interpolator function controls.
971 */
972 static inline uint32_t
973 brw_pixel_interp_desc(UNUSED const struct gen_device_info *devinfo,
974 unsigned msg_type,
975 bool noperspective,
976 unsigned simd_mode,
977 unsigned slot_group)
978 {
979 return (SET_BITS(slot_group, 11, 11) |
980 SET_BITS(msg_type, 13, 12) |
981 SET_BITS(!!noperspective, 14, 14) |
982 SET_BITS(simd_mode, 16, 16));
983 }
984
985 void brw_urb_WRITE(struct brw_codegen *p,
986 struct brw_reg dest,
987 unsigned msg_reg_nr,
988 struct brw_reg src0,
989 enum brw_urb_write_flags flags,
990 unsigned msg_length,
991 unsigned response_length,
992 unsigned offset,
993 unsigned swizzle);
994
995 /**
996 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
997 * desc. If \p desc is not an immediate it will be transparently loaded to an
998 * address register using an OR instruction.
999 */
1000 void
1001 brw_send_indirect_message(struct brw_codegen *p,
1002 unsigned sfid,
1003 struct brw_reg dst,
1004 struct brw_reg payload,
1005 struct brw_reg desc,
1006 unsigned desc_imm,
1007 bool eot);
1008
1009 void
1010 brw_send_indirect_split_message(struct brw_codegen *p,
1011 unsigned sfid,
1012 struct brw_reg dst,
1013 struct brw_reg payload0,
1014 struct brw_reg payload1,
1015 struct brw_reg desc,
1016 unsigned desc_imm,
1017 struct brw_reg ex_desc,
1018 unsigned ex_desc_imm,
1019 bool eot);
1020
1021 void brw_ff_sync(struct brw_codegen *p,
1022 struct brw_reg dest,
1023 unsigned msg_reg_nr,
1024 struct brw_reg src0,
1025 bool allocate,
1026 unsigned response_length,
1027 bool eot);
1028
1029 void brw_svb_write(struct brw_codegen *p,
1030 struct brw_reg dest,
1031 unsigned msg_reg_nr,
1032 struct brw_reg src0,
1033 unsigned binding_table_index,
1034 bool send_commit_msg);
1035
1036 brw_inst *brw_fb_WRITE(struct brw_codegen *p,
1037 struct brw_reg payload,
1038 struct brw_reg implied_header,
1039 unsigned msg_control,
1040 unsigned binding_table_index,
1041 unsigned msg_length,
1042 unsigned response_length,
1043 bool eot,
1044 bool last_render_target,
1045 bool header_present);
1046
1047 brw_inst *gen9_fb_READ(struct brw_codegen *p,
1048 struct brw_reg dst,
1049 struct brw_reg payload,
1050 unsigned binding_table_index,
1051 unsigned msg_length,
1052 unsigned response_length,
1053 bool per_sample);
1054
1055 void brw_SAMPLE(struct brw_codegen *p,
1056 struct brw_reg dest,
1057 unsigned msg_reg_nr,
1058 struct brw_reg src0,
1059 unsigned binding_table_index,
1060 unsigned sampler,
1061 unsigned msg_type,
1062 unsigned response_length,
1063 unsigned msg_length,
1064 unsigned header_present,
1065 unsigned simd_mode,
1066 unsigned return_format);
1067
1068 void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
1069 struct brw_reg header,
1070 struct brw_reg sampler_index);
1071
1072 void gen4_math(struct brw_codegen *p,
1073 struct brw_reg dest,
1074 unsigned function,
1075 unsigned msg_reg_nr,
1076 struct brw_reg src,
1077 unsigned precision );
1078
1079 void gen6_math(struct brw_codegen *p,
1080 struct brw_reg dest,
1081 unsigned function,
1082 struct brw_reg src0,
1083 struct brw_reg src1);
1084
1085 void brw_oword_block_read(struct brw_codegen *p,
1086 struct brw_reg dest,
1087 struct brw_reg mrf,
1088 uint32_t offset,
1089 uint32_t bind_table_index);
1090
1091 unsigned brw_scratch_surface_idx(const struct brw_codegen *p);
1092
1093 void brw_oword_block_read_scratch(struct brw_codegen *p,
1094 struct brw_reg dest,
1095 struct brw_reg mrf,
1096 int num_regs,
1097 unsigned offset);
1098
1099 void brw_oword_block_write_scratch(struct brw_codegen *p,
1100 struct brw_reg mrf,
1101 int num_regs,
1102 unsigned offset);
1103
1104 void gen7_block_read_scratch(struct brw_codegen *p,
1105 struct brw_reg dest,
1106 int num_regs,
1107 unsigned offset);
1108
1109 void brw_shader_time_add(struct brw_codegen *p,
1110 struct brw_reg payload,
1111 uint32_t surf_index);
1112
1113 /**
1114 * Return the generation-specific jump distance scaling factor.
1115 *
1116 * Given the number of instructions to jump, we need to scale by
1117 * some number to obtain the actual jump distance to program in an
1118 * instruction.
1119 */
1120 static inline unsigned
1121 brw_jump_scale(const struct gen_device_info *devinfo)
1122 {
1123 /* Broadwell measures jump targets in bytes. */
1124 if (devinfo->gen >= 8)
1125 return 16;
1126
1127 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1128 * (to support compaction), so each 128-bit instruction requires 2 chunks.
1129 */
1130 if (devinfo->gen >= 5)
1131 return 2;
1132
1133 /* Gen4 simply uses the number of 128-bit instructions. */
1134 return 1;
1135 }
1136
1137 void brw_barrier(struct brw_codegen *p, struct brw_reg src);
1138
1139 /* If/else/endif. Works by manipulating the execution flags on each
1140 * channel.
1141 */
1142 brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size);
1143 brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
1144 struct brw_reg src0, struct brw_reg src1);
1145
1146 void brw_ELSE(struct brw_codegen *p);
1147 void brw_ENDIF(struct brw_codegen *p);
1148
1149 /* DO/WHILE loops:
1150 */
1151 brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size);
1152
1153 brw_inst *brw_WHILE(struct brw_codegen *p);
1154
1155 brw_inst *brw_BREAK(struct brw_codegen *p);
1156 brw_inst *brw_CONT(struct brw_codegen *p);
1157 brw_inst *brw_HALT(struct brw_codegen *p);
1158
1159 /* Forward jumps:
1160 */
1161 void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx);
1162
1163 brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index,
1164 unsigned predicate_control);
1165
1166 void brw_NOP(struct brw_codegen *p);
1167
1168 void brw_WAIT(struct brw_codegen *p);
1169
1170 void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func);
1171
1172 /* Special case: there is never a destination, execution size will be
1173 * taken from src0:
1174 */
1175 void brw_CMP(struct brw_codegen *p,
1176 struct brw_reg dest,
1177 unsigned conditional,
1178 struct brw_reg src0,
1179 struct brw_reg src1);
1180
1181 void
1182 brw_untyped_atomic(struct brw_codegen *p,
1183 struct brw_reg dst,
1184 struct brw_reg payload,
1185 struct brw_reg surface,
1186 unsigned atomic_op,
1187 unsigned msg_length,
1188 bool response_expected,
1189 bool header_present);
1190
1191 void
1192 brw_untyped_surface_read(struct brw_codegen *p,
1193 struct brw_reg dst,
1194 struct brw_reg payload,
1195 struct brw_reg surface,
1196 unsigned msg_length,
1197 unsigned num_channels);
1198
1199 void
1200 brw_untyped_surface_write(struct brw_codegen *p,
1201 struct brw_reg payload,
1202 struct brw_reg surface,
1203 unsigned msg_length,
1204 unsigned num_channels,
1205 bool header_present);
1206
1207 void
1208 brw_memory_fence(struct brw_codegen *p,
1209 struct brw_reg dst,
1210 struct brw_reg src,
1211 enum opcode send_op,
1212 enum brw_message_target sfid,
1213 bool commit_enable,
1214 unsigned bti);
1215
1216 void
1217 brw_pixel_interpolator_query(struct brw_codegen *p,
1218 struct brw_reg dest,
1219 struct brw_reg mrf,
1220 bool noperspective,
1221 unsigned mode,
1222 struct brw_reg data,
1223 unsigned msg_length,
1224 unsigned response_length);
1225
1226 void
1227 brw_find_live_channel(struct brw_codegen *p,
1228 struct brw_reg dst,
1229 struct brw_reg mask);
1230
1231 void
1232 brw_broadcast(struct brw_codegen *p,
1233 struct brw_reg dst,
1234 struct brw_reg src,
1235 struct brw_reg idx);
1236
1237 void
1238 brw_float_controls_mode(struct brw_codegen *p,
1239 unsigned mode, unsigned mask);
1240
1241 /***********************************************************************
1242 * brw_eu_util.c:
1243 */
1244
1245 void brw_copy_indirect_to_indirect(struct brw_codegen *p,
1246 struct brw_indirect dst_ptr,
1247 struct brw_indirect src_ptr,
1248 unsigned count);
1249
1250 void brw_copy_from_indirect(struct brw_codegen *p,
1251 struct brw_reg dst,
1252 struct brw_indirect ptr,
1253 unsigned count);
1254
1255 void brw_copy4(struct brw_codegen *p,
1256 struct brw_reg dst,
1257 struct brw_reg src,
1258 unsigned count);
1259
1260 void brw_copy8(struct brw_codegen *p,
1261 struct brw_reg dst,
1262 struct brw_reg src,
1263 unsigned count);
1264
1265 void brw_math_invert( struct brw_codegen *p,
1266 struct brw_reg dst,
1267 struct brw_reg src);
1268
1269 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
1270
1271 void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn,
1272 unsigned desc, unsigned ex_desc);
1273
1274 static inline void
1275 brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc)
1276 {
1277 brw_set_desc_ex(p, insn, desc, 0);
1278 }
1279
1280 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
1281
1282 enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod);
1283 enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
1284
1285 /* brw_eu_compact.c */
1286 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
1287 struct disasm_info *disasm);
1288 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
1289 brw_inst *dst, brw_compact_inst *src);
1290 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
1291 brw_compact_inst *dst, const brw_inst *src);
1292
1293 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
1294 brw_inst *orig, brw_inst *uncompacted);
1295
1296 /* brw_eu_validate.c */
1297 bool brw_validate_instruction(const struct gen_device_info *devinfo,
1298 const brw_inst *inst, int offset,
1299 struct disasm_info *disasm);
1300 bool brw_validate_instructions(const struct gen_device_info *devinfo,
1301 const void *assembly, int start_offset, int end_offset,
1302 struct disasm_info *disasm);
1303
1304 static inline int
1305 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
1306 {
1307 brw_inst *insn = (brw_inst *)((char *)store + offset);
1308
1309 if (brw_inst_cmpt_control(devinfo, insn))
1310 return offset + 8;
1311 else
1312 return offset + 16;
1313 }
1314
1315 struct opcode_desc {
1316 unsigned ir;
1317 unsigned hw;
1318 const char *name;
1319 int nsrc;
1320 int ndst;
1321 int gens;
1322 };
1323
1324 const struct opcode_desc *
1325 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
1326
1327 const struct opcode_desc *
1328 brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw);
1329
1330 static inline unsigned
1331 brw_opcode_encode(const struct gen_device_info *devinfo, enum opcode opcode)
1332 {
1333 return brw_opcode_desc(devinfo, opcode)->hw;
1334 }
1335
1336 static inline enum opcode
1337 brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
1338 {
1339 const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
1340 return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
1341 }
1342
1343 static inline void
1344 brw_inst_set_opcode(const struct gen_device_info *devinfo,
1345 brw_inst *inst, enum opcode opcode)
1346 {
1347 brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
1348 }
1349
1350 static inline enum opcode
1351 brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
1352 {
1353 return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
1354 }
1355
1356 static inline bool
1357 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
1358 {
1359 const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1360 return desc && desc->nsrc == 3;
1361 }
1362
1363 /** Maximum SEND message length */
1364 #define BRW_MAX_MSG_LENGTH 15
1365
1366 /** First MRF register used by pull loads */
1367 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1368
1369 /** First MRF register used by spills */
1370 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
1371
1372 #ifdef __cplusplus
1373 }
1374 #endif
1375
1376 #endif